Sony SS-HQ1 Application Notes page 28

Countermeasures for the CXD3172AR and Surrounding Areas
1. For the power supply of AVD 1-6 (pins 2, 21, 29, 55, 56, and 74) and SVD 1 and 2 (pins 50 and 100),
connect LC filters by the source to prevent crosstalk from other circuits causing interference.
Additionally, connect bypass capacitors between each power supply pin and ground.
2. For the power supply of VDD, connect LC filters by the source to prevent crosstalk from other circuits
causing interference. Additionally, VDD1 (pin14), VDD2 (pin45), and VDD4 (pin95) which are a power
supply are unified to the same VDD as noise countermeasures. (See the application circuit diagram.)
Additionally, connect bypass capacitors between each pin and ground.
3. VRT, VIN, and VRB (pins 1, 3, and 5, respectively) are ADC input pins, so make their signal lines with
the CXA2096N as short as possible. Noise may be generated if these ADC patterns are too close to a
high-speed pulse (H1, H2, RG, XSHP, XSHD, or XSR), oscillator or oscillator circuit pattern, so be sure
to take this into consideration during layout design.
4. RG, H1, and H2 (pins 19, 22, and 23, respectively) are output pins for the reset gate pulse and
horizontal register transfer pulse. If there is overshoot or undershoot in the waveform, it may cause
noise. To deal with it, insert a serial resistance of approximately 100 ohms for each. Additionally, set the
parameters to adjust waveform duty, delay, and drivability to match the waveform conditions of the
clock driving the CCD.
If connectors are used in the connection with the CCD element, use a ground shield between signals to
prevent signal degradation. For the connectors, provide many ground pins to strengthen the earth
coupling.
Furthermore, shorten the H1 and H2 wiring length between ICs as much as possible. Before use, make
sure that the H1 and H2 amplitudes conform to the CCD specifications.
5. XSHP, XSHD, and XRS (pins 28, 27, and 25, respectively) are output pins for sample hold pulse to the
CXA2096N. If there is overshoot or undershoot in the waveform, it may cause noise. To deal with it,
insert a serial resistance of approximately 100 ohms for each. Additionally, set the parameters to adjust
duty, delay, and drivability so that the sample hold waveform matches the CCD input waveform.
Arrange the CXD2096N and CCD element on the same board if possible. Use a ground shield between
signals to prevent signal degradation.
If separate boards are used, provide many connector ground pins to strengthen the earth coupling as
an additional countermeasure.
6. If PLL (the phase comparator) is used by means of phase comparator output PCOMP (pin 42) and
system drive clock input MCK (pin 43), make the signal line of the PLL oscillator circuit as short as
possible and surround it with a ground shield to make it less susceptible to nearby circuits.
We also recommend positioning the PLL oscillator circuit and the board's inner layer away from other
circuits and removing the board's inner layer pattern so they are not affected by floating capacitance.
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- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005