Vs Lock Mode (Vsl-S) - Sony SS-HQ1 Application Notes

12.2.8. VS Lock Mode (VSL-S)

VS Lock (VSL-S) synchronizes the camera vertical and horizontal phases to the external VD/HD signal.
A reset operation is performed in the vertical direction, and a PLL operation is performed in the horizontal
direction. The SGMODE setting is A[h]. (See Table 12.2-5.)
This is not supported in auto mode (ATMODEON=1[h]).
System Configuration
The master signal is external VD/HD (EXT-VID/EXT-HD).
EXT-VD resets the CXD3172AR's internal vertical direction counter.
The EXT-HD signal and MCK-frequency-divided HD (MCK-HD) signal are phase-compared inside the
CXD3172AR. In addition, the 27.000MHz clock is used for input to ECK (pin 88). In this case, the MODESEL
(operation mode) setting is as shown in Table 12.2-13. We recommend using X'tal oscillation for the VCXO on
the MCK side. A system block diagram is shown in Fig 12.2-26. The external input signal is presented in Table
12.2-25.
(X'tal)
VCXO
3.3V
Table 12.2-25 External Input Signal (VS Lock (VSL-S) mode)
LPF
(27.000MHz)
(H-PLL)
42 86
MCK
43
CXD3172AR
57 58
Fig 12.2-26 VS(VSL-S) mode
Pin Name(Pin No)
S0(44pin) EXT-VD(3.3Vpp: digital signal)
S1(46pin) EXT-HD(3.3Vpp: digital signal)
EXVIDEOY(57pin)
3.3V connection
EXVIDEO(58pin)
X'tal
87 88
47
S2
48
S3
49
S4
44 46
I/O signals
213
- SS-HQ1 Application Notes -
Ver.1.0.0 January 7, 2005
EXT-HD
EXT-VD