Mitsubishi Electric MELSEC-Q Structured Programming Manual page 30

FXCPU Structured Programming Manual
[Device & Common]
4. FX /FX /FX
1S 1N
The memory type varies depending on the PLC, and is classified as follows by the device initialization timing.
A: Latched type memory
B: Special device and index memory
C: Non-latched type memory
*1. Some devices are cleared when the PLC mode switches from STOP to RUN.
1) Types of program memory
Parameter
Sequence program
Comment
File register
*1. The battery is not used when an optional EEPROM or EPROM memory is attached.
2) Types of word device memory
Data register (D)
Index register (V and Z)
Timer current value
register (T)
Counter current value
register (C)
Clock data
*1. Attach a memory board having the clock function when the clock function is required in the FX
Series.
28
/FX /FX PLCs
2N 1NC 2NC
Classification
A1: Backed up by battery
A2: Backed up by EEPROM
A3: Backed up by capacitor
Item
Can be secured by
parameter setting.
Item
General type
Latched (backed-up) type
*1
File type
Special type
V, Z
For 100 ms
For 10 ms
Retentive type for 100 ms
Retentive type for 1 ms
General type
Latched (backed-up) type
High speed type
Current value
Power OFF Power OFF→ON
Does not change.
(The device status is not held correctly when the battery voltage becomes
lower than the holding voltage.)
Does not change.
Does not change.
(The device status is held correctly for 10 days (when the ambient tempera-
ture is 25°C) after the capacitor is fully charged, but the device status is not
held correctly after the capacitor is discharged.)
Set to initial
Cleared.
*1
value.
Cleared.
FX FX
1S 1N
A2 A2
A2 A2
A2 A2
A2 A2
FX FX
1S 1N
C C
A2 A2/A3
A2 A2
B B
B B
C C
C C
- A3
- A3
C C
A2 A2/A3
A2 A2
A3 A3
1 Device Outline
1.2 Program Memory and Devices
STOP→RUN RUN→STOP
*1
Does not change.
Does not change. Cleared.
Does not change while M8033 is ON.
FX FX FX
2N 1NC
*1
A2
A1
*1
A2
A1
*1
A2
A1
*1
A2
A1
FX FX FX
2N 1NC
C C
A1 A2/A3
A1 A2
B B
B B
C C
C C
A1 A3
A1 A3
C C
A1 A2/A3
A1 A2
A1 A3
2NC
2NC
*1
A1
*1
A1
*1
A1
*1
A1
2NC
C
A1
A1
B
B
C
C
A1
A1
C
A1
A1
*1
A1