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3 HARDWARE DESCRIPTION
LOCAL DATA BUS
LOCAL ADDRESS BUS
EEPROM
32K x 8
CAP-
BACKED
REAL
TIME
CLOCK
TIMER
COUNTER
CAP-
BACKED
RAM
128K x 16
(512K x 16)
Figure 3–10: BLOCK DIAGRAM OF THE SYSTEM PROCESSOR (i960 CPU)
GE Power Management
WDT
CLOCKOUT
COUNTER
RESET
i960
XINT
INTERRUPT
ENCODER
BUFFER
SYSTEM BUS
CONTROLS
SIGNALS
SYS-DAT
TRANSCEIVER
SYSTEM BUS
INTERRUPT
SYSTEM ADDRESS BUS
LPS-D Line Protection System
3.3 PRINTED CIRCUIT BOARD MODULES
DATA BUS
PIPELINED / BURST
CLOCK
GENERATOR
24.576 MHz
C L O C K
ADDRESS
DATA
C O N T R O L
M E M O R Y
CONTROLLER
CHIP SELECTS
BYTE ENABLE
SIGNALS
SYS-ADD
BUFFER
ADDRESS BUS
P R O G R A M
FLASH
M E M O R Y
STATIC
RAM
3-
13
3
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