ICS ELECTRONICS 4863 Manual page 77

The Questionable Enable Register enables set Event bits to be included in
the summary output to the Status Byte Register. The following example
enables bits 0 and 1:
Note that the Questionable Event Register has to be cleared after an SRQ
is generated by reading the register or with the *CLS command. If the
register is not cleared, the event bits will remain set.
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3.4.3.2
The Questionable Condition Register reflects the real time condition of the
4863's first 15 digital inputs. A logical 1 means that the corresponding
digital input is high or an open contact. A logical 0 is a low input of a contact
closure to ground. To read the Questionable Condition Register use the
following SCPI query:
The response is a decimal number that is the sum of the digital inputs whose
levels are equal to a logical 1. Reading the Questionable Condition Register
does not change its contents.
3.4.4
The 488.2 Operation Registers let the user read device specific status
conditions and detect any changes in the device's status. The Operation
Registers are similar to the Questionable Registers described in paragraph
3.4.3.
In the 4863 and 2363, the Operation Condition Register reports the Status
A and Status B inputs, the EDR Flip-flop and the WTG (Waiting for
Trigger) status. The WTG bit is true when the unit has been armed and is
waiting for a trigger. The 4863 also has the LLO and REM status bits from
the GPIB interface. The following commands demonstrate some possibili-
STAT:QUES:PTR 1
STAT:QUES:NTR 2
STAT:QUES:ENAB 3 'enables Event bits 0 and 1
Reading the Digital Inputs
STAT:QUES:COND?
Operation Registers
'enables bit 0 to set on a posi-
tive transition of CH1
'enables bit 1 to set on a nega-
tive transition of CH2
'reads the status inputs
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