ICS ELECTRONICS 4863 Manual page 74

3.4 488.2 STATUS REPORTING STRUCTURE
The 4863 includes the expanded IEEE-488.2 status reporting structure
shown in Figure 3-2. The expanded status reporting structure conforms to
the SCPI 1994.0 Specification and builds on the IEEE 488.2 Standard status
structure with the addition of the Questionable and Operation registers. The
Event and Status registers are controlled and queried with the IEEE-488.2
common commands. The Status Byte Register may also be read by serial
polling the 4863. The added Questionable and Operation registers are
controlled and queried with SCPI commands.
As shown in Figure 3-2, IEEE 488.2 SRQ generation is a multilevel
function and is determined by the occurrence of an event that has its
corresponding enable bit set to '1'. Each register is summarized in a bit in
the Status Byte Register. When those bits are enabled, the Status Byte
Register sets bit 6 and generates a Service Request by pulling the SRQ line
low. SRQs are used to signal the bus controller that an event has occurred
and/or that the unit needs service. There are three major sources of SRQs,
each of which is summarized in the Status Byte Register. Two of the sources
are event registers with their own enabling bits and the third is the Output
Queue. The Event registers and the Output Queue are cleared when read or
by the *CLS command. The RQS bit in the Status Byte Register is reset
when the unit is serial polled or when the cause is gone. The *STB? query
does not reset the MSS bit.
3.4.1 Event Registers
An event register captures 0 to 1 transitions in its associated condition
register or in the standard event conditions. An event bit becomes TRUE
(1) when the associated condition bit makes logical 0 to 1 transition. Once
an event bit is set it is held until the event register is read or cleared with the
*CLS command.
Each event register contains eight or sixteen bits. When the register is read,
its response is a decimal number that is the sum of the binary bit weights of
the bits that are logical 1s.
e.g., 23 decimal = 0001 0111 or 0000 0000 0001 0111 binary
Each event register bit has a corresponding enable bit. The enabling bits are
ANDed with the state of the event bits to create the summary condition in
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