ICS ELECTRONICS 4863 Manual page 75

the Status Byte Register. Unwanted conditions can be blocked from
generating SRQs by setting their corresponding enabling bit to a '0'. The
enabling bits are set by writing the value equal to the sum of all of the
desired logic 1 bits to the enabling register. The value is normally decimal
but can be expressed in HEX, OCTAL or BINARY by prefixing the number
with a #H, #O or #B.
3
15:10 9 8 7 6 5 4 3 2 1 0
15:10 9 8 7 6 5 4 3 2 1 0
15:10 9 8 7 6 5 4 3 2 1 0
15:10 9 8 7 6 5 4 3 2 1 0
Service
Request
Generation
7 6
&
&
7 6
&
&
&
&
&
&
&
&
&
Operation Enable Register
RQS
{
7 6 5 4 3 2 1 0
MSS
Read by *STB?
&
{
7 6 5 4 3 2 1 0
Figure 3-2 4863 Status Reporting Structure
Standard
Event Status
Register
5 4 3 2 1 0
*ESR?
&
&
&
Standard
&
&
Event Status
&
Enable
Register
5 4 3 2 1 0
*ESE <NRf>
*ESE?
15 Digital Inputs, CH Numbers
15..8
Operation
15 14....7 6 5 4 3 2 1 0
Condition
Register
Transistion
15 14....7 6 5 4 3 2 1 0
Register
Operation
Event
15 14....7 6 5 4 3 2 1 0
Register
&
&
+
&
15 14....7 6 5 4 3 2 1 0
Questionable Enable Register
ESB MAV Read by Serial Poll
Status Byte Register
&
&
&
&
&
&
Service Request
Enable Register
**SRE<>, *SRE?
3-8
Queue
Not-Empty
Output Queue
7 6 5 4 3 2 1
Questionable
Condition
Register
Transistion
Register
Questionable
Event
Register
&
&
&
+
&
&
&
&
Note 1 - Execution Error
includes EDR not set and
missing Listen handshake
+
e r r o r s .