Epson S5U13506P00C100 User Manual page 12

Page 12
S1D13506
X25B-G-014-02
JP6 - Panel Enable Polarity
JP6 selects the polarity of the LCDPWR panel enable signal.
When the jumper is at position 1-2, the LCDPWR signal is active high (default setting).
When the jumper is at position 2-3, the LCDPWR signal is active low.
Figure 3-7: Configuration Jumper (JP6) Location
JP7 - PCI FPGA Enable
JP7 controls the PCI FPGA.
When no jumper is installed, the PCI FPGA is enabled and the evaluation board may be
used in a PCI environment (default setting).
When the jumper is in position 1-2, the PCI FPGA is disabled and the evaluation board may
be used with a non-PCI host system.
Note
Non-PCI host system must be connected to headers H1 and H2.
Figure 3-8: Configuration Jumper (JP7) Location
JP6
LCDPWR
LCDPWR
Active Low
Active High
JP7
non-PCI
(FPGA Enabled)
(FPGA Disabled)
S5U13506P00C100 PCI Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
PCI
Issue Date: 2009/03/02