Epson S5U13506P00C100 User Manual page 8

Page 8
Switch Signal
S1-1 MD15
S1-2 MD1
S1-3 MD2
S1-4 MD3
S1-5 MD4
S1-6 MD5
S1-7 MD11
S1-8 MD12
= Required configuration when used in a PCI environment
MD11 MD3
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 1
S1D13506
X25B-G-014-02
The following DIP switch settings configure the S1D13506.
Table 3-1: Configuration DIP Switch Settings
Value of this pin at rising edge of RESET# is used to configure:
Closed/On=1
WAIT# is always driven.
See Table 3-2:, "Host Bus Interface Selection" on page 8
Little Endian
WAIT# is active high
See Table 3-2:, "Host Bus Interface Selection" on page 8
BUSCLK input divided by 2
The following table shows the Host Bus Interface options available. The host bus interface
is selected according to the evaluation platform to be used.
Table 3-2: Host Bus Interface Selection
MD2 MD1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1 1
= Required configuration when used in a PCI environment
WAIT# is tristated when S1D13506 is not selected
WAIT# is active low
BUSCLK input not divided
Host Bus Interface
SH-4/SH-3
MC68K Bus 1
MC68K Bus 2
Generic
Reserved
MIPS/ISA
PowerPC
PC Card
Philips PR31500/PR31700 / Toshiba TX3912
S5U13506P00C100 PCI Evaluation Board User Manual
Epson Research and Development
Vancouver Design Center
Open/Off=0
Big Endian
Issue Date: 2009/03/02