Table of Contents
Advertisement
Quick Links
S1D13506 LCD/CRT/TV Controller
S5U13506P00C100 PCI Evaluation
Board User Manual
Document Number: X25B-G-014-02
Status: Revision 2.0
Issue Date: 2009/03/02
© SEIKO EPSON CORPORATION 2006 - 2009. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners.
Advertisement
Table of Contents
Related Manuals for Epson S5U13506P00C100
Summary of Contents for Epson S5U13506P00C100
- Page 1 The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners.
- Page 2 Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
-
Page 3: Table Of Contents
Technical Support ........31 EPSON LCD/CRT Controllers (S1D13506) ....31 S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02... - Page 4 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
-
Page 5: Introduction
1 Introduction This manual describes the setup and operation of the S5U13505P00C100 PCI Evaluation Board. The S5U13506P00C100 is designed as an evaluation platform for the S1D13506 Color LCD/CRT/TV Controller chip. This document is updated as appropriate. Please check the Epson Research and Devel- opment website at http://www.erd.epson.com for the latest revision of this document before... -
Page 6: Features
• 4/8/16-bit 3.3V or 5V color passive LCD panel support • 9/12/18-bit 3.3V or 5V TFT/D-TFD LCD panel support • Embedded RAMDAC for CRT and TV support • Software initiated Power Save Mode S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02... -
Page 7: Installation And Configuration
Vancouver Design Center 3 Installation and Configuration The S5U13506P00C100 is designed to support as many platforms as possible. The board incorporates a DIP switch and several jumpers which allow both evaluation board and S1D13506 LCD controller settings to be configured for a specified evaluation platform. - Page 8 Host Bus Interface SH-4/SH-3 MC68K Bus 1 MC68K Bus 2 Generic Reserved MIPS/ISA PowerPC PC Card Philips PR31500/PR31700 / Toshiba TX3912 = Required configuration when used in a PCI environment S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
-
Page 9: Configuration Jumpers
Note When used in a PCI environment, JP1 must be set to the 1-2 position. BUSCLK from BUSCLK Oscillator (U2) from H2 Figure 3-2: Configuration Jumper (JP1) Location S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02... - Page 10 When the jumper is at position 1-2, the evaluation board is operating normally (default setting). When no jumper is installed, VDD current consumption can be measured by connecting an ammeter to JP3. Normal CoreVDD Measurement Operation Figure 3-4: Configuration Jumper (JP3) Location S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
- Page 11 When the jumper is at position 1-2, the LCD panel voltage level is configured for 5.0V. When the jumper is at position 2-3, the LCD panel voltage level is configured for 3.3V (default setting). +5V LCDVCC +3.3 LCDVCC Figure 3-6: Configuration Jumper (JP5) Location S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02...
- Page 12 Note Non-PCI host system must be connected to headers H1 and H2. non-PCI (FPGA Enabled) (FPGA Disabled) Figure 3-8: Configuration Jumper (JP7) Location S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
- Page 13 When the jumper is at position 2-3, the IREF current is 9.2mA. This setting is used for TV display, but it may be used by CRT display as well. IREF = 4.6mA IREF = 9.2mA Figure 3-9: Configuration Jumper (JP8) Location S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02...
-
Page 14: Technical Description
Table 4-4:, “CPU Interface Pin Mapping”. Note The S5U13506P00C100 is designed to work only with 3.3V systems. To use it with a 5V system, some modifications must be done to the board as follows: 1. Replace the 3.3V DRAM (U6) on the board with a 5V DRAM. -
Page 15: Cpu Interface Pin Mapping
IOCHRDY DTACK# DSACK1# -WAIT /CARDxWAIT CARDxWAIT* /WAIT# inverted inverted RESET# RESET# RESET# RESET# RESET# RESET# RESET# PON* RESET RESET Note A0 for these busses is not used internally by the S1D13506. S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02... -
Page 16: Cpu Bus Connector Pin Mapping
Connected to WAIT# of the S1D13506 Connected to CS# of the S1D13506 Connected to MR# of the S1D13506 Connected to WE1# of the S1D135065 S1D13506 supply, provided by the S5U13506P00C100 S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02... - Page 17 Connected to BS# of the S1D13506 Connected to S1D13506 BUSCLK if JP1 is in position 2-3 Connected to RD# of the S1D13506 Connected to AB20 of the S1D13506 Not connected S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02...
-
Page 18: Lcd Support
S1D13506 Hardware Functional Specification, document number X25B-A-001-xx. For S1D13506 FPDAT[15:0] pin mapping for various types of panel see Table 4-7:, “LCD Signal Connector (J4)” on page 19. S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02... -
Page 19: Lcd Interface Pin Mapping
GPIO pins to control the LCD bias power allowing for software control of power sequencing delays. For further information on LCD power sequencing, see the S1D13506 Programming Notes and Examples, document number X25B-G-003- S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02... -
Page 20: Buffered Lcd Connector
3.3V or 5V. Pin 32 on this connector provides power for the LCD panel logic at the same voltage as the buffer power supply. S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02... -
Page 21: Crt/Tv Support
The evaluation board has 2 headers, JP3 and JP4, which allow the independent measurement of S1D13506 VDD and DACVDD current consumption. To measure the current, remove the appropriate jumper and connect an ammeter to the corresponding header pins. S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02... -
Page 22: References
5 References 5.1 Documents • Epson Research and Development, Inc., S1D13506 Hardware Functional Specification, Document Number X25B-A-001-xx. • Epson Research and Development, Inc., S1D13506 Programming Notes and Examples, Document Number X25B-G-003-xx. 5.2 Document Sources • Epson Research and Development Website: http://www.erd.epson.com. -
Page 23: Parts List
R0805 — 69.8R,1% R0805 — 140R,1% R0805 generic SW DIP-8 DIPSW8 Grayhill 76SB08S S1D13506F00A TQFP128 Epson S1D13506F00A 40MHz DIP14 Epson SG8002DB, 40MHz socketed 25.175MHz DIP14 Epson SG8002DB, 25MHz socketed S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02... - Page 24 SOJ, Lead free LT1117CST-3.3 — Linear Technologies LT1117CST-3.3 INVERTER SINGLE SC70-5 Fairchild Semiconductor NC7S04P5 NC7S04 U9,U10,U11 74AHC244 SO20W TI 74AHC244 EPF6016TC14 TQFP144 Altera EPF6016TC144-2 EPC1PI8N DIP8 Altera EPC1PI8N programmed, socketed S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
-
Page 25: Schematic Diagrams
Epson Research and Development Page 25 Vancouver Design Center 7 Schematic Diagrams Figure 7-1: S5U13506P00C100 Evaluation Board Schematics (1 of 5) S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02... - Page 26 Page 26 Epson Research and Development Vancouver Design Center Figure 7-2: S5U13506P00C100 Evaluation Board Schematics (2 of 5) S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
- Page 27 Epson Research and Development Page 27 Vancouver Design Center Figure 7-3: S5U13506P00C100 Evaluation Board Schematics (3 of 5) S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02...
- Page 28 Page 28 Epson Research and Development Vancouver Design Center Figure 7-4: S5U13506P00C100 Evaluation Board Schematics (4 of 5) S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...
- Page 29 Epson Research and Development Page 29 Vancouver Design Center Figure 7-5: S5U13506P00C100 Evaluation Board Schematics (5 of 5) S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02...
-
Page 30: Board Layout
Page 30 Epson Research and Development Vancouver Design Center 8 Board Layout Figure 8-1: S5U13506P00C100 Evaluation Board Layout S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02... -
Page 31: Technical Support
Youngdeungpo-Ku, Seoul, 150-763, KOREA Phone: +82-2-784-6027 FAX: +82-2-767-3677 SEIKO EPSON CORP. SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 FAX: +81-42-587-5117 S5U13506P00C100 PCI Evaluation Board User Manual S1D13506 Issue Date: 2009/03/02 X25B-G-014-02... - Page 32 Page 32 Epson Research and Development Vancouver Design Center Change Record X23A-G-014-02 Revision 2.0 • update sales offices X23A-G-014-01 Revision 1.0 • initial release S1D13506 S5U13506P00C100 PCI Evaluation Board User Manual X25B-G-014-02 Issue Date: 2009/03/02...