Wake-Up Options (Uja1162A/66A/68Af/68Axf-Evb) - NXP Semiconductors UJA116 A Series User Manual

NXP Semiconductors

2.4 Wake-up options (UJA1162A/66A/68AF/68AXF-EVB)

UM11379
User manual
The UJA1162A, UJA1166A and UJA1168A support a Sleep mode for use in energy-
sensitive applications. Once in Sleep mode, the device will remain in this low-power
mode until a wake-up request is received. A wake-up event can be triggered remotely
via a standard pattern or dedicated wake-up frame on the CAN bus (UJA1168A only), or
locally via the WAKE pin (details of wake-up functionality can be found in the data sheets
and application hints; see
Table 9. WAKE/INH connections
UJA1162A, UJA1166A, UJA1168A
WAKE (pin 9)
[1]
INH (pin 7)
[1] Not valid for the UJA1168ATK/X and UJA1168ATK/XF; pin 7 is VEXT in these devices (see data sheet:
The UJA1162A, UJA1166A, UJA1168AF and UJA1168AXF evaluation boards feature
local wake-up test circuitry. The WAKE pin is pulled HIGH by default via 10 kΩ resistors
R6 and R7. When switch SW1 is pressed, the WAKE pin is pulled LOW. Local wake-
up is enabled automatically in the UJA1162A and UJA1166A. It must be enabled via the
register map in the UJA1168A (as described in the UJA1168A data sheet).
In the UJA1162A and UJA1166A, pin INH is used to control the supply to the MCU. It is
pulled LOW via resistor R8 when the SBC switches to Sleep mode. When a wake-up
event is detected, INH is forced HIGH to switch on the voltage regulator supplying the
MCU.
In the UJA1168A, the MCU is intended to be supplied via V1. V1 is off in Sleep mode
and switches on automatically when a wake-up event is detected. Pin INH in the
UJA1168ATK and UJA1168ATK/F can be used to control external voltage regulators and
other devices, but is not necessarily relevant for wake-up.
The WAKE and INH pins can be accessed via header J3, on the top of the evaluation
board.
J3
INH
WAKE
GND
Figure 8. Local wake and INH circuitry
All information provided in this document is subject to legal disclaimers.
Section 7).
UJA1162A-EVB, UJA1166A-EVB, UJA1168AF-EVB,
UJA1162AXF-EVB
J3-11: connect to wake-up signal
J3-10: connect to control input signal from external
regulator(s) (not relevant for UJA1168AXF-EVB)
R7, 10 kΩ R6, 10 kΩ
BAT
R8
SW1
10 kΩ
Rev. 1 — 23 April 2021
UM11379
UJA116xA evaluation boards
INH(p7)
WAKE(p9)
UJA1162A
UJA1166A
UJA1168AF
C7
10 nF
GND(p2)
aaa-040311
© NXP B.V. 2021. All rights reserved.
Section 7).
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