Sony IPELA XIS-10DC Service Manual page 65

INPUTS
DIS_ARPVLAN : ARP BROADCAST TO ALL VLAN DISABLE
DIS_DS_PRI : DIFFSERV PRIORITY DISABLE
DIS_FC_AUTOOFF : AUTO TURN OFF OF FLOW CONTROL ABILITY DISABLE
DIS_LEAKYVLAN : LEAKY VLAN DISABLE
DIS_TRUNK : TWO PORT TRUNKING FUNCTION DISABLE
DIS_VLAN : VLAN DISABLE
DIS_VLAN_PRI : VLAN TAG PRIORITY DISABLE
EN_48PASS1 : 48 PASS 1 MECHANISM ENABLE
EN_AGRS_BACK : AGGRESSIVE BACK-OFF MECHANISM ENABLE
EN_ANEG : AUTO-NEGOTIATION ENABLE
EN_AUTOXOVER : AUTO CROSSOVER DETECTION ENABLE
EN_BKPRS : BACK PRESSURE ABILITY ENABLE IN HALF DUPLEX MODE
EN_BRD_CTRL : BROADCAST STORM CONTROL DISABLE
EN_DEFER : CARRIER SENSE DEFERRING ENABLE
EN_FCTRL : FLOW CONTROL ABILITY ENABLE IN FULL DUPLEX MODE
EN_FORWARD : FORWARDING ENABLE OF MAC ADDRESS
EN_RST_BLNK : BLINKING OF LED UPON RESET ENABLE
FORCE_DUPLEX : FORCE DUPLEX MODE
FORCE_SPEED : FORCE OPERATING SPEED
LED_BLNK_TIME : BLINKING SPEED OF ACTIVITY AND COLLISION LED SELECT
MAX_PAUSE_COUNT : MAX PAUSE FRAME COUNT SELECT
MAX_PKT_LEN : MAX FRAME LENGTH SELECT
MCOL : MII COLLISION DETECT
MII_DUP_STA : MII PORT DUPLEX STATUS
MII_FCTRL_STA : MII PORT FLOW CONTROL STATUS
MII_LNK_STA : MII PORT LINK STATUS
MII_MODE0, MII_MODE1 : MODE SELECT
MII_SPD_STA : MII PORT SPEED STATUS
MRXC : MII RECEIVE CLOCK
MRXD0 - MRXD3 : MII RECEIVE DATA
MRXDV : MII RECEIVE DATA VALID
MTXC : MII TRANSMIT CLOCK
P2_LED0, P2_LED1 : PORT LED STATUS
PTXD0 - PTXD3 : MII TRANSMIT DATA
PTXEN : MII TRANSMIT ENABLE
QWEIGHT0, QWEIGHT1 : WEIGHTED ROUND ROBIN RATIO PRIORITY QUEUE
RESET
: RESET
RXIN0 - RXIN7, : DIFFERENTIAL RECEIVE DATA
RXIP0 - RXIP7
SEL_PORTPRI0, : HIGH PRIORITY PORT SELECT
SEL_PORTPRI1
X1 : 25 MHz CRYSTAL
OUTPUTS
IBREF : CONTROL TRANSMIT OUTPUT WAVEFORM POWER
MTXD0 - MTXD3 : MII TRANSMIT DATA OF MAC
MTXEN : MII TRANSMIT ENABLE
PCOL : MII COLLISION DETECT
PRXC : MII/SNI RECEIVE CLOCK
PRXD0 - PRXD3 : MII RECEIVE DATA OF MAC
PRXDV : MII RECEIVE DATA VALID
PTXC : MII TRANSMIT CLOCK
TXON0 - TXON7, : DIFFERENTIAL TRANSMIT DATA
TXOP0 - TXOP7
X2 : 25 MHz CRYSTAL
INPUTS/OUTPUTS
ENEEPROM : SERIAL EEPROM LOAD ENABLE
LED_MODE_0 - LED_MODE_2 : LED MODE SELECT
LOOPLED
: NETWORK LOOP DETECT
P0_LED0 - P7_LED0, : PORT LED STATUS
P0_LED1 - P7_LED1,
P0_LED2 - P7_LED2,
P0_LED3 - P7_LED3
PORT_LED_LOC : PORT LED LOCATION
SCL_MDC : EEPROM SERIAL CLOCK OR MDC
SDA_MDIO : EEPROM SERIAL DATA OR MDIO
XIS-10DC
122 WAVEFORM
IBREF
SHAPING
127, 128
10BASE-T OR
RXIP0, RXIN0
10/100
125, 124 100BASE-TX
MAC 0
TXIP0, TXIN0
PHY CEIVER
10BASE-T OR
6, 7
RXIP1, RXIN1 10/100
100BASE-TX
4, 3
MAC 1
TXIP1, TXIN1
PHY CEIVER
10, 9
10BASE-T OR
RXIP2, RXIN2
10/100
12, 13 100BASE-TX
TXIP2, TXIN2 MAC 2
PHY CEIVER
18, 19 10BASE-T OR
RXIP3, RXIN3
10/100
100BASE-TX
16, 15
MAC 3
TXIP3, TXIN3
PHY CEIVER
22, 21
10BASE-T OR
RXIP4, RXIN4
10/100
100BASE-TX
24, 25
MAC 4
TXIP4, TXIN4
PHY CEIVER
30, 31 10BASE-T OR
RXIP5, RXIN5 10/100
100BASE-TX
28, 27
MAC 5
TXIP5, TXIN5
PHY CEIVER
34, 33
10BASE-T OR
RXIP6, RXIN6 10/100
36, 37 100BASE-TX
MAC 6
TXIP6, TXIN6
PHY CEIVER
40, 39
10BASE-T OR
RXIP7, RXIN7
10/100
100BASE-TX
42, 43
MAC 7
TXIP7, TXIN7
PHY CEIVER
10/100
MAC
MAC 8
MODE
INTER
13
MII SIGNAL
FACE
MODE
PHY
SELECT
MODE
MII MODE0,
101, 102
MII MODE1
FLOW
CONTROL
TX/RX
FIFO
FLOW
CONTROL
TX/RX
FIFO
FLOW
CONTROL
LOOK-UP TABLE
TX/RX
(1024-ENTRIES)
FIFO
FLOW
CONTROL
TX/RX
QUEUE
FIFO
MANAGEMENT
FLOW
CONTROL
TX/RX
FIFO
BUFFER
MANAGEMENT
FLOW
CONTROL
TX/RX
FIFO
FLOW
PACKET
CONTROL
BUFFER
TX/RX
FIFO
FLOW
CONTROL
TX/RX
FIFO
EEPROM
INTERFACE
FLOW
CONTROL
CONTROL
TX/RX
REGISTERS
FIFO
6-3
IC