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3-1. SNT-1 Board
3-1-1. Digital Image Data Processing Circuit
The analog video signal input from the 360d camera
module is input to the video decoder (IC101) through the
CN13 on the SNT-1 board.
In the video decoder (IC101), the analog video signal is
converted into the YUV411 digital image data (VD0 to
VD7) and output to the JPEG controller ASIC (IC53)
along with the clock signal (CLK27M).
In the JPEG controller ASIC (IC53), the image format of
the YUV411 digital image data is converted into
YCbCr422, and frame data is written in the frame memory
(SDRAM, IC51). The conversion of interlacing to non-
interlacing and the data conversions such as square
latticing and resizing are performed. And raster block
conversion is performed using a buffer (SRAM, IC52),
then the resultant data is sent to JPEG CODEC (IC54).
Data is JPEG-compressed in JPEG CODEC (IC54).
The JPEG controller ASIC (IC53) incorporates a DMA
interface with SH CPU (IC106). IC53 transfers the JPEG
compression data to the system memory (SDRAM, IC159
and IC160) by DMA (XSH_DREQ and XSH_DACK) and
stores it at high speed.
SH bus address decoding, external interrupt control or
external wait control is provided.
The control signals from each IC are first input to the
JPEG controller ASIC (IC53) and output to SH CPU
(IC106) after it is controlled.
3-1-2. Outline of SH CPU Operation
The main operations of SH CPU (IC106) are as follows:
. Accesses and controls the JPEG controller ASIC (IC53),
system memory (SDRAM, IC159, and IC160), system
ROM (flash memory, IC157, and IC158), PC card
controller (IC251), and PHY chip (IC306).
. Transfers data (JPEG image data) through the network
and records into the PC card.
. Performs the external interface (RS-232C), LED control,
interrupt control, RTC (IC152) control, and software
reset (XSRST) control.
. Fan, heater, and peltier element control
XIS-10DC
Section 3
Circuit Description
3-1-3. System ROM
The system ROM (8 MB flash memory, IC157, and IC158)
stores the data of the operation program of SH CPU
(IC106), Web contents, or system environmental
information. The data is read and written by the SH data
bus. Moreover, firmware can be upgraded through the
network and PC card.
3-1-4. System Memory
The system memory (32 MB SDRAM, IC159, and IC160)
stores the SH CPU (IC106) operation program or Web
contents from the system ROM (flash memory, IC157,
IC158) when the power is turned on.
The area of approximately 8 MB is secured as internal
memory.
The system memory also temporarily stores the JPEG
compression data transferred from the JPEG controller
ASIC (IC53) at high speed by the DMA controller built in
SH CPU (IC106) or the image of the alarm buffer.
3-1-5. RTC Circuit
The dated watch function is realized by the RTC (Real
Time Clock, IC152). The RTC is backed up by the
rechargeable battery (BT151). The watch data of RTC can
be read and written through the network by SH CPU
(IC106).
3-1-6. PC Card Control Block
The PC card is accessed through PC card slot CN9 by the
SH CPU (IC106) and the PC card controller (IC251). The
PC card power supply of 3.3 V DC and 5 V DC can be
used by the PC card power selection circuit (IC252).
The PC card is used for the firmware upgrading.
3-1 (E)
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