Advantech PCI-1751 User Manual page 22

Ti m e r 0 & 1 :
Tw o 1 6 -b i t Ti m e r s o r On e 3 2 -b i t Ti m e r
Timer 0 and Timer 1 of the counter chip can be used separately or can
be cascaded to create a 32-bit programmable timer by setting jumper
JP2. By setting the clock source of Timer 1 to be an external source,
you can user Timer 0 and Timer 1 as two separate 16-bit timers. By
setting the clock source of Timer 1 to be the output of Timer 0 (internal
source) these two timers are cascaded to become one 32-bit timer.
Setting jumper JP1 sets the clock source of Timer 0 to be external, and
this allows Timer 0 and Timer 1 to be cascaded into a 32-bit event
counter.
Co u n t e r 2
Counter 2 can be a 16-bit timer or an event counter, selectable by
setting JP3. When the clock source is set for an internal source,
Counter 2 is a 16-bit timer; when set as an external source, then
Counter 2 is an event counter. Counter 2 is set as mode 0 (interrupt on
terminal count) in the driver provided by Advantech.
Ti m e r / Co u n t e r Fr e q u e n c y a n d In t e r r u p t
The input clock frequency of the counter/timers is 10 MHz. The output
of both Timer 1 and Counter 2 can generate interrupts for the system
(refer to section 3.3). The maximum and minimum timer interrupt
frequency is (10 MHz)/(2)=(5 MHz) and (10 MHz)/
(65535*65535)=0.002328 Hz, respectively.
The gates of the counter/timers are internally pulled to +5 V when gate
control is enabled, but a user can also set it using the connector pins
(CNT0_G, CNT1_G and CNT2_G).
1 8 PCI-1751 User's Manual
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