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J9
P
R
OWER
EQUIREMENTS
The VL-EPM-24 requires only +5V (±5%) for proper operation. The voltage required for the
RS-232 ports is generated with an on-board DC/DC converter. Variable low-voltage supply
circuits provide power to the CPU and other on-board devices.
The exact power requirement of the VL-EPM-24 depends on several factors, including memory
configuration, CPU speed, peripheral connections, and the type and number of expansion
modules and attached devices. For example, driving long RS-232 lines at high speed can increase
power demand.
P
C
OWER
YCLING
To ensure reliable power up when cycling power, you must allow the power to remain off for a
minimum of three seconds. This ensures that all internal clocks and phased-lock loop (PLL)
circuitry have settled before powering back on. The three second minimum is a requirement of
the Intel chipset architecture and not the design of the VL-EPM-24.
In order to reduce boot failures when power is cycled in less than three seconds, the system's
watchdog timer is enabled by default during the power-on self-test (POST) pre-boot sequence.
With the
POST Watchdog
will cause the watchdog to timeout and reboot the board. If disabled, a hang caused by quick
power cycling will cause a boot failure.
L
B
ITHIUM
ATTERY
Warning!
To prevent shorting, premature failure, or damage to the lithium battery, do not
place the board on a conductive surface such as metal, black conductive foam, or
the outside surface of a metalized ESD protective pouch. The lithium battery may
explode if mistreated. Do not recharge, disassemble or dispose of in fire. Dispose
of used batteries promptly.
Normal battery voltage should be at least +3V. If the voltage drops below +2V, contact the
factory for a replacement (part number HB3/0-1). The life expectancy under normal use is
approximately 10 years.
VL-EPM-24 Reference Manual
Some manufacturers include
a pin-1 indicator that
corresponds to pin-10 of the
power connector pinout
10
6 8
2 4
7 9
1 3 5
Figure 11. J9 and VL-CBR-1008 Pin Numbering
parameter enabled in CMOS Setup, a hang condition during POST
10
8
6
4
2
9
7
5
VL-CBR-1008
3
1
System Features
21
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