Pc/104 Interrupt Request Enable Registers - VersaLogic Tiger Reference Manual

PC/104 Interrupt Request Enable Registers

These registers are used to configure PC/104 bus IRQs. Legacy IRQs on the Serial IRQ (LPC)
bus each have an enable bit that allows the IRQ to be forwarded from the PC/104 bus to the
Serial IRQ (LPC) bus. These registers are set in CMOS Setup, but are accessible to user software
for runtime configuration as well.
Not all IRQs listed will necessarily be available for use on the PC/104 bus. Be sure to note which
legacy IRQs are assigned by the operating system to other devices before enabling them for the
PC/104 bus to avoid conflicts.
PC104_IRQ_EN0 (Read/Write) 1DEh
D7
IRQ11_EN IRQ10_EN
Bit Mnemonic
D7 IRQ11_EN
D6 IRQ10_EN
D5 IRQ9_EN
D4 IRQ7_EN
D3 IRQ6_EN
D2 IRQ5_EN
D1 IRQ4_EN
D0 IRQ3_EN
VL-EPM-24 Reference Manual
D6 D5
IRQ9_EN IRQ7_EN
Table 26: PC/104 Interrupt Request Register 0 Bit Assignments
Description
PC/104 IRQ11 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ10 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ9 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ7 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ6 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ5 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ4 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
PC/104 IRQ3 enable
0 = disabled on PC/104 bus
1 = enabled on PC/104 bus
D4 D3
IRQ6_EN IRQ5_EN
Special Registers
D2 D1
IRQ4_EN IRQ3_EN
D0
51