Watchdog Timer Register - VersaLogic Tiger Reference Manual

Watchdog Timer Register

This register controls the behavior of the System Management Controller if the Super I/O
watchdog timer interrupt pins have been asserted. The actual conditions and setup of the
watchdog timer are configured in the SMSC SCH3114 and Intel SCH ACPI register interface.
WDTHWM (Read Only) 1D3h
D7
WDT_ST
Bit Mnemonic
D7 WDT_ST
D6 Reserved
D5-D4 WDT_MD
D3 HWMINT_ST
D2 Reserved
D1-D0 HWM_INT
VL-EPM-24 Reference Manual
D6 D5
Reserved WDT_MD1 WDT_MD0 HWM_INT_ST
Table 23: Watchdog Timer Register Bit Assignments
Description
Watchdog Timer Status – This bit shows the condition of the GP60/nLED1/WDT
pin (pin 94) on the SMSC3114. This pin can be configured as the watchdog timer
flag to assert when a timeout has occurred.
0 = when the super I/O pin GP60/nLED1/WDT WDT = 1
1 = when the super I/O pin GP60/nLED1/WDT WDT = 0
This bit has no function.
Watchdog Timer Mode – These bits set the behavior of the System Management
Controller for the watchdog timer. On detecting a watchdog timeout, the System
Mgt. Controller can perform a system-wide hardware reset (power is not removed),
cold reset (power is shutdown for approx. 4 sec.), or can shut down the board.
WDT_MD1
0
0
1
1
Hardware Monitor Interrupt Status – This bit shows the condition of the
nHWM_INT pin (pin 114) on the SMSC3114. This pin can be set up as the
hardware monitor interrupt flag to assert when a configured fault condition occurs.
0 = when the super I/O pin, nHWM_INT = 1
1 = when the super I/O pin, nHWM_INT = 0
This bit has no function.
Hardware Monitor Interrupt – These bits set the behavior of the System
Management Controller for the hardware monitor. On detecting the nHWM_INT
super I/O pin asserted, the System Management Controller can activate the
thermal alarm to the US15WP/T SCH, perform a cold reset (power is shut down for
approx. 4 sec.), or can shut down the board. The thermal alarm can be used by
ACPI software to tell the SCH to initiate configurable thermal control measures for
the CPU and chipset I/O devices.
HWM_INT1
0
0
1
1
D4 D3
Reserved
WDT_MD0 Mode
0 Do nothing
1 Warm reset
0 Cold reset
1 Power off
HWM_INT0 INT
0 Do nothing
1 Assert THRM#
0 Cold reset
1 Power off
Special Registers
D2 D1 D0
HWM_INT1 HWM_INT0
48