Communication (Rs232, 10/100 Ethernet, Usb2.0); Table 20 - Rs232 Fpga Pin-Out; Table 21 - Rs232 Connector Pin-Out - Avnet Xilinx Spartan-3 User Manual

2.13.3
Manufacturer: Cypress
Part #: CY7C1062AV33-12BGC
A single Cypress Asynchronous SRAM device, part number: CY7C1062AV33-12BGC, connects to the 32-bit wide shared data bus.
The Cypress device provides 2 MB of SRAM memory on a single IC and is organized as 512K x 32. The device has an operating
voltage of 3.3V and a –12 speed grade for 80 MHz operation.
An example project, using the OPB_EMC is included with the Spartan-3 Dev kit. This example will provide correct timing parameters
for operating the SRAM and Flash devices. See the Software/BSP section of this manual for more information.

2.14 Communication (RS232, 10/100 Ethernet, USB2.0)

For communication, the Spartan-3 FPGA has access to an RS232 transceiver, a 10/100 Ethernet PHY, and a USB2.0 transceiver.
2.14.1
Manufacturer: Harris/Intersil
Part #: ICL3222CA
The RS232 transceiver is a 3222 available from Harris/Intersil (ICL3222CA) and
Devices (ADM3222). This transceiver is operating at 3.3V for VCC. The FPGA transmit/receive signals are connected to a 2.5V I/O
bank of the FPGA (Bank 6). Because the 3222 minimum logic threshold high is 2V, the 2.5V bank will work for this interface. The
internal charge pump creates the RS232 compatible output levels.
The standard RX and TX lines (pin3 and pin2) are connected to the FPGA by way of the 3222. The RTS/CTS pins may be jumpered
out, allowing the FPGA pins to be directly connected to the USB IC's RS232 port. The FPGA will be connected to RTS/CTS when
jumpers JP28 and JP29 are at position 1-2. Otherwise, in position 2-3, the FPGA will not be connected to RTS/CTS, but to the RS232
RX/TX lines of the USB IC.
A straight through serial cable should be used to plug "J3" into a standard PC serial port (male DB9).
* Note: RTS and CTS are only connected to the FPGA when JP28 and JP29 are in position 1-2.
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Released
SRAM
RS-232
Signal Name
Transmit (RS232_TX1)
Receive (RS232_ RX1)
*CTS (RS232_ CTS)
*RTS (RS232_ RTS)

Table 20 - RS232 FPGA Pin-out

Signal Name
TX
RX
CTS
RTS
GND

Table 21 - RS232 Connector Pin-out

Pin 5
Pin 9
FPGA
pin#
P5
P4
P7
P6
DB9 J3 Xcvr pin#
2 17
3 16
8 8
7 9
5 -
24 of 33
Pin 1
Pin 6
DB9 Serial Connector
Xcvr
pin#
13
15
12
10
Analog
Rev 1.0 04/17/2006
Literature # ADS-005104