Table 11 - Video Dac - Fpga Pin-Out; Table 12 - Video Dac Jumpers - Avnet Xilinx Spartan-3 User Manual

* Note: DAC signals are connected to the FPGA by way of a bus switch. This allows the re-use of header signals. If you wish to use
the 50-pin header J17, you may disable the bus switches using JP20.
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Signal *Header Equivalent
Red(0)
Red(1)
Red(2)
Red(3)
Red(4)
Red(5)
Red(6)
Red(7)
Green(0)
Green(1)
Green(2)
Green(3)
Green(4)
Green(5)
Green(6)
Green(7)
Blue(0)
Blue(1)
Blue(2)
Blue(3)
Blue(4)
Blue(5)
Blue(6)
Blue(7)
Video_clk
Horiz_sync
Vert_sync
Comp_sync
Blank
Table 11 – Video DAC - FPGA Pin-out
Jumper
JP23 On – disables oscillator U28
JP20 On – enables bus switches
JT10 Resistor Jumper:
2-3 – Power save mode
Table 12 – Video DAC Jumpers
18 of 33
FPGA pin#
Net
HDR_IO(0) A19
HDR_IO(1) A22
HDR_IO(2) A20
HDR_IO(3) A23
HDR_IO(4) D19
HDR_IO(5) A21
HDR_IO(6) E19
HDR_IO(7) B23
HDR_IO(8) B22
HDR_IO(9) C23
HDR_IO(10) C22
HDR_IO(11) B21
HDR_IO(12) C21
HDR_IO(13) E21
HDR_IO(14) D21
HDR_IO(15) F21
HDR_IO(16) E20
HDR_IO(17) B20
HDR_IO(18) F20
HDR_IO(19) D20
HDR_IO(20) F19
HDR_IO(21) B19
HDR_IO(22) G19
HDR_IO(23) C19
HDR_IO(24) W21
HDR_IO(25) W20
HDR_IO(26) Y21
HDR_IO(27) Y20
HDR_IO(28) AC22
Function Default
OFF
ON
1-2
Rev 1.0
Literature # ADS-005104
04/17/2006