Vga (Db15 & Video Dac); Table 10 - Oled Display Fpga Pin-Out - Avnet Xilinx Spartan-3 User Manual

2.6 VGA (DB15 & Video DAC)
Manufacturer: Analog Devices
Part #: ADV7125KST140
The Spartan-3 Dev board provides a DB15 and Video DAC to drive an
RGB monitor. RGB data is output from the FPGA in a 24-bit parallel format (8 bits each Red/Green/Blue). This data, along with clock,
blanking and synchronization signals is provided to the ADV7125 triple video DAC for conversion to RS-343A/RS-170-compatible video
signals to drive an RGB monitor. Note that the ADV7125 can accept 10-bit R, G and B data but pin utilization of the FPGA limits this
data path to 24 instead of 30 bits. The eight R, G and B data bits are provided to the eight most-significant bits of the DAV7125 RGB
inputs with the two least-significant bits of R, G and B held at ground level.
Also provided by the FPGA to the ADV7125 are composite synchronization and blanking signals.
synchronization signals are brought to pins 14 and 13 (respectively) of DB15 connector (P4) but are not required. The analog RGB
signals generated by the ADV7123 are connected to P4 to drive an analog RGB monitor via a doubly terminated 75-ohm coaxial cable.
The ADV7125 device internally encodes video synchronizing information onto the Green channel.
The 25.175MHz oscillator provides the required clocking for a 640 X 480 60Hz VGA monitor. This is determined as follows: horizontal
lines (pixels) * vertical lines * refresh rate. Due to required overhead (e.g., horizontal and vertical retrace, etc), the 640 X 480 display is
actually 800 X 525 (800 x 525 x 59.94 = 25.175e6). Note that while 60Hz is commonly used in discussion, the actual refresh rate is
59.94Hz. The oscillator may be replaced with a higher frequency oscillator to support higher resolution monitors; e.g., VGA (640 x 480)
@72 Hz requires 31.5MHz, SVGA (800 x 600) @ 72Hz requires 50.0MHz, XGA (1024 X 768) @ 75 Hz requires 78.75MHz, SXGA
(1280 X 1024) @ 75Hz requires 135.0MHz. The ADV7125KST140 140MHz device furnished on the board is sufficient for SXGA
resolution at 75Hz.
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Released
OLED Signal LCD Name
DISP_CSB
DISP_RSTB
DISP_RS
DISP_RD_WRB
DISP_ECLK
DISP_D0
DISP_D1
DISP_D2
DISP_D3
DISP_D4
DISP_D5
DISP_D6
DISP_D7
-

Table 10 - OLED Display FPGA Pin-out

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FPGA pin#
- AA4
- AA6
DISP_RS P8
- Y7
- Y10
DISP_D0 AE21
DISP_D1 AF21
DISP_D2 AE20
DISP_D3 AF20
DISP_D4 AE19
DISP_D5 AE18
DISP_D6 AE17
DISP_D7 AD14
LCD_EN R8
Pin 15
DB15 VGA Connector
Pin 6
Pin 11
analog
Vertical and horizontal
Rev 1.0 04/17/2006
Literature # ADS-005104