Figure 17 - Resistor Jumper Pin-Out; Table 22 - Ethernet Phy Modes; Table 23 - Ethernet Jumpers And Leds - Avnet Xilinx Spartan-3 User Manual

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2.14.2
Transceiver –
Manufacturer: National Semiconductor
Part #:
DP83847ALQA56A
Connector –
Manufacturer: Pulse
Part #:
J0026D01B
The on-board Ethernet PHY is a National DP83847ALQA56A DsPHYTER® II. The DP83847 is a small, low power physical layer
transceiver that only requires a single 3.3V supply. The PHY supports 3.3V signaling levels to the MAC interface, in this case the
Spartan-3 FPGA. The PHY is connected to a Pulse RJ-45 jack with integrated magnetics (part number: J0026D01B). The jack also
integrates two LEDs to show Link and Receive Activity. Four more LEDs are provided on the board for status indication. These LEDs
indicate Link Speed (D13), Transmit Activity (D11), Collision Detect (D10) and Full Duplex operation (D12). The PHY clock is
generated from its own 25 MHz crystal. The PHY address is set to binary "00011". Three-pad resistor jumpers were used to set the
operating mode (JT1, JT2 and JT3). An illustration of the resistor jumper footprint is shown below.
These jumper pads provide the user with the ability to change the operating mode by moving the resistors. By default the PHY is set to
auto negotiate a link with a peer. The available modes of operation are shown in the table below.
Operating Modes
10BaseT Half Duplex, Forced Mode
10BaseT Full Duplex, Forced Mode
100Base-TX Half Duplex, Forced Mode
100Base-TX Full Duplex, Forced Mode
10BaseT Half/Full Duplex Advertised, Auto-negotiate
100Base-TX Half/Full Duplex Advertised, Auto-negotiate
10BaseT/100Base-TX Half Duplex Advertised, Auto-negotiate
10BaseT/100Base-TX Half/Full Duplex, Auto-negotiate (Default)
The use of this port requires an Ethernet MAC core to be instantiated in the FPGA project. The example project that includes network
support utilizes a licensed IP core from Xilinx. A valid license for this IP may be required to regenerate the project. The following table
provides the FPGA pin numbers for the Ethernet PHY interface.
Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners.
Avnet Electronics Marketing
Released
10/100 Ethernet
"Link"

Figure 17 - Resistor Jumper Pin-out

Table 22 - Ethernet PHY Modes

Reference Designator
JP8
JT1-3
D10
D11
D12
D13

Table 23 - Ethernet Jumpers and LEDs

"RX Active"
RJ45 Ethernet Connector
Function
Ethernet Enable
Installed by default
Operating Mode
Resistor Jumpers
(see table above)
Collision Detect
TX Activity
Duplex
Speed Indicator
25 of 33
D13 D11 D10 D12
Speed
RJ45
10/100 Eth
JT3
JT2
JT1
2-3
2-3
2-3
2-3
2-3
1-2
2-3
1-2
2-3
2-3
1-2
1-2
1-2
2-3
2-3
1-2
2-3
1-2
1-2
1-2
2-3
1-2
1-2
1-2
Note
TX Col Dup
JP8
Eth En
Rev 1.0
04/17/2006
Literature # ADS-005104

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