Figure 13 - I/O Voltage Selection Banks 4&5; Figure 14 - I/O Voltage Selection Banks 1&2; Figure 15 - I/O Voltage Selection Banks 2&3 - Avnet Xilinx Spartan-3 User Manual

JP11 "USB DIS" – USB Disable, install a shunt to hold the Cypress EZ-USB device in reset. When open, the USB reset line is
controlled by either an I/O pin of the FPGA or the push-button labeled "SW2".
Default: Open, the FPGA or push-button controls the USB reset.
JP12 "FLASH WP#" – Flash write protect. When jumper is installed, WP# will be tied hard low. When uninstalled, WP# is pulled high
via pull-up resistor.
Default: Uninstalled; write protect not active.
JP13 "FLASH RESET" – Connects the flash reset pin to the FPGA. This connection is only available on the 2000 density part. When
uninstalled (or unavailable ie...1500 density part), the flash reset will be inactive (flash enabled) by way of resistor pull-up on the board.
Default: Installed
JP14 "LCD BACKLIGHT" – Enables the LED backlight panel on the 2x20 LCD.
Default: Installed
JP16 "BANK 4&5 VCCO VOLTAGE" – VIO Selection, selects the I/O voltage for FPGA banks 4 and 5. Only one jumper should be
placed at this connector. Valid placements are 1-2, 2-3 as indicated in the Figure below.
Default: Installed across pins 1-2; 3.3V supply.
JP17 "BANK 0&1 VCCO VOLTAGE" – VIO Selection, selects the I/O voltage for FPGA banks 0 and 1. Only one jumper should be
placed at this connector. Valid placements are 1-2, 3-4, or 5-6 as indicated in the Figure below.
Default: Installed across pins 1-2; 3.3V supply.
JP18 "BANK 2&3 VCCO VOLTAGE" – VIO Selection, selects the I/O voltage for FPGA banks 2 and 3. Only one jumper should be
placed at this connector. Valid placements are 1-2, 3-4, or 5-6 as indicated in the Figure below.
Default: Installed across pins 1-2; 3.3V supply.
JP20 "A/V ENABLE" – The Video DAC, Audio Codec, PS2 Ports, and Buzzer are connected to the FPGA by way of bus switches.
Installing this jumper will enable the switches, thereby connecting the peripherals to the FPGA. Removing this jumper will disable the
switches, disconnecting the peripherals from the FPGA. This may be desirable if the 50-pin I/O header is to be used instead of the A/V
peripherals.
Default: Installed; A/V peripherals enabled.
JP21 "CODEC CLK DISABLE" – Installing this jumper will disable the 24.576MHz oscillator to the Codec.
Default: Uninstalled, codec oscillator enabled
JP22 "AUDIO EN" – When uninstalled, the Codec is held in reset by a resistor pull-down. When installed, the reset line is connected to
the FPGA, allowing it to take the codec out of reset.
Default: Installed, FPGA controls reset line.
JP23 "VIDEO CLK DISABLE" – Installing this jumper will disable the 25.175MHz oscillator to the video DAC.
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Figure 13 - I/O Voltage Selection Banks 4&5
Figure 14 - I/O Voltage Selection Banks 1&2
Figure 15 - I/O Voltage Selection Banks 2&3
11 of 33 Rev 1.0 04/17/2006
Literature # ADS-005104