Figure 10 - Fly Wire Connection J1; Table 5 - Fpga Configuration From Prom - Avnet Xilinx Spartan-3 User Manual

Configuration Mode
(M0 : M1 : M2)
Master Serial DEFAULT
(0:0:0)
Master Parallel (Master SelectMAP)
(1:1:0)
Slave Serial
(1:1:1)
Slave Parallel (Slave SelectMAP)
(0:1:1)
Design Revisioning With Platform Flash
The Spartan-3 Development Board is designed to support the advanced features of the parallel Platform Flash PROM
including support for multiple design revisions and compressed configuration files. These features are disabled by the default
jumper settings. If an MCS (prom file) has been built with multiple revisions, use the "BIT SEL" jumper (JP3) to select the
desired revision. By default, no jumpers are installed and rev 0 will be loaded. To load revision 1, a jumper would be placed
at JP3 position 1-2.
2.2.3 Custom Configuration Methods
In addition to JTAG chain signals, J1 provides the user with an interface to the FPGA dedicated and dual function
programming pins. This enables fly-wire support for the programming methods mentioned above and gives flexibility for
developing a custom programming solution.
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Released
Prom Clock En
JP24
Table 5 – FPGA Configuration from PROM ... Jumper Setting

Figure 10 - Fly Wire Connection J1

9 of 33
Prom Enable Mode Jumpers
JP25 JP2
Notes
DEFAULT
FPGA provides CCLK
FPGA provides CCLK
PROM provides CCLK
PROM provides CCLK
Rev 1.0 04/17/2006
Literature # ADS-005104