Table 18 - Lvds Fpga Pin-Out - Avnet Xilinx Spartan-3 User Manual

LVDS_N14
LVDS_P15
LVDS_N15
LVDS_P16
LVDS_N16
LVDS_P17
LVDS_N17
LVDS_P18
LVDS_N18
LVDS_P19
LVDS_N19
LVDS_P20
LVDS_N20
LVDS_P21
LVDS_N21
LVDS_P22
LVDS_N22
LVDS_P23
LVDS_N23
LVDS_P24
LVDS_N24
LVDS_P25
LVDS_N25
LVDS_P26
LVDS_N26
LVDS_P27
LVDS_N27
LVDS_P28
LVDS_N28
LVDS_P29
LVDS_N29
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Released
95.46237
95.94724 R133
95.16314
95.79405 R134
95.24426
95.15417 R135
95.72406
95.93547 R136
95.3271
95.80103 R137
95.04219
95.85368 R138
95.19809
95.96422 R139
95.27415
95.80083 R140
95.09904
95.86594 R141
95.2591
95.95932 R142
95.03457
95.93609 R143
95.03483
95.97747 R144
95.21863
95.93873 R145
95.33188
95.81595 R146
95.05711
95.94143 R147
95.18259

Table 18 - LVDS FPGA Pin-out

22 of 33
32 M19
104 P19
103 P20
110 R21
109 R22
42 N24
41 N23
113 T21
112 T22
45 P21
44 P22
116 U23
115 U24
48 T25
47 T26
51 U25
50 U26
122 W25
121 W26
54 V24
53 V25
125 R19
124 R20
57 V22
56 V23
128 T19
127 T20
60 Y25
59 Y26
63 AC25
62 AC26
Rev 1.0 04/17/2006
Literature # ADS-005104