Table 9 - Oled Display Pin-Out - Avnet Xilinx Spartan-3 User Manual

2.5.2 128x64 OSRAM Pictiva™ OLED Graphics Display
Manufacturer: OSRAM
Part #: OS128064PK16MY0A00
128 Pixels
1
128x64 OLED
Graphics Display
The Spartan-3 Development board includes a 128x64 OSRAM Pictiva™ OLED(Organic Light Emitting Diode) graphics display. This is
a 4-bit per pixel (grayscale) single-color passive matrix display. The display has a contrast ratio of 100:1 and a 160° viewing angle.
The Pictiva displays are available in serial or parallel interface, although applications in this kit use the 8-bit parallel interface.
The parallel bus interface is compatible with 68-series and 80-series microcontrollers and is selectable at pin 4 of the ribbon cable (see
pinout below). This will affect the function of several other pins as noted in the table below. The Spartan-3 Dev board uses a resistor
jumper (JT5) to select the desired level of pin 4. By default the jumper is placed at pads 1-2 for a logic high enabling an 80-series
interface. This placement is subject to change based on future demo applications.
Display
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
The OLED drive voltage (VLL) must be between 12V and 16V. However, it requires very little operating current. Typical ILL is 20-
24mA. So an on-board 12V supply could be used with little affect on the power budget. If there is no 12V supply on board, one may
design in a low-cost, low-power 12V source. The Spartan-3 Dev board uses a National Semiconductor LM2704 Micropower Step-up
DC/DC Converter. This small (SOT23) converter has an input range of 2.2V-7V and an adjustable output up to 20V.
For more display information visit
For power supply information please see www.national.com.
It should be noted that the 2x20 Character display and 128x64 graphics display share a common data bus. In designs where only one
of the displays is to be used, the other's Enable (or CS) pin should be driven inactive using the FPGA. This will help avoid bus
contention. An alternative is to simply remove the unused display from the board. The following table illustrates the pins which are
common as well as the corresponding pin on the FPGA.
Copyright © 2003 Avnet, Inc. AVNET and the AV logo are registered trademarks of Avnet, Inc. All other trademarks are property of their respective owners.
Avnet Electronics Marketing
Released
64 Pixels
Pin Name I/O
CS# I Chip Select – Active Low
RES# I Reset – Active Low
BS1 I Interface Protocol Select.
D/C# I Data / Command
R/W# (WR#) I Read/Write in 68 series mode
Write strobe in 80-series mode
E (RD#) I E clock in 68-series mode
Read strobe in 80-series mode
D0 I/O
D1 I/O
D2 I/O
D3 I/O
D4 I/O
D5 I/O
D6 I/O
D7 I/O
VSSB I
VDD I Positive supply (2.4V – 3.5V)
VCC(VLL) I OLED Drive power (12V – 16V)
VSS I

Table 9 - OLED Display Pin-out

www.osram-os.com or www.pictiva.com.
16 of 33
4-Bits/Pixel Single Color Graphics Display
Description
LOW = 68-series
HIGH = 80-series
HIGH = Bus contains data for DDRAM
LOW = Bus contains command
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
n/c
Ground
FPGA
Pin#
AA4
AA6
-
P8
Y7
Y10
AE21
AF21
AE20
AF20
AE19
AE18
AE17
AD14
-
-
-
-
Rev 1.0 04/17/2006
Literature # ADS-005104