Figure 8. Jtag, Jtag Lfast & Sipi - STMicroelectronics SPC58XCADPT176S User Manual

JTAG interfac e
C56 47nF
Place CAPS as close to VDD_HV_IO_JTAG VDD_HV_IO_JTAG
connector pins as DNP
possible but do NOT fit
C57 47nF
caps at board assembly.
R25
DNP DNP
GND JTAG Connector
J18
TDI 1 2
TDI
TDO 3 4
TDO
TCK 5 6
(pg3) TCK
EVTI EVTI_0/EVTO_0 7 8
( g p ) 3 E V I T
9 10
PORST_ESR0
11 12
EVTO 13 14
(pg3) EVTO
N2514-6002RB
TDI, TDO, TCK, TMS & JCOMP are not connected to
daughter card.
PORST, ESR0, EVTI and EVTO are connected to daughtercard
JCOMP
JCOMP
TMS
TMS
PORST
(pg3,5) PORST
Figure 8. JTAG, JTAG LFAST & SIPI
VDD_HV_IO_JTAG
(VSS)
(VSS) R3
(VSS) R28 10K
DNP
TMS J41
(pg3)
(VSS) DNP 1
(pg3) EVTO (pg3)
JCOMP
(pg3)
2
3
(pg3,5) ESR0
R4
10K STRIP 2mm
GND
SIPI interface
J20
SIPI_TXP 1 2
(pg3) SIPI_TXP
SIPI_TXN 3 4
(pg3) SIPI_TXN
5 6 DRCLK
SIPI_RXN 7 8
(pg3) SIPI_RXN
SIPI_RXP
9 10
(pg3) SIPI_RXP
11 12
R24 100R
ERF8-005-05.0-L-DV-L-TR
DNP
GND GND
Previson Eiger DC-DC Regulato r
SMPS_REGULATOR_OUT
VDD_HV_IO_MAIN
J36 J37
1 1
2 2
3 PIN 140 3
(smps_vlx)
4 PH0 4
5 PIN 138 PG15 5
6 (smps_pmos0) PH1 6
PIN 141
STRIP (smps_nmos1) STRIP
GND
(pg3,6) PH[0..15]
(pg3,6) PG[0..15]
JTAG/LFAST LVDS INTERFAC E
10 Pin Versio n
VDD_HV_IO_JTAG
JCOMP TMS TDI TDO
C132
R17 100R
C133
DNP
R18 R19 R20 R21 R22
0R 0R DNP 0R 0R
GND
CN1
GND
1 2
3 4
JCOMP_RxDATA_N TDO_RxDATA_P
5 6
TMS_TxDATA_P TDI_TxDATA_N
7 8
EVTI VDD_HV_IO_JTAG
9 10
R23 SAMTEC TFM-105-02-L-D-WT
DNP
GND
GND
PF14
PF14 (pg3,6)
0603 DNP
0603 DNP
TCK (pg3)
J42
(pg3)
1
PORST (pg3,5)
(pg3)
2
3
ESR0 (pg3,5)
C134
27pF STRIP 2mm
0603 PORST_ESR0
GND