Reset Behavior Of Io Port Pins; Additional Information - Cypress FR81S CY91F52 Series Recommendation For Hardware Setup

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Reset Behavior of IO port pins

This chapter shows the behavior of IO-Port during and after RESET
During the power-on or RSTX reset state the GPIO port pins are going to HiZ and the inputs are disabled to prevent
the leakage by any floating pin. After release of reset the IO-ports will be set to initial value (see also related DS of
FR81S series)
Pin
X0/X1
X0A/X1A
Gpio port pins
If some external bus pins should be used as GPIO than do not use any address or bus control lines as input, because
these lines are driven as output high.
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Additional Information

Information about CYPRESS Microcontrollers can be found on the following Internet page:
http://www.cypress.com/cypress-microcontrollers
Related documents for further information are listed in the table below:
Ref. #
1 CY91520 Series 32-Bit Microcontroller FR Family
FR81S Hardware Manual
2 CY91520 Series 32-Bit FR81S Microcontroller
3 CY91590 Series FR81S Hardware Manual
4 CY91590 Series FR Family FR81S 32-Bit
Microcontroller
www.cypress.com
Table 9. Power-On/RSTX reset state GPIO initial state
Function
Main oscillator
Sub oscillator
GPIO
Table 10. Related Documents
Document file name
Document No. 002-09375 Rev. *B
Recommendation for Hardware Setup 32-Bit FR81S Family
Initial state
Running
Running
Input disabled HiZ
Description
FR81S CY91520 Series Hardware Manual
FR Family FR81S, CY91520 Series datasheet
FR81S CY91590 Series Hardware Manual
FR Family FR81S, CY91590 Series datasheet
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