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Related Manuals for Cypress FR Series
Summary of Contents for Cypress FR Series
- Page 1 The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will offer these products to new and existing customers with the series name, product name, and ordering part number with the prefix “CY”.
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Page 2: Table Of Contents
CAN clock CLKCAN. The CLKB provides the clock to the CPU. The CLKCAN provides the clock to the CAN controllers. The CLKP provides the clock for all other peripherals. Each of these four clocks features a separate prescaler. The following block diagram shows the clock distribution. www.cypress.com Document No. 002-05317 Rev. *C... -
Page 3: Rc Clock
The PLL Clock is available on all FR devices and is based on the Main Clock. By default, it is disabled. Before enabling it, it must be configured. The PLL Clock also feeds the Clock Modulator. The Clock Modulator is discussed in subsequent sections. www.cypress.com Document No. 002-05317 Rev. *C... -
Page 4: Sub Clock
Example: Let’s consider the case where the required Modulated PLL Clock - CLKMOD is 16 MHz with the desired baud rate for the USART in asynchronous mode is 2 MBPS. www.cypress.com Document No. 002-05317 Rev. *C... - Page 5 “± phase skew min/max” would be 7.875. This means that the 80 clock periods would be either shortened to 72.125 clock periods or may get lengthened to 87.875 clock period that is the error of up to 1 bit. This may cause parity error or framing error respectively at the receiver. www.cypress.com Document No. 002-05317 Rev. *C...
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Page 6: Registers
(relative to the base clock) 0001 Base clock / 2 T3,T2, 7,6,5,4 for the clock used by the 0000 T1,T0 … … external bus interface (CLKT). 1111 Base clock / 16 3,2,1,0 Undefined Always write 0 www.cypress.com Document No. 002-05317 Rev. *C... -
Page 7: Clock Source Configuration Register (Cscfg)
Sub clock Calibration is sourced by RC Oscillator(100kHz) Real Time Clock is sourced by Main Oscillator Real Time Clock is sourced by Sub CSC1, Clock Source Selection for Oscillator CSC0 Real Time Clock is sourced by RC Oscillator(100kHz) Setting prohibited www.cypress.com Document No. 002-05317 Rev. *C... -
Page 8: Oscillation Control Register (Osccr)
Initial Value Value Operation Undefined Always write 0 0000 CLKPLL/ 1 0000* 0001 CLKPLL/ 2 DVN5-0 PLL divide-by-N selection XXXX … … 1111 CLKPLL/ 16 * INITX pin input, watchdog reset + Software reset www.cypress.com Document No. 002-05317 Rev. *C... -
Page 9: Pll Control Registers (Plldivg)
Interrupt Request Enable IEUP Gear UP Gear UP interrupt request enabled Gear UP interrupt not active GRUP Interrupt Flag Gear UP Gear UP interrupt active * INITX pin input, watchdog reset + Software reset www.cypress.com Document No. 002-05317 Rev. *C... -
Page 10: Clock Supervisor Control Register (Csvcr)
Missing Sub clock has been detected Missing Main clock has not been detected SRST Sub clock mode reset Missing Main clock has been detected 32k oscillation used as Sub clock OUTE Output enable RC oscillation used as Sub clock www.cypress.com Document No. 002-05317 Rev. *C... -
Page 11: Clock Modulator Control Register (Cmcr)
The modulation parameter determines the degree of modulation and the maximal and minimal occurring frequencies in the modulated clock. Refer to the Hardware Manual for a description of an approach to select the optimal setting. www.cypress.com Document No. 002-05317 Rev. *C... -
Page 12: Using The Start.asm
Beside these configurations, there is the possibility to define a user configuration in the chapter 5 "Definition of CLOCK_SPEED CLOCK_USER Configurations". Set the parameter and the parameters mentioned in chapter 5.1 CLOCKSPEED == CLOCK_USER to desired values. www.cypress.com Document No. 002-05317 Rev. *C... - Page 13 ; <<< 0x7002h: FCHCR; #set FLASHREADT 0xC413 ; <<< 0x7004h: FMWT; #set FLASHMWT2 0x10 ; <<< 0x7006h: FMWT2; #endif ;============================================================================ ; 5.2 CLOCKSPEED == NO_CLOCK ;============================================================================ #if (CLOCKSPEED == NO_CLOCK) #set CLOCKSOURCE NOCLOCK #endif www.cypress.com Document No. 002-05317 Rev. *C...
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Page 14: Clock Setup Sequence
To avoid voltage drops and surges when switching the clock source from oscillator to high frequency PLL/ DLL output (or vice versa), a clock smooth gear-up and gear-down circuitry is implemented with the PLL interface. www.cypress.com Document No. 002-05317 Rev. *C... -
Page 15: Clock Setup Sequence (Example)
(PLLCTRL: IEUP, PLLCTRL: IEDN). Wait for the PLL stabilization time. Set the base clock division registers (DIVR0, DIVR1). Switch the clock source to the PLL (CLKR.CLKS “00”-> “10”) www.cypress.com Document No. 002-05317 Rev. *C... - Page 16 DIVR0 |= peripheral_clock_div; DIVR1 = 0x00; DIVR1 = external_bus_clock_div << 4; /* Set the PLL interface registers (N, M, DG, MG) */ PLLDIVM = counter_m; PLLDIVN = counter_n; PLLDIVG = counter_g; PLLMULG = counter_mulg; //gear steps www.cypress.com Document No. 002-05317 Rev. *C...
- Page 17 /* Wait for gear UP */ if(counter_g) /*if counter_g == 0; */ /* auto gear disabled so the flag will not be set*/ while ((!PLLCTRL_GRUP)){ HWWD = 0x10; HWWD = 0x10; PLLCTRL_GRUP = 0; www.cypress.com Document No. 002-05317 Rev. *C...
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Page 18: Clock Modulator Configuration
In order to power down the clock modulator its needs to be disabled (using the MODEN bit of CMCR register). After that, once the MODRUN bit gets cleared to zero, the clock modulator can be powered down. www.cypress.com Document No. 002-05317 Rev. *C... -
Page 19: Clocks Example
The following example demonstrates how to stop the clock modulator. SAMPLE CODE /*---------------------------------------------------------------------------*/ . . . CMCR_FMOD = 0; // modulation disable while (0 != CMCR_FMOD_RUN); // wait till modulator is disabled CMCR_PDX = 0; // power down clock modulator . . . www.cypress.com Document No. 002-05317 Rev. *C... -
Page 20: Additional Information
FR, MB91460, FR Clocks Additional Information Information about Cypress Microcontrollers can be found on the following Internet page: http://www.cypress.com/cypress-microcontrollers The software examples related to this application note is: 91460_Clock_Modulator 91460_Clock_Setting It can be found on the following Internet page: http://www.cypress.com/cypress-mcu-product-softwareexamples www.cypress.com... -
Page 21: Document History
Description of Change Change Date NOFL 04/24/2008 V1.0, First draft, HPi 05/19/2008 V1.1, Updated Chapter 5, HPi 06/04/2008 V1.2, Updated Chapter 5, HPi Converted Spansion Application Note “MCU-AN-300066-E-V12” to Cypress 5090735 NOFL 04/13/2016 format 5869105 AESATMP9 08/31/2017 Updated logo and copyright. 6059091... - Page 22 Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
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