User Manuals: Cypress FM4 Series Microcontrollers

Manuals and User Guides for Cypress FM4 Series Microcontrollers. We have 1 Cypress FM4 Series Microcontrollers manual available for free PDF download: Peripheral Manual

Cypress FM4 Series Peripheral Manual (1102 pages)

32-Bit

Brand: Cypress | Category: Microcontrollers | Size: 13 MB

Table of Contents
10
CHAPTER 1: System Overview

23
- Bus Architecture
  24
  - Bus Block Diagram
    26
  - Memory Architecture
    27
  - Memory Map
    28
  - Peripheral Address Map
    29
- Cortex-M4F Architecture
  32
  - Option Configuration
    35
- Mode
  36
CHAPTER 2-1: Clock

37
CHAPTER 3: Clock Supervisor

139
- Overview
  140
- Configurations and Block Diagrams
  141
- Explanation of Operations
  143
- Setup Procedure Examples
  144
- Operation Examples
  146
- Registers
  150
CHAPTER 4: Resets

159
- Overview
  160
- Configuration
  161
- Explanation of Operations
  162
  - Reset Factors
    163
  - Resetting Inside the Device
    166
    
    Resets to Cortex-M4
    167
    
    Resets to Peripheral Circuit
    168
  - Reset Sequence
    169
  - Operations after Resets Are Cleared
    171
- Register
  172
  - Reset Factor Register (RST_STR: Reset Status Register)
    173
CHAPTER 5: Low-Voltage Detection

175
CHAPTER 6: Low Power Consumption Mode

189
CHAPTER 7-1: VBAT Domain Configuration

243
- Configuration
  244
- CHAPTER 7-2: VBAT Domain(A)
  245
  - Overview of VBAT Domain
    246
  - Configuration of VBAT Domain
    248
    
    Interfacing with Always-On Domain
    249
    
    Rtc
    259
    
    32 Khz Oscillation Circuit
    260
    
    Power-On Circuit
    262
    
    Backup Registers
    263
    
    VBAT I/O Ports
    265
    
    Chip Power Supply Control
    268
    
    Hibernation Control
    271
    
    Procedure for Setting 32 Khz Clock
    275
    
    Procedure for Setting VBAT I/O Port
    279
    
    Registers
    282
    
    VB_CLKDIV Register
    283
    
    WTOSCCNT Register
    284
    
    CCS/CCB Register
    285
    
    BOOST Register
    286
    
    EWKUP Register
    287
    
    HIBRST Register
    288
    
    VDET Register
    289
    
    Port Function Set Register (VBPFR)
    290
    
    Pull-Up Set Register (VBPCR)
    292
    
    Port I/O Direction Set Register (VBDDR)
    293
    
    Port Input Data Register (VBDIR)
    294
    
    Port Output Data Register (VBDOR)
    295
    
    Port Pseudo-Open Drain Set Register (VBPZR)
    296
    
    Usage Precautions
    297
- CHAPTER 7-3: VBAT Domain(B)
  299
  - Overview of VBAT Domain
    300
  - Configuration of VBAT Domain
    302
    
    Interfacing with Always-On Domain
    303
    
    Rtc
    313
    
    32 Khz Oscillation Circuit
    314
    
    Power-On Circuit
    316
    
    Backup Registers
    317
    
    VBAT I/O Ports
    319
    
    Chip Power Supply Control
    322
    
    Hibernation Control
    325
    
    Procedure for Setting 32 Khz Clock
    329
    
    Procedure for Setting VBAT I/O Port
    333
    
    Registers
    336
    
    VB_CLKDIV Register
    337
    
    WTOSCCNT Register
    338
    
    CCS/CCB Register
    339
    
    BOOST Register
    341
    
    EWKUP Register
    342
    
    HIBRST Register
    343
    
    VDET Register
    344
    
    Port Function Set Register (VBPFR)
    345
    
    Pull-Up Set Register (VBPCR)
    347
    
    Port I/O Direction Set Register (VBDDR)
    348
    
    Port Input Data Register (VBDIR)
    349
    
    Port Output Data Register (VBDOR)
    350
    
    Port Pseudo-Open Drain Set Register (VBPZR)
    351
  - Usage Precautions
    352
CHAPTER 8: Interrupts

353
CHAPTER 9: External Interrupt and NMI Control Sections

437
Chapter 10: Dmac

453
- Overview of DMAC
  454
- Configuration of DMAC
  455
  - DMAC and System Configuration
    456
  - I/O Signals of DMAC
    458
  - Functions and Operations of DMAC
    460
    
    Software-Block Transfer
    461
    
    Software-Burst Transfer
    463
    
    Hardware-Demand Transfer
    464
    
    Hardware-Block Transfer & Burst Transfer
    465
    
    Channel Priority Control
    467
  - DMAC Control
    468
    
    Overview of DMAC Control
    469
    
    DMAC Operation and Control Procedure for Software Transfer
    470
    
    DMAC Operation and Control Procedure for Hardware (EM=0) Transfer
    477
    
    DMAC Operation and Control Procedure for Hardware (EM=1) Transfer
    486
  - Registers of DMAC
    490
    
    List of Registers
    491
    
    Entire DMAC Configuration Register (DMACR)
    492
    
    Configuration a Register (DMACA)
    494
    
    Configuration B Register (DMACB)
    497
    
    Transfer Source Address Register (DMACSA)
    500
    
    Transfer Destination Address Register (DMACDA)
    501
  - Usage Precautions
    502
Chapter 11: Dstc

503
- Overview of DSTC
  504
- DSTC Operations Overview and DSTC System Configuration
  505
  - Operations Overview of DSTC
    505
  - DSTC and System Configuration
    507
- Functions and Operations of DSTC
  510
  - Settings of des
    511
    
    Specifying Transfer Data Size
    511
    
    Setting Transfer Addresses
    512
    
    Specifying Outerreload
    514
    
    Setting Chain Start and Transfer End Notification
    517
    
    Other des Settings
    519
    
    Control Functions of DSTC
    522
    
    Control of SW Transfer
    522
    
    DESTP Register
    522
    
    DSTC Internal Block Diagram
    522
    
    Control of HW Transfer
    523
    
    Arbitration of Transfer Requests
    524
    
    Operation of the Transfer End
    526
    
    Read Skip Buffer Function
    526
    
    MONERS Register
    527
    
    Standby Function
    529
    
    Operation Flows of DSTC
    531
    
    SW Transfer Flow
    531
    
    HW Transfer Flow
    534
    
    Operation Flow after Specifying of DESP
    536
- Examples of DSTC Operations and Control
  539
  - Transfer Operation Example 1
    540
  - Transfer Operation Example 2
    543
  - Transfer Operation Example 3
    545
  - Transfer Operation Example 4
    547
  - Transfer Operation Example 5
    549
  - Examples of Controlling DSTC
    552
- Registers and Descriptors of DSTC
  556
  - Lists of Control Registers and des
    557
  - DESTP Register
    558
  - Hwdesp[N] Register
    559
  - CMD Register
    560
  - CFG Register
    561
  - SWTR Register
    563
  - MONERS Register
    564
  - Dreqenb[N] Register
    567
  - Hwint[N] Register
    568
  - Hwintclr[N] Register
    569
  - Dqmsk[N] Register
    570
  - Dqmskclr[N] Register
    571
  - Descriptor 0 (DES0)
    572
  - Descriptor 1 (DES1)
    576
  - Descriptor 2 (DES2)
    578
  - Descriptor 3 (DES3)
    578
  - Descriptor 4 (DES4)
    579
  - Descriptor 5 (DES5)
    579
  - Descriptor 6 (DES6)
    579
CHAPTER 12: I/O Port

581
CHAPTER 13: CRC (Cyclic Redundancy Check)

741
- Overview of CRC
  742
- CRC Operations
  743
  - CRC Calculation Sequence
    744
  - CRC Use Examples
    745
- CRC Registers
  749
  - CRC Control Register (CRCCR)
    750
  - Initial Value Register (CRCINIT)
    752
  - Input Data Register (CRCIN)
    753
  - CRC Register (CRCR)
    754
CHAPTER 14: External Bus Interface

755
- Overview of External Bus Interface
  756
- Block Diagram
  758
- Operations
  761
  - Bus Access Mode
    762
  - SRAM and nor Flash Memories Access
    767
  - NAND Flash Memory Access
    769
    
    Read Access to NAND Flash Memory
    770
    
    Write (Auto Program) Access
    771
    
    Auto Block Erase Access
    772
  - Issue of an 8-Bit NAND Flash Memory Read/Write Command
    773
  - 8-Bit NAND Flash Memory Status Read
    774
  - 8-Bit NAND Flash Memory Data Write
    775
  - Automatic Wait Setup
    776
  - External RDY
    781
  - SDRAM Access
    782
  - Interrupt Function
    788
  - Access Mode
    789
  - SDRAM Buffer Read (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products)
    792
- Connection Examples
  794
- Setup Procedure Example
  799
- Registers
  803
CHAPTER 15: SD Card Interface

841
- Overview of SD Card Interface
  842
- Registers
  843
  - SDMA System Address / Argument 2 Register
    845
  - Block Size Register
    846
  - Block Count Register
    847
  - Argument 1 Register
    848
  - Transfer Mode Register
    849
  - Command Register
    850
  - Response Register
    851
  - Buffer Data Port Register
    852
  - Present State Register
    853
  - Host Control 1 Register
    854
  - Power Control Register
    855
  - Block Gap Control Register
    856
  - Wakeup Control Register
    857
  - Clock Control Register
    858
  - Timeout Control Register
    859
  - Software Reset Register
    860
  - Normal Interrupt Status Register
    861
  - Error Interrupt Status Register
    862
  - Normal Interrupt Status Enable Register
    864
  - Error Interrupt Status Enable Register
    865
  - Normal Interrupt Signal Enable Register
    866
  - Error Interrupt Signal Enable Register
    867
  - Auto CMD Error Status Register
    868
  - Host Control 2 Register
    869
  - Capabilities Register
    870
  - Maximum Current Capabilities Register
    874
  - Force Event Register for Auto CMD Error Status
    875
  - Force Event Register for Error Interrupt Status
    876
  - ADMA Error Status Register
    878
  - ADMA System Address Register
    879
  - Preset Value Registers
    880
  - Shared Bus Control Register
    881
  - Slot Interrupt Status Register
    883
  - Host Controller Version Register
    884
  - AHB Config Register
    885
  - Power Switching Register
    889
  - Tuning Setting Register
    890
  - Tuning Status Register
    894
  - Power Switching Interrupt Status Register
    896
  - Power Switching Interrupt Status Enable Register
    897
  - Power Switching Interrupt Signal Enable Register
    898
  - MMC/Esd Control Register
    899
  - MMC Wait IRQ Control Register
    903
  - MMC Wait IRQ Control Register
    905
  - MMC Response Check Bit Register
    906
  - Card Detect Setting Register
    907
- MMC Boot Operation
  908
  - Example of Controlling Alternative Boot Mode (Using ADMA)
    910
- MMC Wait IRQ
  912
  - Example of Controlling Wait IRQ
    912
- Sdclk
  914
CHAPTER 16: Debug Interface

915
- Overview and Configuration
  916
- Pin Description
  917
  - Pins for Debug Purposes
    918
  - Trace Pins
    919
  - Functions Initially Assigned to Pins
    920
  - Internal Pull-Ups of JTAG Pins
    921
CHAPTER 17: Flash Memory

923
CHAPTER 18: Unique ID Register

925
- Overview
  926
- Registers
  927
  - Unique ID Register 0 (UIDR0: Unique ID Register 0)
    928
  - Unique ID Register 1 (UIDR1: Unique ID Register 1)
    929
CHAPTER 19: Programmable CRC

931
Appendixes

955
- Register Map
  956
  - Register Map
    958
  - Flash_If
    959
    
    TYPE1-M4, TYPE2-M4 Products
    959
    
    TYPE3-M4 Product
    960
- TYPE4-M4, TYPE5-M4, TYPE6-M4 Products
  961
- Unique ID
  962
- ECC Capture Address
  962
- Clock/Reset
  963
  - TYPE1-M4, TYPE2-M4 Products
    963
  - TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products
    965
- Hw Wdt
  967
- Sw Wdt
  967
- Dual_Timer
  968
- Mft
  969
  - TYPE1-M4, TYPE2-M4 Products
    969
  - TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products
    972
- Ppg
  975
- Base Timer
  978
- IO Selector for Base Timer
  979
- Qprc
  980
  - TYPE1-M4, TYPE2-M4, TYPE6-M4 Products
    980
  - TYPE3-M4, TYPE4-M4, TYPE5-M4 Products
    981
- Qprc Nf
  982
- A/DC
  983
- CR Trim
  984
- Exti
  985
  - TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE4-M4 Products
    985
  - TYPE5-M4, TYPE6-M4 Products
    985
- INT-Req. READ
  986
  - TYPE1-M4, TYPE2-M4, TYPE6-M4 Products
    986
  - TYPE3-M4, TYPE5-M4 Product
    992
  - TYPE4-M4 Product
    999
- D/Ac
  1006
- Hdmi-Cec
  1007
- Gpio
  1008
  - TYPE1-M4, TYPE2-M4, TYPE6-M4 Products
    1008
  - TYPE3-M4 Product
    1015
  - TYPE4-M4 Product
    1024
  - TYPE5-M4 Product
    1032
- Lvd
  1041
- Ds_Mode
  1041
- USB Clock
  1042
- Can_Prescaler
  1043
- Mfs
  1043
- Crc
  1045
- Watch Counter
  1045
- Rtc
  1046
  - TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE6-M4 Products
    1046
  - TYPE4-M4 Product
    1049
  - TYPE5-M4 Product
    1053
- Low-Speed CR Prescaler
  1054
- Peripheral Clock Gating
  1055
  - TYPE1-M1, TYPE2-M4 Products
    1055
  - TYPE3-M4, TYPE4-M4 Products
    1055
  - TYPE5-M4, TYPE6-M4 Products
    1056
    
    Smart Card Interface
    1057
    
    Mfsi2S
    1058
    
    I2S Prescaler
    1059
    
    TYPE1-M4, TYPE2-M4, TYPE3-M4 Products
    1059
    
    TYPE4-M4 Product
    1060
    
    Gdc_Prescaler
    1061
    
    EXT-Bus I/F
    1062
    
    TYPE1-M4 Product
    1062
    
    TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products
    1065
    
    Usb
    1068
    
    Dmac
    1070
    
    Dstc
    1072
    
    Can
    1074
    
    Ethernet-Control
    1076
    
    Ethernet-MAC
    1076
    
    I2S
    1077
    
    SD-Card
    1077
    
    Can Fd
    1078
    
    Programmable-CRC
    1081
    
    Workflash_If
    1081
    
    High-Speed Quad SPI Controller
    1082
    
    TYPE1-M4, TYPE2-M4, TYPE3-M4 Products
    1082
    
    TYPE4-M4 Product
    1085
    
    Hyperbus Interface
    1088
    
    GDC Sub System Controller
    1089
    
    GDC Sub System SDRAM Controller
    1092
  - B List of Notes
    1093
    
    Notes When High-Speed CR Is Used for the Master Clock
    1094
  - C Major Changes
    1096
    
    Major Changes
    1097
Revision History

1101

Cypress Categories

Microcontrollers Motherboard Media Converter Computer Hardware

Switch

More Cypress Manuals

User Manuals: Cypress FM4 Series Microcontrollers

Cypress FM4 Series Peripheral Manual (1102 pages)

Table of Contents

CHAPTER 1: System Overview

CHAPTER 2-1: Clock

CHAPTER 3: Clock Supervisor

CHAPTER 4: Resets

CHAPTER 5: Low-Voltage Detection

CHAPTER 6: Low Power Consumption Mode

CHAPTER 7-1: VBAT Domain Configuration

CHAPTER 8: Interrupts

CHAPTER 9: External Interrupt and NMI Control Sections

Chapter 10: Dmac

Chapter 11: Dstc

CHAPTER 12: I/O Port

CHAPTER 13: CRC (Cyclic Redundancy Check)

CHAPTER 14: External Bus Interface

CHAPTER 15: SD Card Interface

CHAPTER 16: Debug Interface

CHAPTER 17: Flash Memory

CHAPTER 18: Unique ID Register

CHAPTER 19: Programmable CRC

Appendixes

Revision History

Related Products

Cypress Categories