Table of Contents
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Recommendation for Hardware Setup 32-Bit FR81S Family
This application note describes how to set up a hardware environment for Cypress FR81S MCUs. As an example, the
CY91F52x MCU is used.
Contents
1 Introduction .................................................................. 1
2 Minimal System ........................................................... 2
2.1 Schematic ........................................................... 2
2.2 Serial Interface .................................................... 2
2.3 Power supply ...................................................... 2
2.4 Analog Digital Converter Supply Pins ................. 2
2.5 Analog Input Pins ................................................ 3
2.6 Reset Pin (RSTX) ............................................... 4
2.7 Non maskable Interrupt Pin (NMIX) .................... 4
2.8 C-Pin ................................................................... 5
2.9 Clock Source ....................................................... 5
2.10 Mode Pins ........................................................... 6
2.11 Not Connected Pins ............................................ 6
2.12 Debug Interface connection ................................ 7
3 Layout and Electromagnetic Compatibility ................... 8
3.1 General ............................................................... 8
3.2 Power supply Pins .............................................. 8
3.3 Oscillator Pins ..................................................... 9
3.4 Power Line Routing ............................................. 9
3.5 Power Supply Decoupling ................................. 10
3.6 Recommended Power Supply Circuit ............... 12
1
Introduction
This design guide describes design restrictions and recommendations regarding signal wiring and the electrical power
system of the MCU. For more details about the device features and its relevant settings, please refer to the FR81S
Hardware Manual and its corresponding Datasheet for electrical characteristics.
www.cypress.com
3.7 Reset circuit ...................................................... 13
3.9 Test points ........................................................ 18
3.10 Other documents .............................................. 18
4 Port Input / Unused Pins / Latch-up ........................... 19
4.1 Port Input / Unused Pins ................................... 19
4.2 Latch-up consideration (switch) ........................ 20
4.3 5 V Tolerant Input pins ...................................... 24
5 Flash Programming Connection ................................ 25
5.1 Overview ........................................................... 25
5.2 Serial programming via UART0 ........................ 25
5.3 Serial programming via MDI interface ............... 27
5.4 Parallel programming interface ......................... 29
5.5 Security function ............................................... 29
6 Reset Behavior of IO port pins .................................. 30
7 Additional Information ................................................ 30
Worldwide Sales and Design Support ............................. 32
Cypress Developer Community....................................... 32
Technical Support ........................................................... 32
Document No. 002-09375 Rev. *B
AN209375
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Related Manuals for Cypress FR81S CY91F52 Series
Summary of Contents for Cypress FR81S CY91F52 Series
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Page 1: Table Of Contents
AN209375 Recommendation for Hardware Setup 32-Bit FR81S Family This application note describes how to set up a hardware environment for Cypress FR81S MCUs. As an example, the CY91F52x MCU is used. Contents 1 Introduction ..............1 3.7 Reset circuit ............13 2 Minimal System ............ -
Page 2: Minimal System
The analog converter supply pins (AVCCn, AVRHn / AVRLn, AVSSn) should be connected even if the ADC of the MCU is not used. Please refer to our application note “mcu-an-300215-e-16fx_adc” for using the ADC and pin connection. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 3: Analog Input Pins
Value AVcc 4.5 V… 5.5 V Cadc 8.30 pF (Max) 3 V… 3.6 V Cadc 8.30 pF (Max) 4.5 V… 5.5 V Radc 1.9K (Max) 3 V… 3.6 V Radc 4.3K (Max) Cpin 5pF..15pF www.cypress.com Document No. 002-09375 Rev. *B... -
Page 4: Reset Pin (Rstx)
The NMIX supports two several functions, (a) using as NMI input and (b) simultaneous assert of RSTX and NMIX pins to generate an irregular reset. There is internal 50k pull-up resistor, but for high noise requirements an external pull-up resistor with typical 10k is recommended. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 5: C-Pin
X0A pin is neither used as GPIO nor as clock input, the pin can be left open. If you want to use only CR clock, then you need a MCU version with disabled CSV. Please also refer to the chapter “Handling the device” in the corresponding hardware manual for details. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 6: Mode Pins
Concerning special use cases, it is referred to Port Input / Unused Pins / Latch-up for how to proceed with unused (not connected) pins. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 7: Debug Interface Connection
L2 wiring length Less than 15 cm. Please check for detailed OCDS layout design rules of the MB2100-01-E (see chapter Flash Programming Connection and the chapter ‘On Chip Debugger: OCD’ of the hardware manual. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 8: Layout And Electromagnetic Compatibility
Dedicated power supply pins for the internal power supply regulator (used to supply the MCU core). External capacitors connected to these pins are required. Please refer to datasheet “C Pin Connection Diagram” reference for further information. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 9: Oscillator Pins
1 nF and 10 µF. ▪ Use ferrite filter for each power domain ▪ Split the used I/O signals in separate layer for low / high speed, and digital / analog signal types www.cypress.com Document No. 002-09375 Rev. *B... -
Page 10: Power Supply Decoupling
DeCaps for power supply have to be placed within the “current flow”. Otherwise they are senseless, because then their function become inoperable. The following graphic illustrates this: Figure 7. Power Supply decoupling caps placement www.cypress.com Document No. 002-09375 Rev. *B... - Page 11 MCU, this solution is the best for high-density board assembly. Figure 9. Power Supply decoupling on double-side assembled boards L1 (MCU) L2 (GND) L3 (VCC) L3 (VCC) L2 (GND) L1 (MCU) www.cypress.com Document No. 002-09375 Rev. *B...
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Page 12: Recommended Power Supply Circuit
Figure 10. Principal Supply circuit Close to MCU pins 100nF 10uF 10uF 100nF AVcc 10uF 10uF 100nF AVRH *R2 (e.g. 10R) : Optional 100nF AVSS *C (e.g. 1nF) : Optional www.cypress.com Document No. 002-09375 Rev. *B... -
Page 13: Reset Circuit
Detector (LVD) and complete reset of the device before program execution starts. The reset signal at RSTX pin goes through a noise filter to avoid any spike on the reset input. Please note there are two types of reset level (RST and INIT). Figure 11. Block Diagram of reset extension circuit www.cypress.com Document No. 002-09375 Rev. *B... - Page 14 Recommendation for Hardware Setup 32-Bit FR81S Family Please see also the datasheet, chapter “External reset timing” of related MCU series. Table 7. External reset timing Figure 12. External reset timing www.cypress.com Document No. 002-09375 Rev. *B...
- Page 15 Recommendation for Hardware Setup 32-Bit FR81S Family Figure 13. Block Diagram of reset extension circuit www.cypress.com Document No. 002-09375 Rev. *B...
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Page 16: Quartz Crystal Placement And Signal Routing
As a result of crystal test maybe will be needed a damping resistor (Rd). Figure 14. Principal Oscillator Circuit CY91F52x Inverter Figure 15. Principal Oscillator Circuit and Startup Sequence www.cypress.com Document No. 002-09375 Rev. *B... - Page 17 MCU, PCB or crystal are replaced for a different one. As a result of this matching test the value of C is provided and then the calculation of C and C can be done using the Equation. www.cypress.com Document No. 002-09375 Rev. *B...
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Page 18: Test Points
MONCLK out could be used e.g. for clock calibration of main or sub oscillator. Figure 18. MONCLK internal clock select and prescaler Table 8. Supported output functions for test purposes 3.10 Other documents For further detailed information please refer to the application notes on the web page. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 19: Port Input / Unused Pins / Latch-Up
Debouncing and decoupling capacitors should always be chosen as smallest as possible. Please refer to Latch-up consideration (switch). All pins are set to input Hi-Z after its power-on default. Therefore set unused pins to input with internal pull-up/down resistor, or provide them with pull-up or pull-down resistors. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 20: Latch-Up Consideration (Switch)
The longer the circuit path is the higher will be its inductivity LX (and capacity CX). An equivalent circuit diagram looks like the following illustration: Figure 21. Usual Configuration Switch, equivalent circuit www.cypress.com Document No. 002-09375 Rev. *B... - Page 21 By closing the switch SW the circuit becomes a parallel oscillator with the wire-inductivity LX, the debouncing capacity and the damping RPD of the pull-down resistor (Assume the power supply to be ideal, i.e. it has no internal resistance): Figure 24. Equivalent circuit on switch closed www.cypress.com Document No. 002-09375 Rev. *B...
- Page 22 (a) Signal on the pin with a large capacity. (b) Signal on the pin with a small capacity This solution has two disadvantages: First the debouncing effect decreases and second, there is no guarantee, that the latch-up condition is eliminated. www.cypress.com Document No. 002-09375 Rev. *B...
- Page 23 VP is within the positive CMOS/TTL/Automotive level. Figure 28. Reduction of the signal on the pin due to the series resistor www.cypress.com Document No. 002-09375 Rev. *B...
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Page 24: Tolerant Input Pins
CY91F52x: P035, P041, P093, P122. Please see also the note *6 in the DS “ELECTRICAL CHARACTERISTICS – Maximum clamp current”. The current limitation with series resistor for + B signal is input is not possible for a 5 V tolerant input. www.cypress.com Document No. 002-09375 Rev. *B... -
Page 25: Flash Programming Connection
CY91F52x MB91F52x RESET FTDI: TTL-232R NMIX P006 To enable the serial programming using this method, you have to configure the Mode pins in an appropriate way (see Figure 30) according to the Table 3. www.cypress.com Document No. 002-09375 Rev. *B... - Page 26 MD0, inverting MD1 and a pull-up resistor on the pin P006. Figure 31. Principal Schematic for serial programming via Usart0 Flash Programming System SOT0_0 SIN0_0 Closed P006 Serial Programming Mode Open User/Run Mode RSTX Reset www.cypress.com Document No. 002-09375 Rev. *B...
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Page 27: Serial Programming Via Mdi Interface
Recommendation for Hardware Setup 32-Bit FR81S Family The software used for flash programming of this MCU series is FR Cypress Serial Programmer tool. You can see a snapshot in the Figure 32. Figure 32. Snapshot of the FR program used for flash programming via Usart0... - Page 28 Figure 35. Electronic Components needed to protect the Debug I/F pin (R1 = 43 R, R2 = 10 k, D1 e.g. HZM6.2Z4MFA-E, D2 Schottky diode e.g. BAS40, Debug connector: SMA 50R connector for development target boards.) www.cypress.com Document No. 002-09375 Rev. *B...
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Page 29: Parallel Programming Interface
OCD. The debug security area is allocated at 30 bytes of built-in flash start address +4 to +33. (For further information please go to the Hardware Manual of this series) www.cypress.com Document No. 002-09375 Rev. *B... -
Page 30: Reset Behavior Of Io Port Pins
If some external bus pins should be used as GPIO than do not use any address or bus control lines as input, because these lines are driven as output high. Additional Information Information about CYPRESS Microcontrollers can be found on the following Internet page: http://www.cypress.com/cypress-microcontrollers Related documents for further information are listed in the table below: Table 10. - Page 31 Modified Figure 1: Principle schematic for minimal requirements and Figure 30: Principle schematic for serial programming via Usart0 (with USB cable) 6095053 NOFL 03/12/2018 Updated to Cypress template. Completing Sunset Review. Replaced “MB” with “CY” in all instances across the document. 6523608 NOFL 03/27/2019 Completing Sunset Review.
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Page 32: Worldwide Sales And Design Support
High-Risk Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a Cypress product as a Critical Component in a High-Risk Device.
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