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Cypress FM4 Series Peripheral Manual

Cypress FM4 Series Peripheral Manual

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32-Bit Microcontroller FM4 Family

Peripheral Manual

Doc. No. 002-04856 Rev. *E

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

www.cypress.com

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Page 1 32-Bit Microcontroller FM4 Family Peripheral Manual Doc. No. 002-04856 Rev. *E Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 www.cypress.com...
Page 2 A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.
Page 3 Note that the sample programs are subject to change without notice. Since they are offered as a way to demonstrate standard operations and usage, evaluate them sufficiently before running them on your system. Cypress assumes no responsibility for any damage that may occur as a result of using a sample program. Overall Organization of This Manual Peripheral Manual has 19 chapters and Appendixes as shown below.
Page 4 CHAPTER 17: Flash Memory CHAPTER 18: Unique ID Register CHAPTER 19: Programmable CRC Appendixes FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 5 Related Manuals The manuals related to this family are listed below. See the manual appropriate to the applicable conditions. The contents of these manuals are subject to change without notice. Contact us to check the latest versions available. Peripheral Manual FM4 Family Peripheral Manual (this manual) Called Peripheral Manual hereafter) FM4 Family Peripheral Manual Timer Part (002-04858)
Page 6 How to Use This Manual Finding a Function The following methods can be used to search for the explanation of a desired function in this manual: Search from the table of the contents The table of the contents lists the manual contents in the order of description. Search from the register The address where each register is located is not described in the text.
Page 7 The Target Products in This Manual In this manual, the products are classified into the following groups and are described follows. For the descriptions such as TYPE1-M4, see the relevant items of the target product in the list below. Table 1 TYPE1-M4 Product List Flash memory size Description in this manual...
Page 8 Table 3 TYPE3-M4 Product List Description Flash memory size No-Flash in this SRAM size 2 Mbytes 1.5 Mbytes 1 Mbytes manual 256 Kbytes S6E2CCAL S6E2CC9L S6E2CC8L S6E2CCAJ S6E2CC9J S6E2CC8J S6E2CCAH S6E2CC9H S6E2CC8H S6E2C5AL S6E2C59L S6E2C58L S6E2C5AJ S6E2C59J S6E2C58J S6E2C5AH S6E2C59H S6E2C58H S6E2C4AL S6E2C49L...
Page 9 Table 5 TYPE5-M4 Product List Flash memory size Description in this manual 1 Mbytes 512 Kbytes S6E2GM8J S6E2GM6J S6E2GM8H S6E2GM6H S6E2GK8J S6E2GK6J S6E2GK8H S6E2GK6H S6E2GH8J S6E2GH6J TYPE5-M4 S6E2GH8H S6E2GH6H S6E2G28J S6E2G26J S6E2G28H S6E2G26H S6E2G38J S6E2G36J S6E2G38H S6E2G36H Table 6 TYPE6-M4 Product List Flash memory size Description in this manual...
Page 10: Table Of Contents
Contents CHAPTER 1: System Overview ........................ 23 1. Bus Architecture ..........................24 1.1. Bus Block Diagram ......................26 1.2. Memory Architecture ......................27 1.3. Memory Map........................28 1.4. Peripheral Address Map ....................29 2. Cortex-M4F Architecture ........................ 32 2.1. Option configuration ......................35 3.
Page 11 Contents CHAPTER 2-2: Peripheral Clock Gating ....................81 1. Peripheral Clock Gating Overview ....................82 2. Peripheral Clock Gating Configuration................... 85 3. Peripheral Clock Gating Control ....................87 3.1. Peripheral Clock Control Procedures ................88 4. Peripheral Clock Gating Function Registers .................. 91 4.1.
Page 12 Contents CHAPTER 4: Resets ..........................159 1. Overview ............................160 2. Configuration ..........................161 3. Explanation of Operations ......................162 3.1. Reset Factors ......................... 163 3.2. Resetting Inside the Device .................... 166 3.2.1. Resets to Cortex-M4 ..................167 3.2.2. Resets to Peripheral Circuit ................168 3.3.
Page 13 Contents 9. Usage Precautions ........................241 CHAPTER 7-1: VBAT Domain Configuration ..................243 1. Configuration ..........................244 CHAPTER 7-2: VBAT Domain(A) ......................245 1. Overview of VBAT Domain ......................246 2. Configuration of VBAT Domain ....................248 2.1. Interfacing with Always-on Domain ................. 249 2.2.
Page 14 Contents 7.4. BOOST Register ......................341 7.5. EWKUP Register ......................342 7.6. HIBRST Register ......................343 7.7. VDET Register ........................ 344 7.8. Port Function Set Register (VBPFR) ................345 7.9. Pull-up Set Register (VBPCR) ..................347 7.10. Port I/O Direction Set Register (VBDDR) ..............348 7.11.
Page 15 Contents 4.31. IRQ091 Batch Read Register (IRQ091MON) ............... 422 4.32. IRQ092/093/094/095 Batch Read Register (IRQxxxMON) ........... 423 4.33. IRQ102 Batch Read Register (IRQ102MON) ............... 424 4.34. IRQ112 Batch Read Register (IRQ112MON) ............... 425 4.35. IRQ115 Batch Read Register (IRQ115MON) ............... 427 4.36.
Page 16 Contents 5.5. Transfer Source Address Register (DMACSA) ............... 500 5.6. Transfer Destination Address Register (DMACDA) ............501 6. Usage Precautions ........................502 CHAPTER 11: DSTC ..........................503 1. Overview of DSTC ........................504 2. DSTC Operations Overview and DSTC System Configuration ............ 505 2.1 Operations Overview of DSTC ..................
Page 17 Contents 5.14. Descriptor 1 (DES1) ....................... 576 5.15. Descriptor 2 (DES2) ....................... 578 5.16. Descriptor 3 (DES3) ....................... 578 5.17. Descriptor 4 (DES4) ....................... 579 5.18. Descriptor 5 (DES5) ....................... 579 5.19. Descriptor 6 (DES6) ....................... 579 CHAPTER 12: I/O Port ..........................581 1.
Page 18 Contents 4.40. Extended Pin Function Setting Register 35 (EPFR35) ..........732 4.41. Special Port Setting Register (SPSR) ................734 4.42. Port Pseudo Open Drain Setting Register (PZRx) ............736 4.43. Port Drive capability Select Register (PDSRx) ............. 738 5. Usage Precautions ........................739 CHAPTER 13: CRC (Cyclic Redundancy Check) ..................
Page 19 Contents 6.13. Write Error Address Register (WEAD) ................837 6.14. Error Status Clear Register (ESCLR) ................838 6.15. Access Mode Register (AMODE) ................. 839 7. Usage Precautions ........................840 CHAPTER 15: SD Card Interface ......................841 1. Overview of SD Card Interface ....................842 2.
Page 20 Contents 2.45. MMC Response Check Bit Register ................906 2.46. Card Detect Setting Register ..................907 3. MMC Boot Operation ........................908 3.1. Example of Controlling Alternative Boot Mode (Using ADMA)........910 4. MMC Wait IRQ ..........................912 4.1. Example of Controlling Wait IRQ ..................912 5.
Page 21 Contents 1.1.3. TYPE4-M4, TYPE5-M4, TYPE6-M4 Products ..........961 1.2. Unique ID........................962 1.3. ECC Capture Address ....................962 1.4. Clock/Reset ........................963 1.4.1. TYPE1-M4, TYPE2-M4 Products ..............963 1.4.2. TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products ......965 1.5. HW WDT ........................967 1.6.
Page 22 Contents 1.31. Smart Card Interface ....................1057 1.32. MFSI2S ........................1058 1.33. I2S Prescaler ......................1059 1.33.1. TYPE1-M4, TYPE2-M4, TYPE3-M4 Products ..........1059 1.33.2. TYPE4-M4 Product ..................1060 1.34. GDC_Prescaler ......................1061 1.35. EXT-Bus I/F ........................ 1062 1.35.1. TYPE1-M4 Product ..................1062 1.35.2.
Page 23: Chapter 1: System Overview
CHAPTER 1: System Overview This chapter explains the system overview. 1. Bus Architecture 2. Cortex-M4F Architecture 3. Mode FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 24: Bus Architecture
CHAPTER 1: System Overview Bus Architecture This section explains the bus architecture. For this family bus, AHB Bus Matrix circuit actualizes a multi-layer bus. Master and slave architectures are shown below:  Master − Cortex-M4F CPU(I-code Bus, D-code Bus, System Bus) −...
Page 25 CHAPTER 1: System Overview Notes: − Bit-band operation must not be performed to a register which RMW is prohibited. − When Read-Modify-Write process is performed over the software without bit-band operation, RMW signal is not output. Therefore, in this case, the flag value can be read in read operation although a register supports RMW process, and it is necessary not to be cleared an unrelated flag mistakenly in write operation.
Page 26: Bus Block Diagram
CHAPTER 1: System Overview Bus Block Diagram Figure 1-1 illustrates the bus block diagram. Figure 1-1 Bus Block Diagram SWJ-DP SRAM0 I-Code bus FLASH FLASH Cortex -M4F (Main) Core D-Code bus System bus SRAM1 ETM/HTM SRAM2 TPIU/ETB ROM table FLASH FLASH I/F (Work/Dual) Ethernet/SD-Card/GDC bus...
Page 27: Memory Architecture
CHAPTER 1: System Overview Memory Architecture This section shows the memory architecture. For this family, 4G-byte address space is available. Maximum 4M-byte FLASH memory, maximum 512K-byte SRAM0 area, maximum 256K-byte SRAM1 area, and maximum 256K-byte SRAM2 area are defined. Also, as an external bus area, 2G-byte area from 0x60000000 to 0xDFFFFFFF is defined. An external memory device can be connected to this area.
Page 28: Memory Map
CHAPTER 1: System Overview Memory Map Figure 1-2 illustrates the memory map. Figure 1-2 Memory Map Peripherals Area 0x41FF_FFFF Reserved 0x4008_1000 Progammable-CRC 0xFFFF_FFFF 0x4008_0000 CAN ch.2 (CAN-FD) 0x4007_0000 Reserved GPIO 0x4006_F000 SD-Card I/F 0xE010_0000 0x4006_E000 Cortex-M4F Private Reserved Peripherals Area 0x4006_D000 0xE000_0000 0x4006_C000...
Page 29: Peripheral Address Map
CHAPTER 1: System Overview Peripheral Address Map Table 1-1 shows the peripheral address map. Table 1-1 Peripheral Address Map Access other Register Start Address End Address Peripheral CHAPTER than CPU FLASH IF Register (Main)/ FLASH_IF/ 0x4000_0000 0x4000_0FFF Chapter17 Unique ID Register Unique ID Disabled Chapter18...
Page 30 CHAPTER 1: System Overview Access other Start Address End Address Peripheral Register Map CHAPTER than CPU 0x4002_F000 0x4002_FFFF Reserved 0x4003_0000 0x4003_0FFF External Interrupt EXTI Chapter 9 Interrupt Factor Check INT-Req 0x4003_1000 0x4003_1FFF Chapter 8 Register READ 0x4003_2000 0x4003_2FFF Reserved Chapter 2 in Analog 0x4003_3000 0x4003_3FFF D/A Converter...
Page 31 CHAPTER 1: System Overview Access other Start Address End Address Peripheral Register Map CHAPTER than CPU Chapter 7-1 0x4003_D000 0x4003_D0FF I2S Prescaler I2S Prescaler In Communication Macro Part APB2 Enabled 0x4003_D100 0x4003_DFFF GDC Prescaler *3 GDC Part Prescaler 0x4003_E000 0x4003_EFFF Reserved 0x4003_F000 0x4003_FFFF...
Page 32: Cortex-M4F Architecture
CHAPTER 1: System Overview Cortex-M4F Architecture This section explains the core architecture used in this family. Cortex-M4F core block architecture* used in this family is as follows: − Cortex-M4 Core − NVIC − − − − − − − − SWJ-DP −...
Page 33 CHAPTER 1: System Overview − SysTick Timer SysTick Timer is a system timer for OS task management integrated into NVIC. This family generates STCLK through dividing HCLK by eight and sets the values of SysTick Calibration Value Register (Address: 0xE000E01C) as shown below: bit31: NOREF = 0 bit30:...
Page 34 CHAPTER 1: System Overview ETM (Embedded Trace Macrocell) This family is equipped with a Cortex-M4 optional component ETM to support instruction trace. HTM (AMB AHB Trace Macrocell) This family is equipped with a Cortex-M4 optional component HTM to support AHB trace. SWJ-DP This family is equipped with SWJ-DP to support both serial wire protocol and JTAG protocol.
Page 35: Option Configuration
CHAPTER 1: System Overview Option Configuration Table 2-1 shows the option configuration of this family for Cortex-M4 core. For detail of feature, see Cortex-M4 Technical Reference Manual. Table 2-1 Option configuration TYPE1-M4 TYPE3-M4 Feature TYPE2-M4 TYPE4-M4 TYPE6-M4 TYPE5-M4 Memory Protection Unit (MPU) Present Present Present...
Page 36: Mode
CHAPTER 1: System Overview Mode This section explains the function of operating modes. In this family, the following operating modes can be used: − User Mode Internal ROM (Flash memory) Startup: CPU obtains a reset vector from Flash memory and starts operations.
Page 37: Chapter 2-1: Clock
CHAPTER 2-1: Clock This chapter explains the operating clock. 1. Clock Generation Unit Overview 2. Clock Generation Unit Configuration/Block Diagram 3. Clock Generation Unit Operations 4. Clock Setup Procedure Examples 5. List of Clock Generation Unit Registers 6. Clock Generation Unit Usage Precautions FM4 Peripheral Manual, Doc.
Page 38: Clock Generation Unit Overview
CHAPTER 2-1: Clock Clock Generation Unit Overview This section provides an overview of the clock generation unit. The clock generation unit generates various types of clocks used to operate the MCU. Source clock is the generic name for external and internal oscillation clocks of this MCU. The following five types of clocks are source clocks: ...
Page 39: Clock Generation Unit Configuration/Block Diagram
CHAPTER 2-1: Clock Clock Generation Unit Configuration/Block Diagram This section explains configuration of the clock generation unit. Source Clocks Source clock is the generic name for external and internal oscillation clocks of this MCU. The following five types of clocks are source clocks: ...
Page 40 CHAPTER 2-1: Clock Internal Bus Clocks The following signals are bus clocks generated internally.  Base clock (HCLK/FCLK) HCLK and FCLK are collectively called the base clock. Both HCLK and FCLK are supplied to the CPU. HCLK is a clock for macro connected to the AHB bus. The clock frequency can be set to between 1/1 and 1/16 frequency of the master clock.
Page 41 CHAPTER 2-1: Clock  USB/Ethernet clock This clock generates a clock at 48 MHz, used by USB communication. Also, it generates a clock for Ethernet. It sets the PLL oscillator for USB/Ethernet to generate a USB/Ethernet clock. This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, and deep standby stop mode.
Page 42 CHAPTER 2-1: Clock Block Diagram Figure 2-1, Figure 2-2 shows the block diagram of the clock generation unit. Figure 2-1 Block Diagram of Clock Generation Unit (TYPE1-M4, TYPE2-M4) USB clock CAN prescaler clock CLKPLL K frequency M frequency division Analog division N frequency division...
Page 43 CHAPTER 2-1: Clock Figure 2-2 Block Diagram of Clock Generation Unit (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4) USB clock / USB / Ethernet clock / USB / Ethernet clock I2S clock GDC clock CAN prescaler clock CLKPLL K frequency M frequency division Analog division N frequency...
Page 44: Clock Generation Unit Operations
CHAPTER 2-1: Clock Clock Generation Unit Operations This section explains the clock generation unit. Selecting the Clock Mode Definition of Clock Mode (Selecting the Master Clock) The MCU clock mode is defined by the source clock selected by the system clock mode control register. Five types of clock modes are provided: Main clock mode, sub clock mode, high-speed CR clock mode, low-speed CR clock mode, and main PLL clock mode.
Page 45: Internal Bus Clock Frequency Division Control
CHAPTER 2-1: Clock Internal Bus Clock Frequency Division Control This section explains the internal bus clock frequency division. Frequency division ratio from the base clock can be set independently for each internal bus clock. This function can set the operating frequency optimized for each circuit. The maximum frequency of the internal bus clock differs by product.
Page 46: Pll Clock Control
CHAPTER 2-1: Clock PLL Clock Control This section explains the PLL clock control. The PLL Clock Control Circuit is used to generate the main PLL clock from the main clock or high-speed CR clock. The PLL Oscillation Circuit can enable/disable operation (oscillation), select the input clock, set the stabilization wait time, and set the multiplication.
Page 47 CHAPTER 2-1: Clock Table 3-1 Example of PLL Multiplication Ratio Settings Input clock PLLin PLLout CLKPLL 4 MHz 4 MHz 320 MHz 80 MHz 4 MHz 4 MHz 240 MHz 120 MHz 4 MHz 4 MHz 320 MHz 160 MHz 4 MHz 4 MHz 400 MHz...
Page 48: Oscillation Stabilization Wait Time
CHAPTER 2-1: Clock Oscillation Stabilization Wait Time This section explains the oscillation stabilization wait time. An oscillation stabilization wait time is required if the source clock is not in a stable operating state. During the oscillation stabilization wait time, internal and external clocks stop the supply, only the internal time counter operates to wait until the stabilization wait time passes, a time value set in the Clock Stabilization Wait Time Register (CSW_TMR) or PLL Clock Oscillation Stabilization Wait Time Setup Register (PSW_TMR).
Page 49: Interrupt Factors
CHAPTER 2-1: Clock Interrupt Factors This section explains interrupt factors relevant to clocks. The clock generation unit has the following interrupt factors. Interrupt Factors The clock generation unit has the following four types of interrupt factors: − FCS (anomalous frequency detection) interrupt When the FCS (anomalous frequency detection) is enabled, and an anomalous frequency of the main clock is detected, an interrupt occurs.
Page 50: Clock Gear Function
CHAPTER 2-1: Clock Clock Gear Function The clock gear function is equipped in TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products. Due to drastic frequency difference, switching from the main clock to PLL clock or from PLL clock to the main clock cause huge fluctuation of power supply current. By utilizing the clock gear circuit, it can gradually shift the operating frequency from high-frequency to low-frequency or from low-frequency to high-frequency.
Page 51 CHAPTER 2-1: Clock Gear-up Procedure The gear-up procedure explains below. 1. The step loop configuration (PLLCG_CTL.PLLCGLP[7:0]), the step configuration (PLLCG_CTL.PLLCGSTP[1:0]) and the start step configuration (PLLCG_CTL.PLLCGSSN[6:0]) set the gear step you want to use. And the clock gear enable bit (PLLCG_CTL.PLLCGEN) is set to be enabled (1). 2.
Page 52: Clock Setup Procedure Examples
CHAPTER 2-1: Clock Clock Setup Procedure Examples This section explains procedure examples of setting up clocks. Setup Procedure Examples Figure 4-1 Example of Clock Setup Procedure (Power-on -> High-speed CR Run Mode -> Desired Clock Mode) (Except TYPE5-M4 products) Power-on * U s e high-speed CR clock for the PLL input clock.
Page 53 CHAPTER 2-1: Clock Figure 4-2 Example of Sub Oscillation Setup Procedure (Except TYPE5-M4 products) Start the sub oscillation enabling Access VBAT RTC LVD detection register (VDET). Release PONR of VBAT domain Set VBAT register (VBPFR.SPSR[1:0]=0b01) Set 32k oscillation Access VBAT register (CCB, CCS). Set 32k oscillation circuit and oscillation current value.
Page 54 CHAPTER 2-1: Clock − When 32k oscillation clock control linkage of VBAT register is disabled (WTOSCCNT.SOSCNTL=0) and 32k oscillation is disabled (WTOSCCNT.SOSCEX=1), the setting combination of sub clock mode oscillation of system clock mode control register enabled (SCM_CTL.SOSCE=1) and sub CSV function of CSV control register enabled (CSV_CTL.SVSVE=1) is prohibited.
Page 55 CHAPTER 2-1: Clock Figure 4-3 Example of Clock Setup Procedure (Power-on -> High-speed CR Run Mode -> Desired Clock Run Mode) (TYPE5-M4 products) Power-on * U se high-speed CR clock for the PLL input clock. Waiting for high-speed CR / low-speed CR oscillation stabilty Use the PLL clock? High-speed CR / low-speed CR oscillation stabilization...
Page 56 CHAPTER 2-1: Clock Figure 4-4 Example of Clock Setup Procedure (Low-speed CR Run Mode -> Desired Clock Run Mode) (Except TYPE5-M4 products) Low-speed CR run mode Y e s Select the sub run mode? Set sub clock oscillation enabled. See Figure 4-2 S e l e c t t he h i gh - s pee d CR r un m ode ? Complete waiting for...
Page 57 CHAPTER 2-1: Clock Figure 4-5 Example of Clock Setup Procedure (Low-speed CR Run Mode -> Desired Clock Run Mode) (TYPE5-M4 products) Low-speed CR run mode Y e s Enable the sub clock oscillation in the System Clock Select the sub run mode? Mode Control Register (SCM_CTL:SOCE=1).
Page 58: List Of Clock Generation Unit Registers
CHAPTER 2-1: Clock List of Clock Generation Unit Registers This section provides the register list of clock generation. Clock Generation Unit Register List Abbreviation Register Name Reference SCM_CTL System Clock Mode Control Register SCM_STR System Clock Mode Status Register BSC_PSR Base Clock Prescaler Register APBC0_PSR APB0 Prescaler Register...
Page 59: System Clock Mode Control Register (Scm_Ctl)
CHAPTER 2-1: Clock System Clock Mode Control Register (SCM_CTL) The SCM_CTL selects the master clock and enables/disables the clock oscillation. Register configuration Field RCS[2:0] PLLE SOSCE Reserved MOSCE Reserved Attribute Initial value Register functions [bit7:5] RCS[2:0]: Master clock switch control bits bit7 bit6 bit5...
Page 60 CHAPTER 2-1: Clock Notes: − This register is not initialized by software reset. − When you change the clock mode, you should set the enable bit to transition for desired clock oscillation. Then, you can change the clock switch control bits (SCM_CTL:RCS[2:0]). −...
Page 61: System Clock Mode Status Register (Scm_Str)
CHAPTER 2-1: Clock System Clock Mode Status Register (SCM_STR) The SCM_STR indicates a clock selected for the master clock and a waiting state for clock oscillation stability. Register configuration Field RCM[2:0] PLRDY SORDY Reserved MORDY Reserved Attribute Initial value Register functions [bit7:5] RCM[2:0]: Master clock selection bits bit7 bit6...
Page 62: Base Clock Prescaler Register (Bsc_Psr)
CHAPTER 2-1: Clock Base Clock Prescaler Register (BSC_PSR) The BSC_PSR sets the frequency division ratio of the base clock. Register configuration Field Reserved Attribute Initial value Register functions [bit7:3] Reserved: Reserved bits 0b00000 is read from these bits. Set these bits to 0b00000 when writing. [bit2:0] BSR: Base clock frequency division ratio setting bits bit2 bit1...
Page 63: Apb0 Prescaler Register (Apbc0_Psr)
CHAPTER 2-1: Clock APB0 Prescaler Register (APBC0_PSR) The APBC0_PSR sets the APB0 bus clock frequency division. Register configuration Field Reserved APBC0 Attribute Initial value Register functions [bit7:2] Reserved: Reserved bits 0b000000 is read from these bits. Set these bits to 0b000000 when writing. [bit1:0] APBC0: APB0 bus clock frequency division setting bits bit1 bit0...
Page 64: Apb1 Prescaler Register (Apbc1_Psr)
CHAPTER 2-1: Clock APB1 Prescaler Register (APBC1_PSR) The APBC1_PSR sets the APB1 bus clock frequency division. Register configuration Field APBC1EN Reserved APBC1RST Reserved APBC1 Attribute Initial value Register functions [bit7] APBC1EN: APB1 clock enable bit Description Disables PCLK1 output Enables PCLK1 output [Initial value] [bit6:5] Reserved: Reserved bits 0b00 is read from these bits.
Page 65: Apb2 Prescaler Register (Apbc2_Psr)
CHAPTER 2-1: Clock APB2 Prescaler Register (APBC2_PSR) The APBC2_PSR sets the APB2 bus clock frequency division. Register configuration Field APBC2EN Reserved APBC2RST Reserved APBC2 Attribute Initial value Register functions [bit7] APBC2EN: APB2 clock enable bit Description Disables PCLK2 output Enables PCLK2 output [Initial value] [bit6:5] Reserved: Reserved bits 0b00 is read from these bits.
Page 66: Software Watchdog Clock Prescaler Register (Swc_Psr)
CHAPTER 2-1: Clock Software Watchdog Clock Prescaler Register (SWC_PSR) The SWC_PSR sets the frequency division and enables the output of the software watchdog clock. Register configuration Field Reserved SWDS Attribute Initial value Register functions [bit7:2] Reserved: Reserved bits 0b000000 is read from these bits. Set these bits to 0b000000 when writing.
Page 67: Trace Clock Prescaler Register (Ttc_Psr)
CHAPTER 2-1: Clock Trace Clock Prescaler Register (TTC_PSR) The TTC_PSR sets the trace clock frequency division. Register configuration Field Reserved Attribute Initial value Register functions [bit7:2] Reserved: Reserved bits 0b000000 is read from this bit. Set these bits to 0b000000 when writing. [bit1:0] TTC: Trace clock divide ratio setting bits bit1 bit0...
Page 68: Clock Stabilization Wait Time Register (Csw_Tmr)
CHAPTER 2-1: Clock Clock Stabilization Wait Time Register (CSW_TMR) The CSW_TMR sets the stabilization wait time of the main/sub clock. Register configuration Field SOWT MOWT Attribute Initial value 0000 0000 Register functions [bit7:4] SOWT: Sub clock stabilization wait time setup bits bit7 bit6 bit5...
Page 69: Pll Clock Stabilization Wait Time Setup Register (Psw_Tmr)
CHAPTER 2-1: Clock PLL Clock Stabilization Wait Time Setup Register (PSW_TMR) 5.10 The PSW_TMR sets the main PLL clock stabilization wait time. Register configuration Field Reserved PINC Reserved POWT Attribute Initial value Register functions [bit7:5] Reserved: Reserved bits 0b000 is read from these bits. Set these bits to 0b000 when writing.
Page 70: Pll Control Register 1 (Pll_Ctl1)
CHAPTER 2-1: Clock PLL Control Register 1 (PLL_CTL1) 5.11 The PLL_CTL1 sets the PLL frequency division ratio. Register configuration Field PLLK PLLM Attribute Initial value 0000 0000 Register functions [bit7:4] PLLK: PLL input clock frequency division ratio setting bits bit 7:4 Description 0000 0001...
Page 71: Pll Control Register 2 (Pll_Ctl2)
CHAPTER 2-1: Clock PLL Control Register 2 (PLL_CTL2) 5.12 The PLL_CTL2 sets the PLL frequency division ratio. Register configuration Field Reserved PLLN Attribute Initial value 000000 Register functions [bit7:6] Reserved: Reserved bits 0b00 is read from these bits. Set these bits to 0b00 when writing. [bit5:0] PLLN: PLL feedback frequency division ratio setting bits bit5:0 Description...
Page 72: Debug Break Watchdog Timer Control Register (Dbwdt_Ctl)
CHAPTER 2-1: Clock Debug Break Watchdog Timer Control Register (DBWDT_CTL) 5.13 The DBWDT_CTL sets the watchdog timer count operation for debug mode tool break. Register configuration Field DPHWBE Reserved DPSWBE Reserved Attribute Initial value Register functions [bit7] DPHWBE: HW-WDG debug mode break bit Description HW-WDG stops counting at the tool break [Initial value] HW-WDG continues counting at the tool break...
Page 73: Interrupt Enable Register (Int_Enr)
CHAPTER 2-1: Clock Interrupt Enable Register (INT_ENR) 5.14 The INT_ENR enables/disables interrupts. Register configuration Field Reserved FCSE Reserved PCSE SCSE MCSE Attribute Initial value Register functions [bit7:6] Reserved: Reserved bits 0b00 is read from these bits. Set these bits to 0b00 when writing. [bit5] FCSE: Anomalous frequency detection interrupt enable bit Description Disables FCS interrupts...
Page 74: Interrupt Status Register (Int_Str)
CHAPTER 2-1: Clock Interrupt Status Register (INT_STR) 5.15 The INT_STR indicates the status of interrupts. Register configuration Field Reserved FCSI Reserved PCSI SCSI MCSI Attribute Initial value Register functions [bit7:6] Reserved: Reserved bits 0b00 is read from these bits. Set these bits to 0b00 when writing. [bit5] FCSI: Anomalous frequency detection interrupt status bit Description No FCS interrupt has been asserted.
Page 75: Interrupt Clear Register (Int_Clr)
CHAPTER 2-1: Clock Interrupt Clear Register (INT_CLR) 5.16 The INT_CLR clears interrupt factors. Register configuration Field Reserved FCSC Reserved PCSC SCSC MCSC Attribute Initial value Register functions [bit7:6] Reserved: Reserved bits 0b00 is read from these bits. Set these bits to 0b00 when writing. [bit5] FCSC: Anomalous frequency detection interrupt factor clear bit Description When 0 is...
Page 76 CHAPTER 2-1: Clock [bit0] MCSC: Main clock oscillation stabilization wait completion interrupt factor clear Description When 0 is The main clock oscillation stabilization wait completion interrupt factor is not affected by the written written value. When 1 is Clears the main clock oscillation stabilization wait completion interrupt factor. written When read The fixed value 0 is read.
Page 77: Pll Clock Gear Control Register (Pllcg_Ctl)
CHAPTER 2-1: Clock PLL Clock Gear Control Register (PLLCG_CTL) 5.17 The PLLCG_CTL sets the clock gear. This register is equipped in TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 products. Register configuration Field PLLCGLP Attribute Initial value 11111111 Field PLLCGSTP PLLCGSSN Attribute Initial value 000000 Field PLLCGSTS...
Page 78 CHAPTER 2-1: Clock [bit7:6] PLLCSTS : PLL clock gear start bits bit7 bit6 Description Not used clock gear [Initial value] Stop clock gear operation at minimum frequency when clock gear is enabled. Gear up operation Stop clock gear operation at maximum frequency when clock gear is enabled. Gear down operation [bit5:2] Reserved: Reserved bits 0b0000 is read from these bits.
Page 79: Clock Generation Unit Usage Precautions
CHAPTER 2-1: Clock Clock Generation Unit Usage Precautions This section explains the precautions for using the clock generation unit.  The oscillation stabilization wait time of main clock and sub clock oscillators Because the stabilization wait time of main clock/sub clock oscillator depends on the oscillator type (crystal, ceramic, etc.), the oscillation stabilization wait time suitable for the oscillator type must be selected.
Page 80 CHAPTER 2-1: Clock − If the standby mode is released by an interrupt, the device restarts in the clock mode that indicated by the RCS[2:0] bits in the SCM_CTL register. − If any reset occurs other than software resets, the high-speed CR clock (CLKHC) is set as a master clock.
Page 81: Chapter 2-2: Peripheral Clock Gating
CHAPTER 2-2: Clock Gating This chapter explains the functions of Peripheral Clock Gating. 1. Peripheral Clock Gating Overview 2. Peripheral Clock Gating Configuration 3. Peripheral Clock Gating Control 4. Peripheral Clock Gating Registers FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 82: Peripheral Clock Gating Overview
CHAPTER 2-2: Clock Gating Peripheral Clock Gating Overview This section shows an overview of the Peripheral Clock Gating which stops the operation clocks of peripheral functions individually. By using these functions, the system can reduce the current consumption of the total system with gating the operation clocks of peripheral functions not used. Overview of Peripheral Clock Gating ...
Page 83 CHAPTER 2-2: Clock Gating Overview of Connection with Clock and Reset Generation Units Figure 1-1 shows the connection between peripheral clock gating and clock generation unit or reset generation unit. The peripheral clock gating exists between peripheral function and clock generation unit or reset generation unit and gates clocks and controls resets in the unit of peripheral function.
Page 84 CHAPTER 2-2: Clock Gating Gating Units and their Initial Status of Peripheral Clock For gating units and their initial states of Peripheral Clock Gating, see Table 1-1. Table 1-1 Control Units and their Initial Status of Peripheral Clock Gating Peripheral Functions Clock Stop Units Initial States Remarks...
Page 85: Peripheral Clock Gating Configuration
CHAPTER 2-2: Clock Gating Peripheral Clock Gating Configuration This section explains the configuration of the Peripheral Clock Gating. Block Diagram Figure 2-1 shows the system configuration of Peripheral Clock Gating. Figure 2-1 Block Diagram of Peripheral Clock Gating Clock Generation Unit/ Reset Generation Unit HCLK Operation Peripheral Function(01)
Page 86 CHAPTER 2-2: Clock Gating Explanation on Block Diagram  Peripheral Clock Gating Control Unit The clock control or the reset control of each peripheral function is executed by changing the register setting value via the APB2 bus. Be sure to rewrite this register with setting APB2 clock enable bit (APBC2_PSR.
Page 87: Peripheral Clock Gating Control
CHAPTER 2-2: Clock Gating Peripheral Clock Gating Control This section explains the control of the peripheral clock gating. The register of the peripheral clock gating becomes an initial state by bus reset (PRESET2)*. Be sure to execute the clock control for necessary peripheral functions immediately after reset of the bus because the bus reset (PRESET2) is generated by all reset factors.
Page 88: Peripheral Clock Control Procedures
CHAPTER 2-2: Clock Gating Peripheral Clock Control Procedures This section explains the control procedures of supplying and stopping peripheral clocks. Clock Supply Procedures The settings of the bus clocks and the peripheral clocks are reset to the initial values immediately after the bus reset release.
Page 89 CHAPTER 2-2: Clock Gating Procedures of Gating and Resupplying Clocks Figure 3-2 explains the procedures of gating the clocks of peripheral functions and resupplying clocks to peripheral functions. Figure 3-2 Procedures of Gating Clocks of Peripheral Functions and Resupplying Clocks to Peripheral Functions Clock gating of Resupplying Clock to peripheral Function...
Page 90 CHAPTER 2-2: Clock Gating  Clock gating of peripheral functions 1. Gating setting of peripheral clocks For the peripheral clock control registers (CKEN0, CKEN1, and CKEN2), change the bit corresponding to the peripheral function for which the clock supply is to be stopped to 0. After gating the clock to the peripheral function to which the clock gating is instructed, the peripheral clock control registers (CKEN0, CKEN1, and CKEN2) updates the register value to the written value.
Page 91: Peripheral Clock Gating Function Registers
CHAPTER 2-2: Clock Gating Peripheral Clock Gating Function Registers This section explains each register function of the peripheral clock gating functions. Table 4-1 shows the list of registers of peripheral clock gating functions. Table 4-1 Registers of the Peripheral Clock Gating Functions Abbreviated Register Name Register Name Reference...
Page 92: Peripheral Function Clock Control Register 0 (Cken0)
CHAPTER 2-2: Clock Gating Peripheral Function Clock Control Register 0 (CKEN0) This section explains Peripheral Function Reset Clock Register 0 (CKEN0). Field Reserved GIOCK Reserved EXBCK Reserved DMACK Attribute Initial value Field Reserved ADCCK[3:0] Attribute Initial value 1111 Field MFSCK[15:8] Attribute Initial value 0xFF...
Page 93 CHAPTER 2-2: Clock Gating [bit26] EXBCK: Settings for operation clock supplying and gating of external bus interface function This bit controls the operation clock supplying and the gating to the external bus interface functions. When this bit is set to 1, the bus clock is supplied to the external bus interface function block, and the external bus interface function can be used.
Page 94 CHAPTER 2-2: Clock Gating [bit15:0] MFSCK[15:0]: Settings for operation clock supply and gating to multi-function serial interface These bits control the operation clock supply and gating to the multi-function serial interface. The correspondence between each bit and the channel is shown below: bit0 - MFSCK0: Multi-function serial interface channel 0 bit1 - MFSCK1: Multi-function serial interface channel 1 bit2 - MFSCK2: Multi-function serial interface channel 2...
Page 95: Peripheral Reset Control Register 0 (Mrst0)
CHAPTER 2-2: Clock Gating Peripheral Reset Control Register 0 (MRST0) This section explains the peripheral reset control register 0 (MRST0). Field Reserved EXBRST Reserved DMARST Attribute Initial value Field Reserved ADCRST[3:0] Attribute Initial value 0000 Field MFSRST[15:8] Attribute Initial value 0x00 Field MFSRST[7:0]...
Page 96 CHAPTER 2-2: Clock Gating [bit23:20] Reserved: Reserved bits Write0 to these bits. [bit19:16] ADCRST[3:0]: Reset control of A/D converter These bits control the reset of each unit of the A/D converter. The correspondence between each bit and A/D converter unit is shown below: bit16 - ADCRST0: A/D converter unit 0 bit17 - ADCRST1: A/D converter unit 1 bit18 - ADCRST2: A/D converter unit 2...
Page 97: Peripheral Clock Control Register 1 (Cken1)
CHAPTER 2-2: Clock Gating Peripheral Clock Control Register 1 (CKEN1) This section explains the peripheral clock control register 1 (CKEN1). Field Reserved Attribute Initial value Field Reserved QDUCK[3:0] Attribute Initial value 1111 Field Reserved MFTCK[3:0] Attribute Initial value 1111 Field Reserved BTMCK[3:0] Attribute...
Page 98 CHAPTER 2-2: Clock Gating [bit11:8] MFTCK[3:0]: Settings for operation clock supply and gating of multi-function timer and PPG These bits control the operation clock supply and gating to the multi-function timer and PPG. The correspondence among each bit, the multi-function timer unit, and the PPG channel is shown below. bit8 - MFTCK0: Multi-function timer unit 0 - PPG channel 0 to channel 7 bit9 - MFTCK1: Multi-function timer unit 1 - PPG channel 8 to channel 15 bit10 - MFTCK2: Multi-function timer unit 2 - PPG channel 16 to channel 23...
Page 99: Peripheral Function Reset Control Register 1 (Mrst1)
CHAPTER 2-2: Clock Gating Peripheral Function Reset Control Register 1 (MRST1) This section explains the peripheral function reset control register 1(MRST1). Field Reserved Attribute Initial value Field Reserved QDURST[3:0] Attribute Initial value 0000 Field Reserved MFTRST[3:0] Attribute Initial value 0000 Field Reserved BTMRST[3:0]...
Page 100 CHAPTER 2-2: Clock Gating [bit11:8] MFTRST[3:0]: Control of multi-function timer and PPG reset control These bits control multi-function timer reset of each unit and PPG reset of every four channels. The correspondence among each bit, quad counter unit, and the PPG channel is shown below. bit8 - MFTRST0: Multi-function timer unit 0 - PPG channel 0, 2, 4, 6 bit9 - MFTRST1: Multi-function timer unit 1 - PPG channel 8, 10, 12, 14 bit10 - MFTRST2: Multi-function timer unit 2 - PPG channel 16, 18, 20, 22...
Page 101: Peripheral Clock Control Register 2 (Cken2)
CHAPTER 2-2: Clock Gating Peripheral Clock Control Register 2 (CKEN2) This section explains the peripheral clock control register 2(CKEN2). Field Reserved QSPICK Reserved CECCK[1:0] Attribute Initial value Field Reserved PCRCCK Reserved I2SCK[1:0] Attribute Initial value Field IISCCK[1:0] ICCCK[1:0] Reserved SDCCK Attribute Initial value Field...
Page 102 CHAPTER 2-2: Clock Gating [bit25:24] CECCK[1:0]: Settings for operation clock supply and gating of HDMI-CEC/Remote Control Reception These bits control the operation clock supply and gating to HDMI-CEC/Remote Control Reception. The correspondence between each bit and the HDMI-CEC/Remote Control Reception channel is shown below.
Page 103 CHAPTER 2-2: Clock Gating [bit17:16] I2SCK[1:0]: Settings for operation clock supply and gating of I S Interface These bits control the operation clock supply and gating to I S Interface. The correspondence between each bit and the I S Interface channel is shown below. bit16 –...
Page 104 CHAPTER 2-2: Clock Gating [bit11:9] Reserved: Reserved bits Write 0 to these bits. [bit8] SDCCK: Settings for operation clock supply and gating to SD card interface This bit controls the operation clock supply and gating to the SD card interface function. When this bit is set to 1, the bus clock is supplied to the SD card interface unit to use the SD card interface function.
Page 105: Peripheral Function Reset Control Reset 2 (Mrst2)
CHAPTER 2-2: Clock Gating Peripheral Function Reset Control Reset 2 (MRST2) This section explains the peripheral function reset control register 2 (MRST2). Field Reserved QSPIRST Reserved CECRST[1:0] Attribute Initial value Field Reserved PCRCRST Reserved I2SRST[1:0] Attribute Initial value Field IISCRST[1:0] ICCRST[1:0] Reserved SDCRST...
Page 106 CHAPTER 2-2: Clock Gating [bit25:24] CECRST[1:0]: Reset control of HDMI-CEC/Remote Control Reception These bits control the reset of each channel of HDMI-CEC/Remote Control Reception. The correspondence between each bit and the HDMI-CEC/Remote Control Reception channel is shown below. bit24 - CECRST0: HDMI-CEC/Remote Control Reception channel 0 bit25 - CECRST1: HDMI-CEC/Remote Control Reception channel 1 If the relevant bit is set to 1, the channel of corresponding HDMI-CEC/Remote Control Reception becomes a reset state, the HDMI-CEC/Remote Control Reception operation stops, and the register...
Page 107 CHAPTER 2-2: Clock Gating [bit15:14] IISCRST[1:0]: Reset control of MFS I S Interface These bits control the reset of each channel of MFS I S Interface. The correspondence between each bit and the MFS I S Interface channel is shown below. bit14 –...
Page 108 CHAPTER 2-2: Clock Gating [bit6:4] CANRST[2:0]: Reset control of CAN controller These bits control the reset of each CAN controller’s channel unit. The correspondence between each bit and the CAN controller channel is shown below. bit4 – CANRST0: CAN controller channel 0 bit5 –...
Page 109: Peripheral Clock Gating Function Usage Precautions
CHAPTER 2-2: Clock Gating Peripheral Clock Gating Function Usage Precautions This section explains the precautions for using peripheral clock gating functions by peripheral function. Overview  Control of a peripheral function to which a clock supply is stopped The register access to a peripheral function to which a clock supply is stopped, both read and write, is not guaranteed.
Page 110 CHAPTER 2-2: Clock Gating Base Timer  Clock setting unit of base timer The peripheral clock control of the base timer is executed in the unit of four channels described in Table 5-1. Table 5-1 Correspondence between Peripheral Clock Gating Setting and Base Timer Channels Setting Bit of Peripheral Clock Control Target Channels Register (CKEN1)
Page 111 CHAPTER 2-2: Clock Gating A/D Converter  A/D Timer Trigger Selection When the base timer is used as a startup trigger of the A/D converter, set the operation clock of the selected base timer channel to the supply side. GPIO ...
Page 112 CHAPTER 2-2: Clock Gating FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 113: Chapter 2-3: High-Speed Cr Trimming
CHAPTER 2-3: High-Speed CR Trimming This chapter explains the High-Speed CR Trimming Function. 1. High-Speed CR Trimming Function Overview 2. High-Speed CR Trimming Function Configuration and Block Diagram 3. High-Speed CR Trimming Function Operation 4. High-Speed CR Trimming Function Setup Procedure Example 5.
Page 114: High-Speed Cr Trimming Function Overview
CHAPTER 2-3: High-Speed CR Trimming High-Speed CR Trimming Function Overview This section explains frequency trimming function of the high-speed CR oscillator. The high-speed CR oscillators used for this device have fluctuation range in frequency accuracy due to process variation. The fluctuation range of frequency accuracy due to process variation and temperature change can be reduced by configuring the trimming function.
Page 115: High-Speed Cr Trimming Function Configuration And Block Diagram
CHAPTER 2-3: High-Speed CR Trimming High-Speed CR Trimming Function Configuration and Block Diagram This section explains the configuration and block diagram of high-speed CR oscillator frequency trimming function. Figure 2-1 shows the block diagram of high-speed CR frequency trimming function. Figure 2-1 Block Diagram of the High-speed CR Oscillator Timing Circuit APB-Bus High-speed CR...
Page 116: High-Speed Cr Trimming Function Operation
CHAPTER 2-3: High-Speed CR Trimming High-Speed CR Trimming Function Operation This section explains operation conducted by frequency trimming function of the high-speed CR oscillator. Operation of High-speed CR Oscillation Frequency Trimming Function  Frequency trimming setup The setup process writes a trimming data value to the High-speed CR oscillation Frequency Trimming Register (MCR_FTRM) to correct the misalignment of high-speed CR clock accuracy caused by process variation.
Page 117: High-Speed Cr Trimming Function Setup Procedure Example
CHAPTER 2-3: High-Speed CR Trimming High-Speed CR Trimming Function Setup Procedure Example This section provides an example of setting up frequency trimming function of the high-speed CR oscillator. Frequency Trimming Setup Take the steps shown in Figure 4-1 to set up frequency trimming. 1.
Page 118 CHAPTER 2-3: High-Speed CR Trimming Frequency Trimming Data Acquisition Example When acquiring the data from the CR trimming area in the flash memory; Read the CR trimming area in the flash memory and get the data. Write the acquired value to TRD bit of the High-speed CR oscillation Frequency Trimming Setup Register (MCR_FTRM).
Page 119 CHAPTER 2-3: High-Speed CR Trimming Figure 4-2 Method to Trim High-speed CR Clock T[sec] Tmax_coarse Tmax_fine Ttgt Tmin_fine Tmin_coarse Xtrmmin_coarse Xtrm Xtrmmax_coarse Xtrmmin_fine Xtrmmax_fine Note: − For information about how to measure Tmin_coarse/fine and Tmax_coarse/fine, see " Example of Trimming Data Acquisition Using Base Timer". Example of Trimming Data Acquisition Using Base Timer Figure 4-3 shows the time chart of high-speed CR oscillation and the trimming process.
Page 120 CHAPTER 2-3: High-Speed CR Trimming Example: When PCLK = 40 MHz (25 ns), frequency division ratio = 1/8, and TIMER1 = 100, Tmax = (100 × 25 ns) / 8 = 312.5 ns Note: − The base timer used for trimming is ch.0. PCLK in Figure 4-3 is an APB1 bus clock.
Page 121 CHAPTER 2-3: High-Speed CR Trimming Frequency Trimming Procedure Example Figure 4-4 shows a trimming procedure example of high-speed CR oscillation. Figure 4-4 Trimming Procedure Example of High-speed CR Oscillation Start Set the master clock as the main oscillation clock by the SCM_CTL register (RCS[2:0]:SCM_CTL = 001) Unlock the MCR_FTRM register Write 0x1ACC_E554 to the MCR_RLR register...
Page 122 CHAPTER 2-3: High-Speed CR Trimming Xtrm Calculation Procedure Example Figure 4-5 shows an Xtrm calculation procedure example. Perform frequency trimming in the two stages of coarse adjustment and fine adjustment. Figure 4-5 Xtrm Calculation Procedure Example Start Calculate the fine adjustment Calculate the coarse adjustment (TRD[4:0]) bit (Xtrm_fine) (TRD[9:5]) bit (Xtrm_coarse)
Page 123 CHAPTER 2-3: High-Speed CR Trimming Procedure Example of Using CR Trimming Area Storage Data inside Flash Memory Figure 4-6 shows a procedure example of reading trimming data stored in the CR trimming area inside the flash memory and setting it in the High-speed CR oscillation Frequency Trimming Register. Figure 4-6 Procedure Example of Using CR Trimming Area Storage Data Start Unlock the register...
Page 124: High-Speed Cr Trimming Function Register List
CHAPTER 2-3: High-Speed CR Trimming High-Speed CR Trimming Function Register List The following lists and explains registers used for frequency trimming function of the high-speed CR oscillator. Table 5-1 lists the registers. Table 5-1 Register List Abbreviation Register Name Reference MCR_PSR High-speed CR oscillation Frequency Division Setup Register MCR_FTRM...
Page 125: High-Speed Cr Oscillation Frequency Division Setup Register (Mcr_Psr)
CHAPTER 2-3: High-Speed CR Trimming High-speed CR Oscillation Frequency Division Setup Register (MCR_PSR) The MCR_PSR register sets the frequency division ratio of high-speed CR oscillation. A divided clock can be input in base timer. Register configuration Field Reserved Attribute Initial value Register functions [bit7:3] Reserved : Reserved bits "0b00000"...
Page 126: High-Speed Cr Oscillation Frequency Trimming Register (Mcr_Ftrm)
CHAPTER 2-3: High-Speed CR Trimming High-speed CR Oscillation Frequency Trimming Register (MCR_FTRM) The MCR_FTRM register sets the frequency trimming value. Register configuration Field Reserved Attribute Initial value Field Reserved TRD[9:0] Attribute Initial value 0111101111 Register functions [bit31:10] Reserved : Reserved bits "0"...
Page 127: High-Speed Cr Oscillation Temperature Trimming Setup Register (Mcr_Ttrm)
CHAPTER 2-3: High-Speed CR Trimming High-speed CR Oscillation Temperature Trimming Setup Register (MCR_TTRM) The MCR_TTRM register sets the temperature trimming value. Register Configuration Field Reserved Attribute Initial value Field Reserved TRT[4:0] Attribute Initial value 10000 Register functions [bit31:5] Reserved : Reserved bits "0"...
Page 128: High-Speed Cr Oscillation Register Write-Protect Register (Mcr_Rlr)
CHAPTER 2-3: High-Speed CR Trimming High-Speed CR Oscillation Register Write-Protect Register (MCR_RLR) The MCR_RLR register controls the write-protect state of the frequency trimming register (MCR_FTRM)/high-speed CR oscillation temperature trimming register (MCR_TTRM). Register configuration Field TRMLCK[31:16] Attribute Initial value 0x0000 Field TRMLCK[15:0] Attribute Initial value...
Page 129: High-Speed Cr Trimming Function Usage Precautions
CHAPTER 2-3: High-Speed CR Trimming High-Speed CR Trimming Function Usage Precautions This section explains the precautions for using the high-speed CR trimming function.  Low-speed CR oscillator This trimming function is only enabled for the high-speed CR oscillator. It cannot apply to the low-speed CR oscillator. ...
Page 130 CHAPTER 2-3: High-Speed CR Trimming FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 131: Chapter 2-4: Low-Speed Cr Prescaler
CHAPTER 2-4: Low-Speed CR Prescaler This chapter shows the functions and operation of low-speed CR Prescaler. 1. Low-speed CR Prescaler Overview 2. Low-speed CR Prescaler Configuration 3. Low-speed CR Prescaler Operation and Setup Procedure Example 4. Low-speed CR Prescaler Register FM4 Peripheral Manual, Doc.
Page 132: Low-Speed Cr Prescaler Overview
CHAPTER 2-4: Low-Speed CR Prescaler Low-speed CR Prescaler Overview This section shows the overview of low-speed CR prescaler. Low-speed CR Prescaler By setting the low-speed CR prescaler load register(LCR_PRSLD), the low-speed CR prescaler divides low-speed CR and generates low-speed CR clock(CLKLC). This macro can correct the accuracy of low-speed CR.
Page 133: Low-Speed Cr Prescaler Configuration
CHAPTER 2-4: Low-Speed CR Prescaler Low-speed CR Prescaler Configuration This section shows the block diagram of low-speed CR prescaler. Block Diagram of Low-speed CR Prescaler For the block diagram of low-speed CR prescaler, see Figure 2-1. Figure 2-1 Block Diagram of Low-speed CR Prescaler Low-speed CR prescaler Reload register (LCR_PRSLD) bit5 bit4 bit3 bit2 bit1 bit0...
Page 134: Low-Speed Cr Prescaler Operation And Setup Procedure Example
CHAPTER 2-4: Low-Speed CR Prescaler Low-speed CR Prescaler Operation and Setup Procedure Example This section explains the operation of Low-speed CR Prescaler. This section also shows the example of setup procedures. Setup Procedures of Low-speed CR Prescaler The Low-speed CR is asynchronous with the peripheral clock (PCLK). For writing to the Low-speed CR Prescaler Reload Register, the peripheral clock is used.
Page 135 CHAPTER 2-4: Low-Speed CR Prescaler Operation of Low-speed CR Prescaler For the operation of the Low-speed CR Prescaler, see Figure 3-1. Figure 3-1 Low-speed CR Prescaler Operation Peripheral Clock (PCLK) Low-speed CR Prescaler Reload Register Low-speed CR Low-speed CR Reload Counter Underflow CLKLC (1) Sets the Low-speed CR Prescaler Load Register (LCR_PRSLD) in synchronization with the peripheral...
Page 136 CHAPTER 2-4: Low-Speed CR Prescaler Low-speed CR Correction Example For the correction example of the Low-speed C, see Figure 3-2. Figure 3-2 Low-speed CR Correction Example Set the watch counter prescaler. Set “Clock Source” to Low-speed CR. (SEL_IN[1:0] = “11”) Set the output clock to the value from 2^4 to 2^1.
Page 137: Low-Speed Cr Prescaler Register
CHAPTER 2-4: Low-Speed CR Prescaler Low-speed CR Prescaler Register This section shows the list of the Low-speed CR Prescaler Register. Low-speed CR Prescaler Register Table 4-1 List of Low-speed CR Prescaler Register Abbreviation Register Name Reference LCR_PRSLD Low-speed CR Prescaler Control Register FM4 Peripheral Manual, Doc.
Page 138: Low-Speed Cr Prescaler Control Register (Lcr_Prsld)
CHAPTER 2-4: Low-Speed CR Prescaler Low-speed CR Prescaler Control Register (LCR_PRSLD) The Low-speed CR Prescaler Control Register is used to set the division ratio of low-speed CR. Field Reserved LCR_PRSLD[5:0] Attribute Initial Value 000000 [bit7:6] Reserved: Reserved bits Always 0 is read. They have no effect in write mode.
Page 139: Chapter 3: Clock Supervisor
CHAPTER 3: Clock Supervisor This chapter explains the clock supervisor functions. 1. Overview 2. Configurations and Block Diagrams 3. Explanation of Operations 4. Setup Procedure Examples 5. Operation Examples 6. Registers 7. Usage Precautions FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 140: Overview
CHAPTER 3: Clock Supervisor Overview This section provides an overview of the clock supervisor functions. The clock supervisor includes the following two types of functions.  Clock failure detection (CSV: Clock failure detection by clock Supervisor) The clock failure detection monitors the main and sub clocks. If a rising edge of the monitored clock is not detected within the specified period, this function determines that the oscillator has failed, and outputs a system reset request.
Page 141: Configurations And Block Diagrams
CHAPTER 3: Clock Supervisor Configurations and Block Diagrams This section explains the block diagram of the clock supervisor functions. Clock Failure Detection Figure 2-1 shows the block diagram of the clock failure detection. Figure 2-1 Clock Failure Detection Block Diagram Main Clock Main clock High-speed CR...
Page 142 CHAPTER 3: Clock Supervisor Anomalous Frequency Detection Figure 2-2 shows the block diagram of the anomalous frequency detection. Figure 2-2 Anomalous Frequency Detection Block Diagram Main Clock Edge Frequency divider detection counter High-speed CR Control circuit / FCS_RESET register and window registers FCS_INT The anomalous frequency detection consists of the following three types of blocks.
Page 143: Explanation Of Operations
CHAPTER 3: Clock Supervisor Explanation of Operations This section explains the operations of the clock supervisor functions. Clock Failure Detection Function The clock failure detection function monitors the main and sub clocks. If a rising edge of the monitored clock is not detected within the specified period, this function determines that the oscillator has failed, and outputs a system reset request.
Page 144: Setup Procedure Examples
CHAPTER 3: Clock Supervisor Setup Procedure Examples This section explains examples of setting up the clock supervisor functions. Example of Clock Failure Detection Function Setup Procedure Setup Start Enable main and sub clock oscillators Oscillation stabilization wait time of main and sub clocks end Clock failure detection operation of main and sub clocks starts Failure Detected?
Page 145 CHAPTER 3: Clock Supervisor Example of Anomalous Frequency Detection Function Setup Procedure Setup Start Access FCSWH_CTL Is the count value out of the window? Set upper frequency window Access FCSWL_CTL Set lower frequency window Is the interrupt flag set? Access CSV_CTL Set FCD (Count Edge setting) FCS interrupt occurs Access CSV_CTL...
Page 146: Operation Examples
CHAPTER 3: Clock Supervisor Operation Examples This section explains examples of clock supervisor operations. Clock Failure Detection Figure 5-1 provides an example of clock failure detection operation. Figure 5-1 Example of Clock Failure Detection Operation Main clock High-speed CR clock Main clock is missing 32 x CR clocks CSV reset...
Page 147 CHAPTER 3: Clock Supervisor Anomalous Frequency Detection Figure 5-3 provides an example of anomalous frequency detection function operation. Figure 5-3 Example of Anomalous Frequency Detection Function Operation Main clock Divided clock of High-speed CR Count-up cycle 1. This function detects rising edges of the divided clock of high-speed CR. 2.
Page 148 CHAPTER 3: Clock Supervisor Example of Anomalous Frequency Detection Function Window Setting The anomalous frequency detection counts up between edges of the divided clock of high-speed CR. The measurement interval is also affected by the accuracy of CR. When you configure the window register value, therefore, the CR accuracy must be considered for the value.
Page 149 CHAPTER 3: Clock Supervisor Thus, you can recognize that a main clock frequency out of the 3.4 MHz to 4.6 MHz range is anomalous. Table 5-1 provides an example of the window settings. Table 5-1 Example of Window Settings Divided Clock of High-speed Count Value including Lower Limit of...
Page 150: Registers
CHAPTER 3: Clock Supervisor Registers This section explains the register list of the clock supervisor functions. Register List Table 6-1 shows the register list. Table 6-1 Register List Abbreviation Register name Reference CSV_CTL CSV control register CSV_STR CSV status register FCSWH_CTL Frequency detection window setting register (Upper) FCSWL_CTL...
Page 151: Csv Control Register (Csv_Ctl)
CHAPTER 3: Clock Supervisor CSV control register (CSV_CTL) The CSV_CTL register configures the control of CSV function. Register configuration Field Reserved Reserved FCSRE FCSDE Attribute Initial value Field Reserved SCSVE MCSVE Attribute Initial value Register functions [bit15] Reserved: Reserved bit "0"...
Page 152 CHAPTER 3: Clock Supervisor [bit7:2] Reserved: Reserved bits "0b000000" is read from these bits. Set these bits to "0b000000" when writing. [bit1] SCSVE: Sub CSV function enable bit Description When 0 is written The sub CSV function is disabled When 1 is written The sub CSV function is enabled.
Page 153: Csv Status Register (Csv_Str)
CHAPTER 3: Clock Supervisor CSV status register (CSV_STR) The CSV_STR register indicates the status of CSV function. Register configuration Field Reserved SCMF MCMF Attribute Initial value Register functions [bit7:2] Reserved: Reserved bits "0b000000" is read from these bits. Set these bits to "0b000000" when writing. [bit1] SCMF : Sub clock failure detection flag Description When written...
Page 154: Frequency Detection Window Setting Register (Upper) (Fcswh_Ctl)
CHAPTER 3: Clock Supervisor Frequency detection window setting register (Upper) (FCSWH_CTL) The FCSWH_CTL register configures the frequency detection window setting register (Upper). Register configuration Field Attribute Initial value 0xFFFF Register functions [bit15:0] FWH: Frequency detection window setting bits (Upper) bit15:0 Description When written Any value can be written to these bits.
Page 155: Frequency Detection Window Setting Register (Lower) (Fcswl_Ctl)
CHAPTER 3: Clock Supervisor Frequency detection window setting register (Lower) (FCSWL_CTL) The FCSWL_CTL register configures the frequency detection window setting register (Lower). Register configuration Field Attribute Initial value 0x0000 Register functions [bit15:0] FWL: Frequency detection window setting bits (Lower) bit15:0 Description When written Any value can be written to these bits.
Page 156: Frequency Detection Counter Register (Fcswd_Ctl)
CHAPTER 3: Clock Supervisor Frequency detection counter register (FCSWD_CTL) The FCSWD_CTL register indicates the counter value of frequency detection using the main clock. Register configuration Field Attribute Initial value 0x0000 Register functions [bit15:0] FWD: Frequency detection count data bit15:0 Description When written No effect on operation When read...
Page 157: Usage Precautions
CHAPTER 3: Clock Supervisor Usage Precautions  This section explains the precautions for using the clock supervisor functions. For details on enabling and clearing the frequency detection interrupt sources, see Chapter "Clock".  For details on clock failure detection and anomalous frequency detection reset sources, see Chapter "Resets".
Page 158 CHAPTER 3: Clock Supervisor FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 159: Chapter 4: Resets
CHAPTER 4: Resets This chapter explains the function and operation of the resets. 1. Overview 2. Configuration 3. Explanation of Operations 4. Register FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 160: Overview
CHAPTER 4: Resets Overview This family has the following reset factors and issues a reset to initialize a device upon accepting a reset factor.  Power-on reset  INITX pin input  External power supply/low-voltage detection reset  Software watchdog reset ...
Page 161: Configuration
CHAPTER 4: Resets Configuration This section explains configuration of reset circuit. Block Diagram of Resets Figure 2-1 Block Diagram of Resets Cortex-M4F SYSRESETREQ SYSRESETREQ SYSRESETn SYSRESETn SQ-WDG reset SW-WDG HRESET PRESET0 PRESET1 HW-WDG reset HW-WDG PRESET2 Clock failure detection reset Reset Anomalous frequency detection reset generator...
Page 162: Explanation Of Operations
CHAPTER 4: Resets Explanation of Operations This section explains the operations of the resets of this family. 3.1. Reset Factors 3.2. Resetting Inside the Device 3.3. Reset Sequence 3.4. Operations after Resets are Cleared FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 163: Reset Factors
CHAPTER 4: Resets Reset Factors This section explains reset factors. Power-On Reset (PONR) A reset that is generated at power-up. Generated by This signal is generated by detecting a rising edge of the power supply. Cleared by This signal is automatically cleared after issuing a reset. Initialization Initializes all register settings and hardware.
Page 164 CHAPTER 4: Resets Hardware Watchdog Reset (HWDGR) A reset that is input from the hardware watchdog timer. Generated by This signal is generated when the hardware watchdog timer underflows. Cleared by This signal is automatically cleared after issuing a reset. Initializes all register settings and hardware except the debug circuit, deep standby control block, and RTC (some registers).
Page 165 CHAPTER 4: Resets Software Reset (SRST) A reset that is generated when an access to the reset control register occurs. This signal is generated by a write to the Cortex-M4 internal reset control register Generated by (SYSRESETREQ bit). Cleared by This signal is automatically cleared after issuing a reset.
Page 166: Resetting Inside The Device
CHAPTER 4: Resets Resetting Inside the Device This section explains the internal reset signals of this device. Resets that are internally connected to the device are divided into resets that are input to the Cortex-M4 core and resets that are input to peripheral circuits. 3.2.1.
Page 167: Resets To Cortex-M4
CHAPTER 4: Resets Resets to Cortex-M4 3.2.1 The device has three reset inputs to the Cortex-M4: PORESETn, SYSRESETn, and nTRST. The following provides reset factors for these three reset inputs. Power-on Reset PORESETn − Power-on reset (PONR) Reset factors − Low-voltage detection reset (LVDH) −...
Page 168: Resets To Peripheral Circuit
CHAPTER 4: Resets Resets to Peripheral Circuit 3.2.2 The bus resets (HRESET, PRESET0, PRESET1, and PRESET2) that are input to the peripheral circuit are basically generated by all reset factors. Resetting of PRESET1 and PRESET2 can be controlled by register settings. The following provides reset factors for the bus resets.
Page 169: Reset Sequence
CHAPTER 4: Resets Reset Sequence This family initiates the program and hardware operations starting with the initial state when a reset factor is cleared. This family of operations starting with the reset and ending with the initiation of the operations is called a reset sequence.
Page 170 CHAPTER 4: Resets 1. Capturing reset factors Reset factors are captured and retained until a reset is issued to the device. 2. Issuing resets When a reset is ready to be issued, a device internal reset is issued. 3. Clearing resets When a reset factor is cleared, a device internal reset is extended for the amount of time required to clear the reset (for example, a wait time required until oscillation of a high-speed CR has become stable).
Page 171: Operations After Resets Are Cleared
CHAPTER 4: Resets Operations after Resets are Cleared PONR, LVDH, INITX, HWDGR, SWDGR, CSVR, FCSR, DSTR Figure 3-1 provides an example of the operation waveform after a cause of INITX pin input reset has been cleared. Figure 3-1 Operation Waveform after INITX Pin Input Reset has been Cleared INITX Clear cause Oscillation of...
Page 172: Register
CHAPTER 4: Resets Register This section explains the configuration and functions of the register. Register List Abbreviation Register Name Reference RST_STR Reset factor register FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 173: Reset Factor Register (Rst_Str: Reset Status Register)
CHAPTER 4: Resets Reset Factor Register (RST_STR: ReSeT STatus Register) The Reset Factor Register (RST_STR) shows the factors of resets that have just occurred. All bits of the RST_STR are initialized by a power-on reset, a low-voltage detection reset or a deep standby reset. It is not initialized by any other reset.
Page 174 CHAPTER 4: Resets Indicates a reset from the hardware watchdog timer. If the timer underflows, a reset is issued and HWDT is enabled (HWDT = 1). Description A hardware watchdog reset has not been issued. A hardware watchdog reset has been issued. [bit4] SWDT: Software watchdog reset flag Indicates a reset from the software watchdog timer.
Page 175: Chapter 5: Low-Voltage Detection
CHAPTER 5: Low-voltage Detection This chapter explains the functions and operations of the Low-voltage Detection Circuit. 1. Overview 2. Configuration 3. Explanation of Operations 4. Setup Procedure Examples 5. Registers FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 176: Overview
CHAPTER 5: Low-voltage Detection Overview The Low-voltage Detection Circuit monitors the power supply voltage, and generates reset and interrupt signals when the power supply voltage falls below the detection voltage. Overview of Low-voltage Detection Circuit  Operations of Low-voltage Reset Circuit −...
Page 177: Configuration
CHAPTER 5: Low-voltage Detection Configuration This section shows the block diagram of the Low-voltage Detection Circuit. Block Diagram of Low-voltage Detection Circuit Low-voltage Detection V C C Voltage Protection Register Register Lock Low-voltage Detection Voltage Control Register Reset signal Vref VS S VS S LVDIE...
Page 178: Explanation Of Operations
CHAPTER 5: Low-voltage Detection Explanation of Operations This section explains the operations of the Low-Voltage Detection Reset Circuit and the Low-voltage Detection Interrupt Circuit. Operations of Low-Voltage Detection Reset Circuit  Operations The Low-Voltage Detection Reset Circuit always enters a monitoring state after power-on. This circuit generates a reset signal when the power supply voltage (VCC) falls below the detection voltage.
Page 179 CHAPTER 5: Low-voltage Detection Operations of Low-voltage Detection Interrupt Circuit  Operations The Low-voltage Detection Interrupt Circuit monitors the power supply voltage (VCC) and generates an interrupt signal when the power supply voltage falls below the specified voltage. An interrupt request is enabled when 1 is set to the LVDIE bit of the Low-voltage Detection Voltage Control Register.
Page 180 CHAPTER 5: Low-voltage Detection Notes: − This circuit does not conduct monitoring the power supply voltage if PCLK2 is gated by Timer mode, RTC mode, Stop mode, Deep standby RTC mode, Deep standby Stop mode, or APB2 Prescaler Register (APBC2_PSR) while waiting for the stabilization of the Low-voltage Detection Circuit.
Page 181: Setup Procedure Examples
CHAPTER 5: Low-voltage Detection Setup Procedure Examples This section explains the procedures to set up the Low-voltage Detection Circuit, giving examples. Figure 4-1 Example of Low-voltage Detection Interrupt Setting Start Clearing a low-voltage detection interrupt factor. Write 0x1ACCE553 to the LVD_RLR Register.
Page 182: Registers
CHAPTER 5: Low-voltage Detection Registers This section explains the configuration and functions of the registers used in the Low-voltage Detection Circuit. List of Low-voltage Detection Circuit Registers Table 5-1 List of Low-voltage Detection Circuit Registers Abbreviation Register Name Reference LVD_CTL Low-voltage Detection Voltage Control Register LVD_STR Low-voltage Detection Interrupt Factor Register...
Page 183: Low-Voltage Detection Voltage Control Register (Lvd_Ctl)
CHAPTER 5: Low-voltage Detection Low-voltage Detection Voltage Control Register (LVD_CTL) The Low-voltage Detection Voltage Control Register (LVD_CTL) controls whether to enable monitoring the power supply voltage for a low-voltage detection interrupt and specifies the detection voltage for a low-voltage detection interrupt. Field LVDIE SVHI...
Page 184 CHAPTER 5: Low-voltage Detection [bit1:0] Reserved: Reserved bits The read value is undefined. These bits have no effect when written. Notes: − The low-voltage detection interrupt enable bit (LVDIE) must be enabled after 0 was written to the LVDCL bit of the Low-voltage Detection Interrupt Clear Register (LVD_CLR) to clear the low-voltage detection interrupt factor bit (LVDIR).
Page 185: Low-Voltage Detection Interrupt Factor Register (Lvd_Str)
CHAPTER 5: Low-voltage Detection Low-voltage Detection Interrupt Factor Register (LVD_STR) The Low-voltage Detection Interrupt Factor Register (LVD_STR) holds a low-voltage detection interrupt factor. Field LVDIR Reserved Attribute Initial value [bit7] LVDIR: Low-voltage detection interrupt factor bit Description A low-voltage detection interrupt request is not detected. [Initial value] A low-voltage detection interrupt request has been detected.
Page 186: Low-Voltage Detection Interrupt Factor Clear Register (Lvd_Clr)
CHAPTER 5: Low-voltage Detection Low-voltage Detection Interrupt Factor Clear Register (LVD_CLR) The Low-voltage Detection Interrupt Factor Clear Register (LVD_CLR) clears a low-voltage detection interrupt factor. Field LVDCL Reserved Attribute Initial value [bit7] LVDCL: Low-voltage detection interrupt factor clear bit Description Clears the low-voltage detection interrupt bit (LVDIR) of the Low-voltage Detection Interrupt Factor Register (LVD_STR) to 0.
Page 187: Low-Voltage Detection Voltage Protection Register (Lvd_Rlr)
CHAPTER 5: Low-voltage Detection Low-voltage Detection Voltage Protection Register (LVD_RLR) The Low-voltage Detection Voltage Protection Register (LVD_RLR) write-protects the Low-voltage Detection Voltage Control Register (LVD_CTL). Field LVDLCK[31:16] Attribute Initial value 0x0000 Field LVDLCK[15:0] Attribute Initial value 0x0001 [bit31:0] LVDLCK[31:0]: Low-voltage Detection Voltage Control Register protection bits −...
Page 188: Low-Voltage Detection Circuit Status Register (Lvd_Str2)
CHAPTER 5: Low-voltage Detection Low-voltage Detection Circuit Status Register (LVD_STR2) The Low-voltage Detection Circuit Status Register (LVD_STR2) checks the operation status of a low-voltage detection interrupt. Field LVDIRDY Reserved Attribute Initial value [bit7] LVDIRDY : Low-voltage detection interrupt status flag Description Stabilization wait state or monitoring stop state [Initial value] Monitoring state...
Page 189: Chapter 6: Low Power Consumption Mode
CHAPTER 6: Low Power Consumption Mode This chapter explains the functions and operations of the low power consumption mode. 1. Overview of Low Power Consumption Mode 2. Configuration of CPU Operation Modes 3. Operations in Standby Modes 4. Examples of Procedure for Setting Standby Mode 5.
Page 190: Overview Of Low Power Consumption Mode
CHAPTER 6: Low Power Consumption Mode Overview of Low Power Consumption Mode The system has two types of low power consumption mode, standby mode and deep standby mode, for reducing power consumption. The standby mode consists of Sleep mode, Timer mode, RTC mode and Stop mode;...
Page 191 CHAPTER 6: Low Power Consumption Mode Overview of Run Modes A Run mode is defined according to which clock is selected as the master clock. A base clock acquired by dividing a master clock frequency is supplied to the CPU clock, the AHB bus clock and the APB bus clock to run the CPU, buses and most peripherals.
Page 192 CHAPTER 6: Low Power Consumption Mode Overview of Sleep Modes Sleep mode is classified as a standby mode. In Sleep mode, the clock supply to the CPU stops. Since the stop of the clock supply to the CPU causes the CPU to stop, power consumption is reduced. Resources connected to the AHB bus and the APB bus continue operating.
Page 193 CHAPTER 6: Low Power Consumption Mode Overview of Timer Modes Timer mode is classified as a standby mode. In Timer mode, the base clock supply stops. Since the stop of the base clock supply causes the CPU clock, the AHB bus clock and all APB bus clocks to stop, power consumption is further reduced.
Page 194 CHAPTER 6: Low Power Consumption Mode Overview of Deep Standby RTC Mode Deep standby RTC mode is classified as a deep standby mode. In deep standby RTC mode, all oscillators stop except for the sub oscillator. All functions stop operating except for the RTC and the Low Voltage Detection Circuit.
Page 195: Configuration Of Cpu Operation Modes
CHAPTER 6: Low Power Consumption Mode Configuration of CPU Operation Modes This section explains the configuration of CPU operation modes. CPU Operation Mode Transition Diagram Figure 2-1 shows the CPU operation mode transition diagram. Figure 2-1 CPU Operation Mode Transition Diagram Power-on (1) Power-on reset (2) Release of power-on reset...
Page 196 CHAPTER 6: Low Power Consumption Mode High-speed CR Mode Transition Diagram In high speed CR mode, the high speed CR oscillator clock is used as the master clock. Figure 2-2 High-speed CR Mode Transition Diagram A-6 SLEEP mode (SLEEPDEEP = 0 A-1 Transition to RUN mode and WFI/WFE instruction) Other mode...
Page 197 CHAPTER 6: Low Power Consumption Mode Main Mode Transition Diagram In main mode, the main oscillator clock is used as the master clock. Figure 2-3 Main Mode Transition Diagram B-6 SLEEP mode (SLEEPDEEP = 0 and B-1 Transition to RUN mode (MORDY = 1) Other mode WFI/WFE instruction) B-2 Start of main oscillator (MORDY = 0)
Page 198 CHAPTER 6: Low Power Consumption Mode Low-speed CR Mode Transition Diagram In low speed CR mode, the low speed CR oscillator clock is used as the master clock. Figure 2-4 Low-speed CR Mode Transition Diagram C-1 Transition to RUN mode C-6 SLEEP mode (SLEEPDEEP = 0, WFI/WFE instruction) Other mode (oscillation stabilized)
Page 199 CHAPTER 6: Low Power Consumption Mode Sub Mode Transition Diagram In sub mode, the sub oscillator clock is used as the master clock. Figure 2-5 Sub Mode Transition Diagram D-1 Transition to RUN mode D-6 SLEEP mode (SLEEPDEEP = 0, WFI/WFE instruction) Other mode (SORDY = 1) D-7 Interrupt...
Page 200 CHAPTER 6: Low Power Consumption Mode PLL Mode Transition Diagram In PLL mode, the PLL clock is used as the master clock. Figure 2-6 PLL Mode Transition Diagram E-1 Transition to RUN mode (PLRDY = 1) Interrupt Main mode TIMER mode (SLEEPDEEP = 1, RTCE = 0, E-2 Start of PLL oscillation (PLRDY = 0) DSTM = 0, STM = 00, WFI/WFE instruction) E-3 End of oscillation stabilization wait...
Page 201 CHAPTER 6: Low Power Consumption Mode MOSCE: MOSCE bit in System Clock Mode Control Register (SCM_CTL) SOSCE: SOSCE bit in System Clock Mode Control Register (SCM_CTL) PLLE: PLLE bit in System Clock Mode Control Register (SCM_CTL) RCS: RSC bit in System Clock Mode Control Register (SCM_CTL) MORDY: MORDY bit in System Clock Mode Status Register (SCM_STR) SORDY:...
Page 202: Operations In Standby Modes
CHAPTER 6: Low Power Consumption Mode Operations in Standby Modes This section explains the operations in standby modes. There are four types of standby mode: Sleep mode (high speed CR sleep mode, main sleep mode, PLL sleep mode, low speed CR sleep mode and sub sleep mode), Timer mode (high speed CR timer mode, main timer mode, PLL timer mode, low speed CR timer mode and sub timer mode), RTC mode and STOP mode.
Page 203 CHAPTER 6: Low Power Consumption Mode Table 3-2 Clock Operation States in Timer Mode Timer Mode High Speed CR Main Timer Low Speed CR PLL Timer Mode Sub Timer Mode Timer Mode Mode Timer Mode High speed CR clock Operating Stopped The state changes The state changes...
Page 204 CHAPTER 6: Low Power Consumption Mode Factors for Returning from Standby Mode Table 3-4 shows factors for returning from Sleep, Timer, RTC and Stop modes. Table 3-4 Factors for Returning from Standby Mode Sleep Mode Timer Mode RTC Mode Stop Mode −...
Page 205: Operations In Sleep Modes (High Speed Cr Sleep Mode, Main Sleep Mode, Pll Sleep Mode, Low Speed Cr Sleep Mode, Sub Sleep Mode)
CHAPTER 6: Low Power Consumption Mode Operations in Sleep Modes (High-Speed CR Sleep Mode, Main Sleep Mode, PLL Sleep Mode, Low-Speed CR Sleep Mode, Sub Sleep Mode) Sleep mode is classified as a standby mode. In Sleep mode, the CPU clock stops and, in turn, power consumption is reduced.
Page 206 CHAPTER 6: Low Power Consumption Mode Return from Sleep Mode The CPU returns from Sleep mode in one of the following situations.  Return due to reset If a reset (INITX pin input reset, low voltage detection reset, software watchdog reset, hardware watchdog reset, clock supervisor reset or anomalous frequency detection reset) occurs, the CPU switches to high speed CR run mode regardless of the clock mode.
Page 207: Operations In Timer Modes (High Speed Cr Timer Mode, Main Timer Mode, Pll Timer Mode, Low Speed Cr Timer Mode, Sub Timer Mode)
CHAPTER 6: Low Power Consumption Mode Operations in Timer Modes (High-Speed CR Timer Mode, Main Timer Mode, PLL Timer Mode, Low-Speed CR Timer Mode, Sub Timer Mode) In Timer mode, the base clock supply stops. Since the stop of the base clock supply causes the CPU clock, the AHB bus clock and all APB bus clocks to stop, power consumption is further reduced.
Page 208 CHAPTER 6: Low Power Consumption Mode Return from Timer Mode The CPU returns from Timer mode in one of the following situations.  Return due to reset If a reset (INITX pin input reset, low voltage detection reset, hardware watchdog reset, clock supervisor reset or anomalous frequency detection reset (main timer mode or PLL timer mode)) occurs, the CPU switches to high speed CR run mode regardless of the clock mode.
Page 209: Operations In Rtc Mode
CHAPTER 6: Low Power Consumption Mode Operations in RTC Mode In RTC mode, all oscillators stop except for the sub oscillator. All functions stop operating except for the watch counter, the RTC and the Low Voltage Detection Circuit. Functions of RTC Mode ...
Page 210 CHAPTER 6: Low Power Consumption Mode Return from RTC Mode The CPU returns from RTC mode in one of the following situations.  Return due to reset If a reset (INITX pin input reset or low voltage detection reset) occurs, the CPU switches to high speed CR run mode regardless of the clock mode.
Page 211 CHAPTER 6: Low Power Consumption Mode  Built-in regulator voltage stabilization wait at return The CPU automatically secures a voltage stabilization wait time (a few hundred µs) for the operation mode transition of the built-in regulator before returning from RTC mode. After the voltage stabilization wait time has lapsed, the CPU executes the return operation.
Page 212: Operations In Stop Mode
CHAPTER 6: Low Power Consumption Mode Operations in Stop Mode In Stop mode, all oscillators stop. All functions stop operating except for the Low Voltage Detection Circuit. Functions of Stop Mode  CPU and on-chip memory In STOP mode, the CPU clock supplied to the CPU, and the AHB bus clock supplied to the on-chip memory and the DMA controller stop.
Page 213 CHAPTER 6: Low Power Consumption Mode Return from Stop Mode The CPU returns from STOP mode in one of the following situations.  Return due to reset If a reset (INITX pin input reset or low voltage detection reset) occurs, the CPU switches to high speed CR run mode regardless of the clock mode.
Page 214 CHAPTER 6: Low Power Consumption Mode  Built-in regulator voltage stabilization wait at return The CPU automatically secures a voltage stabilization wait time (a few hundred s) for the operation mode transition of the built-in regulator before returning from Stop mode. After the voltage stabilization wait time has lapsed, the CPU executes the return operation.
Page 215: Examples Of Procedure For Setting Standby Mode
CHAPTER 6: Low Power Consumption Mode Examples of Procedure for Setting Standby Mode This section provides examples of procedure for setting a standby mode. Figure 4-1 Example of Procedure for Setting Main Timer Mode Start Write 0 to RTCE in PMD_CTL register. Write 0x1ACC to KEY, 0 to DSTM, 0b00 to STM in STB_CTL register together.
Page 216 CHAPTER 6: Low Power Consumption Mode Figure 4-2 Procedure for Setting RTC Mode (with Main Clock Selected as Master Clock) Start Write 1 to RTCE in PMD_CTL register. Write 0x1ACC to KEY, 0 to DSTM, 0b10 to STM in STB_CTL register together. Write 1 to SLEEPDEEP.
Page 217 CHAPTER 6: Low Power Consumption Mode Notes: − Before making the CPU transit to RTC mode, ensure that the Flash memory automatic algorithm has terminated. − Writing 1 to the RTCE bit in the RTC Mode Control Register (PMD_CTL) is effective only if the SORDY bit in the System Clock Mode Status Register (SCM_STR) is 1.
Page 218 CHAPTER 6: Low Power Consumption Mode Figure 4-3 Procedure for Setting Stop Mode (with Main Clock Selected as Master Clock) Start Write 0 to RTCE in PMD_CTL register. Write 0x1ACC to KEY, 0 to DSTM, 0b10 to STM in STB_CTL register together. Write 1 to SLEEPDEEP.
Page 219: Operations In Deep Standby Modes
CHAPTER 6: Low Power Consumption Mode Operations in Deep Standby Modes This section explains the operations in deep standby modes. There are two deep standby modes: deep standby RTC mode and deep standby stop mode. Clock Operation States in Deep Standby Mode The table below shows the respective states of the oscillator clocks, CPU clock, AHB bus clock and APB bus clocks in deep standby RTC mode and deep standby stop mode.
Page 220 CHAPTER 6: Low Power Consumption Mode Internal Power Supply Status and Reset Status in Deep Standby Mode This section shows the power supply status of each function in deep standby mode and the reset status on a deep standby transition reset. Table 5-3 Internal Power Supply Status and Reset Status in Deep Standby Mode Power Supply Status Reset Status...
Page 221: Operations In Deep Standby Rtc Mode
CHAPTER 6: Low Power Consumption Mode Operations in Deep Standby RTC Mode In deep standby RTC mode, all oscillators stop except for the sub oscillator. All functions stop operating except for the RTC, the HDMI-CEC/Remote Control Reception and the Low Voltage Detection Circuit. The power supply for CPUs, on-chip Flash memory, SRAM0 /1/2* and peripherals excluding the RTC, the HDMI-CEC/Remote Control Reception, the Low Voltage Detection Circuit and GPIO are turned off inside the chip.
Page 222 CHAPTER 6: Low Power Consumption Mode Return from Deep Standby RTC Mode The CPU returns from deep standby RTC mode in one of the following situations.  Return due to resets, interrupts and WKUP pin input If a reset (INITX pin input reset or low voltage detection reset) occurs, or the CPU receives a request for an effective RTC interrupt, for an effective HDMI-CEC/Remote Control Reception interrupt, for an effective low voltage detection interrupt or for WKUP pin input, the CPU returns from deep standby RTC mode, and regardless of the clock mode, switches to high speed CR run mode on a deep standby...
Page 223: Operations In Deep Standby Stop Mode
CHAPTER 6: Low Power Consumption Mode Operations in Deep Standby Stop Mode In deep standby stop mode, all oscillators stop. All functions stop operating except for the Low Voltage Detection Circuit. The power supply for CPUs, on-chip Flash memory, SRAM0/1/2* and peripherals excluding the RTC, the HDMI-CEC/Remote Control Reception, the Low Voltage Detection Circuit and GPIO are turned off inside the chip.
Page 224 CHAPTER 6: Low Power Consumption Mode Return from Deep Standby Stop Mode The CPU returns from deep standby stop mode in one of the following situations.  Return due to resets, interrupts and WKUP pin input If a reset (INITX pin input reset or low voltage detection reset) occurs, or the CPU receives a request for an effective low voltage detection interrupt or for WKUP pin input, the CPU returns from deep standby stop mode, and regardless of the clock mode, switches to high speed CR run mode on a deep standby transition reset.
Page 225: Examples Of Procedure For Setting Deep Standby Mode
CHAPTER 6: Low Power Consumption Mode Examples of Procedure for Setting Deep Standby Mode This section provides examples of procedure for setting a deep standby mode. Figure 6-1 Example of Procedure for Setting Deep Standby RTC Mode Start Write 1 to RTCE in PMD_CTL register. Write 0x1ACC to KEY, 1 to DSTM, 0b10 to STM in STB_CTL register together.
Page 226 CHAPTER 6: Low Power Consumption Mode Figure 6-2 Example of Procedure for Setting Deep Standby Stop Mode Start Write 0 to RTCE in PMD_CTL register. Write 0x1ACC to KEY, 1 to DSTM, 0b10 to STM in STB_CTL register together. Write 1 to SLEEPDEEP. Execute WFI instruction or WFE instruction.
Page 227: Procedure For Determining Factor For Returning From Deep Standby Mode
CHAPTER 6: Low Power Consumption Mode Procedure for Determining Factor for Returning from Deep Standby Mode Figure 7-1 shows an example of procedure for determining the factor for returning from a deep standby mode. Figure 7-1 Procedure for Determining the Factor for Returning from a Deep Standby Mode Reset release Is any bit in deep standby return factor registers 1...
Page 228: List Of Low Power Consumption Mode Registers
CHAPTER 6: Low Power Consumption Mode List of Low Power Consumption Mode Registers This section explains the configuration and functions of registers used in low power consumption mode. List of Low Power Consumption Mode Registers Abbreviation Register Name Reference STB_CTL Standby Mode Control Register ...
Page 229: Standby Mode Control Register (Stb_Ctl)
CHAPTER 6: Low Power Consumption Mode Standby Mode Control Register (STB_CTL) The Standby Mode Control Register controls standby modes and deep standby modes. The value of the SPL bit, DSTM bit or STM bit is effective only when it is written at the same time as 0x1ACC is written to the KEY bits.
Page 230 CHAPTER 6: Low Power Consumption Mode [bit2] DSTM: Deep standby mode select bit This bit selects whether the CPU transits to a standby mode or a deep standby mode. [bit1:0] STM: Standby mode select bits These bits, together with the DSTM bit in this register and the RTCE bit in the RTC Mode Control Register (PMD_CTL), select a standby mode to which the CPU transits from one of the following modes: Timer mode, RTC mode, Stop mode, deep standby RTC mode or deep standby stop mode.
Page 231: Sub Clock Supply Control Register (Rck_Ctl)
CHAPTER 6: Low Power Consumption Mode Sub Clock Supply Control Register (RCK_CTL) The Sub Clock Supply Control Register controls clock supply to the RTC, HDMI-CEC/remote control reception. Power consumption can be reduced by stopping the clock supply to unused resource. This register is available only in certain product TYPE.
Page 232: Rtc Mode Control Register (Pmd_Ctl)
CHAPTER 6: Low Power Consumption Mode RTC Mode Control Register (PMD_CTL) The RTC Mode Control Register selects whether the CPU transits to either RTC mode or Stop mode, or to either deep standby RTC mode or deep standby stop mode. Field Reserved RTCE...
Page 233: Deep Standby Return Factor Register 1 (Wrfsr)
CHAPTER 6: Low Power Consumption Mode Deep Standby Return Factor Register 1 (WRFSR) The Deep Standby Return Factor Register 1 indicates the return factors of the low voltage detection reset and the INITX pin input reset that have occurred in a deep standby mode. Field Reserved WLVDH...
Page 234: Deep Standby Return Factor Register 2 (Wifsr)
CHAPTER 6: Low Power Consumption Mode Deep Standby Return Factor Register 2 (WIFSR) The Deep Standby Return Factor Register 2 indicates the return factors of the WKUPx pin input, the low voltage detection (LVD) interrupt, the RTC interrupt and the HDMI-CEC/Remote Control Reception interrupt that have occurred in a deep standby mode.
Page 235 CHAPTER 6: Low Power Consumption Mode [bit1] WLVDI: LVD interrupt return bit This bit indicates the CPU has returned from a deep standby mode due to the LVD interrupt. Description The CPU has not returned from a deep standby mode due to the LVD interrupt. [initial value] The CPU has returned from a deep standby mode due to the LVD interrupt.
Page 236: Deep Standby Return Enable Register (Wier)
CHAPTER 6: Low Power Consumption Mode Deep Standby Return Enable Register (WIER) The Deep Standby Return Enable Register enables the CPU to return from a deep standby mode due to the WKUPx pin input, the low voltage detection (LVD) interrupt, the RTC interrupt and the HDMI-CEC/Remote Control Reception interrupt that have occurred in a deep standby mode.
Page 237 CHAPTER 6: Low Power Consumption Mode [bit2] Reserved: Reserved bit This bit always reads 0. Writing a value to this bit has no effect on operation. [bit1] WLVDE: LVD interrupt return enable bit This bit disables or enables the CPU to return from a deep standby mode due to the LVD interrupt. Description Disables the CPU to return from a deep standby mode due to the LVD interrupt.
Page 238: Wkup Pin Input Level Register (Wilvr)
CHAPTER 6: Low Power Consumption Mode WKUP Pin Input Level Register (WILVR) The WKUP Pin Input Level Register selects the respective valid levels for the WKUP1 to WKUP5 pin inputs having occurred in a deep standby mode. Field Reserved WUI5LV WUI4LV WUI3LV WUI2LV...
Page 239: Deep Standby Ram Retention Register (Dsramr)
CHAPTER 6: Low Power Consumption Mode Deep Standby RAM Retention Register (DSRAMR) The Deep Standby RAM Retention Register controls the retention of data in SRAM2 in a deep standby mode. Field Reserved SRAMR Attribute Initial value 000000 [bit7:2] Reserved: Reserved bits These bits always read 0b000000.
Page 240: Backup Registers 01 To 16 (Bur01 To Bur16)
CHAPTER 6: Low Power Consumption Mode Backup Registers 01 to 16 (BUR01 to BUR16) The Backup Registers are general-purpose registers retaining values in a deep standby mode. Field BUR04 BUR03 BUR02 BUR01 Attribute Initial value 0x00 0x00 0x00 0x00 Field BUR08 BUR07 BUR06...
Page 241: Usage Precautions
CHAPTER 6: Low Power Consumption Mode Usage Precautions Note the following when using the low power consumption mode For a pin shared between analog input and WKUP, if the ADE bit in the Analog Input Setting Register (ADE) is set to 1, the WKUPx pin input is blocked, even when the CPU returning from a deep standby mode due to the WKUPx pin input is enabled.
Page 242 CHAPTER 6: Low Power Consumption Mode FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 243: Chapter 7-1: Vbat Domain Configuration
CHAPTER 7-1: VBAT Domain Configuration The chapter explains the configuration of the VBAT domain. 1. Configuration FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 244: Configuration
CHAPTER 7-1: VBAT Domain Configuration Configuration For the configuration of VBAT domain, see the following relevant chapters. Reference VBAT Domain Chapter of Each Product Table 1-1 Referred VBAT Domain Chapter Product TYPE Referred Chapter TYPE1-M4, TYPE2-M4, Chapter "VBAT domain(A)" TYPE6-M4 TYPE3-M4, TYPE4-M4 Chapter "VBAT domain(B)"...
Page 245: Chapter 7-2: Vbat Domain(A)
CHAPTER 7-2: VBAT Domain(A) This chapter explains the functions and operations of the VBAT power domain(A). 1. Overview of VBAT Domain 2. Configuration of VBAT Domain 3. Chip Power Supply Control 4. Hibernation Control 5. Procedure for Setting 32 kHz Clock 6.
Page 246: Overview Of Vbat Domain
CHAPTER 7-2: VBAT Domain(A) Overview of VBAT Domain The power consumed while the RTC is in operation can be reduced by using the VBAT power supply pin, which provides independent power supply for the RTC (calendar circuit) and the 32 kHz oscillator. Configuration of Power Supply Domain This family consists of the following three power supply domains.
Page 247 CHAPTER 7-2: VBAT Domain(A) On-chip Power Gating In deep standby RTC mode and deep standby stop mode, this family cuts off the power supply for the CPU Domain by using the power switch function built in the chip. The Always-ON Domain keeps the power supply on even in deep standby RTC mode and deep standby stop mode.
Page 248: Configuration Of Vbat Domain
CHAPTER 7-2: VBAT Domain(A) Configuration of VBAT Domain This section explains the internal configuration of the VBAT Domain. Internal Configuration of VBAT Domain Figure 2-1 shows the internal configuration of the VBAT Domain and the connection between the VBAT Domain and the Always-on Domain. Figure 2-1 Internal Configuration of VBAT Domain and Connection between VBAT Domain and Always-on Domain VBAT Domain Always-on Domain...
Page 249: Interfacing With Always-On Domain
CHAPTER 7-2: VBAT Domain(A) Interfacing with Always-on Domain This section explains the methods of interfacing the VBAT Domain withe the Always-on Domain. Overview of Interfacing The VBAT Domain is driven by the 32 kHz oscillation circuit or a clock divided from PCLK. Therefore, if an internal bus is directly connected to a register belonging to the VBAT Domain, a bus master such as the CPU is made to wait when accessing such register.
Page 250 CHAPTER 7-2: VBAT Domain(A) Types of Interface Circuit There are four types of interface circuit as shown in Table 2-1. Table 2-1 Types of Interface Circuit Always-on VBAT Circuit type Transfer clock Figure number Domain Domain Type 1 FF available FF unavailable Figure 2-2 Type 2...
Page 251 CHAPTER 7-2: VBAT Domain(A)  Interface circuit type 2 Figure 2-3 Configuration of Interface Circuit Type 2 VBAT Domain Always-on Domain (Register) (Buffer) Transfer Peripheral 32KHz control function Use this circuit type if the register has to retain data even when the VCC power supply is off. Table 2-3 Behavior of Register of Interface Circuit Type 2 Behavior of register/buffer Initialization of register...
Page 252 CHAPTER 7-2: VBAT Domain(A) The difference between Type 2 Circuit and Type 3 Circuit is the clock for the recall operation and save operation.  Interface circuit type 4 Figure 2-5 Configuration of Interface Circuit Type 4 VBAT Domain Always-on Domain (Register) Peripheral function...
Page 253 CHAPTER 7-2: VBAT Domain(A) Circuit Connected to Interface Circuit The major circuits in the VBAT Domain are the RTC, the VBAT port and the buffer register. The VBAT Domain executes the save operation or the recall operation on the buffer and registers of each circuit together.
Page 254 CHAPTER 7-2: VBAT Domain(A) − CWRITE operation waveform Transfer clock Save data The save data is output from the buffer at a falling edge of the transfer clock and is written to the register at a rising edge of the transfer clock. Three transfer clocks are required for preprocessing before the start of a transfer and three transfer clocks are also required for postprocessing after the end of a transfer.
Page 255 CHAPTER 7-2: VBAT Domain(A)  PWRITE/PREAD Performs a bulk save/recall operation for the registers shown in Table 2-7, which are included in the VBAT port circuit. Table 2-7 List of Registers Transferred by PWRITE/PREAD Register Name Reference Register Name Reference WTCAL0 [RTCCLK] WTCAL1...
Page 256 CHAPTER 7-2: VBAT Domain(A) − PWRITE operation waveform Transfer clock Save data The save data is output from the buffer at a falling edge of the transfer clock and is written to the register at a rising edge of the transfer clock. One transfer clock is required for preprocessing before the start of a transfer.
Page 257 CHAPTER 7-2: VBAT Domain(A)  BWRITE/BREAD The backup registers refer to the 32-byte register area from BREG00 to BREG1F. For the functions of the backup registers, see "2.5 Backup Registers". The interface circuit type for the backup registers is type 3. A save operation is started if 1 is written to Back up register save control bit (BWRITE) in the WTCR20 Register.
Page 258 CHAPTER 7-2: VBAT Domain(A)  Allowed transfer combination Though it should be checked that the TRANS bit in the WTCR0 Register is 0 before the start of a recall operation or of a save operation, the transfers in a combination with the "o" mark in the following table can be executed exceptionally.
Page 259: Rtc
CHAPTER 7-2: VBAT Domain(A) The RTC of the FM4 Family is a calendar circuit with a 32 kHz frequency compensation function. Overview of RTC Functions The RTC has the following functions. − Clock function − Alarm function − Timer function −...
Page 260: 32 Khz Oscillation Circuit
CHAPTER 7-2: VBAT Domain(A) 32 kHz Oscillation Circuit The 32 kHz oscillation circuit is an oscillation circuit exclusively for the crystal oscillator for the clock, and creates the subclock. Overview of Functions of 32 kHz Oscillation Circuit The 32 kHz oscillation circuit has the following functions. −...
Page 261 CHAPTER 7-2: VBAT Domain(A) Application of 32 kHz Oscillation Circuit See "5 Procedure for Setting 32 kHz Clock" for details of application. Registers used for 32 kHz Oscillation Circuit 31 - 24 23 - 16 15 - 8 7 - 0 Initial Value Attribute Reserved...
Page 262: Power-On Circuit
CHAPTER 7-2: VBAT Domain(A) Power-on Circuit The FM4 Family has a power-on circuit independent of the VCC power supply pin detecting the power-on of the VBAT Domain. Overview of Function of Power-on Circuit The power-on circuit in the VBAT Domain has the following function. VBAT power supply pin rising edge detection function While the power-on circuit is outputting the power-on signal, Power-on bit (PON) in the VDET Register reads 1.
Page 263: Backup Registers
CHAPTER 7-2: VBAT Domain(A) Backup Registers The FM4 Family has 32-byte backup registers retaining data with the VBAT power supply. Overview of Function of Backup Registers A backup register retains values written to it while power is being supplied to the VBAT power supply pin. The backup register is reset by the power-on circuit immediately after the VBAT power supply has been turned on.
Page 264 CHAPTER 7-2: VBAT Domain(A) Details of Backup Registers  List of backup registers 31 - 24 23 - 16 15 - 8 7 - 0 Initial Value Attribute BREG03 BREG02 BREG01 BREG00 0x00000000 BREG07 BREG06 BREG05 BREG04 0x00000000 BREG0B BREG0A BREG09 BREG08 0x00000000...
Page 265: Vbat I/O Ports
CHAPTER 7-2: VBAT Domain(A) VBAT I/O Ports The FM4 Family has four I/O ports assigned to the VBAT Domain. These I/O ports (VBAT I/O ports) are controlled by the port control circuit (VBAT port control circuit) of the VBAT Domain, and continues operating even when the VCC power supply is turned off.
Page 266 CHAPTER 7-2: VBAT Domain(A) The interface circuit type of the VBDIR Register is type 4. The interface circuit type of the other registers are type 3. The save operation and recall operation of the 32 kHz oscillation circuit are PWRITE and PREAD respectively.
Page 267 CHAPTER 7-2: VBAT Domain(A) Registers of VBAT I/O Ports  List of registers of VBAT I/O ports 31 - 24 23 - 16 15 - 8 7 - 0 Initial Value Attribute Reserved Reserved Reserved VBPFR 0x0000001C Reserved Reserved Reserved VBPCR 0x00000000 Reserved...
Page 268: Chip Power Supply Control
CHAPTER 7-2: VBAT Domain(A) Chip Power Supply Control This section explains details of applying and cutting off chip power supply. Table of Combinations of VCC Power Supply and VBAT Power Supply Table 3-1 shows the respective states of the VCC power supply and the VBAT power supply. Table 3-1 Combination of VCC Power Supply State and VBAT Power Supply State VBAT Power Supply on VBAT Power Supply off...
Page 269 CHAPTER 7-2: VBAT Domain(A) Driving VBAT Power Supply with battery  Transition of power supply state Figure 3-2 shows how the state of power supply transits when a battery is used as the VBAT power supply. Figure 3-3 shows the respective waveforms of circuits. Power-on bit (PON) in the VDET Register indicates whether the system power supply has been turned on for the first time.
Page 270 CHAPTER 7-2: VBAT Domain(A)  Examples of power supply configuration Figure 3-4 Example of Using Primary Battery as Backup Power Supply On-board regulator On-chip regulator VBAT Power switch Always-on Domain VBAT Domain CPU Domain Figure 3-5 Example of Using Secondary Battery as Backup Power Supply On-board regulator On-chip regulator VBAT...
Page 271: Hibernation Control
CHAPTER 7-2: VBAT Domain(A) Hibernation Control This section shows an example of circuit configuration for controlling off-chip power gating through the microcontroller and an example of the sequence of controlling off-chip gating through the microcontroller. Overview of Hibernation Control Hibernation control turns on or off the VCC power supply (for both Always-on Domain and CPU Domain) by controlling the standby function of the on-board regulator through the VBAT Domain.
Page 272 CHAPTER 7-2: VBAT Domain(A) Table 4-1 Operation of On-board Regulator SYS_STBY VREGCTL = L VREGCTL = H "L" Standby mode Standby mode "H" Standby mode Normal operation mode Figure 4-2 Example of External Connection with Input Voltage (VI) of On-board Regulator Higher than 5.5 V On-chip regulator On-board regulator VBuf...
Page 273 CHAPTER 7-2: VBAT Domain(A) Block Configuration of Hibernation Controller The hibernation controller is part of the RTC circuit. Figure 4-3 shows the configuration of the hibernation controller. Figure 4-3 Hibernation Controller VBAT Domain Always-on Domain CALENDAR (alarm interrupt) EWKUP[0] P49/VWAKEUP P48/VREGCTL HIBRST[0] Example of Hibernation Operation Flow...
Page 274 CHAPTER 7-2: VBAT Domain(A)  Initial settings of hibernation operation Below are the initial settings required for the hibernation operation. − Alarm setting of the RTC For the method of setting the alarm, refer to "CHAPTER: RTC Count Block" in FM4 Family PERIPHERAL MANUAL Timer Part.
Page 275: Procedure For Setting 32 Khz Clock
CHAPTER 7-2: VBAT Domain(A) Procedure for Setting 32 kHz Clock This section explains recommended sequences of setting the 32 kHz oscillation circuit when using the RTC. Features of 32 kHz Oscillation Circuit in VBAT Domain With the 32 kHz oscillation circuit incorporated in the VBAT Domain, even when the CPU Domain and the Always-on Domain are turned off, the 32 kHz oscillation circuit can continue operating and the RTC can continue counting the time.
Page 276 CHAPTER 7-2: VBAT Domain(A)  Examples of operation − No backup power supply is used. VBAT 32KHz Oscillation boost time Oscillation boost time − The backup power supply is used, and the 32 kHz oscillation circuit is linked with the clock control circuit.
Page 277 CHAPTER 7-2: VBAT Domain(A) Not Linking with Clock Control Circuit If always using the backup power supply to keep the RTC operating, do not link the 32 kHz oscillation circuit with the clock control circuit. The average power consumption of the entire system can be reduced by executing the following operations: keep only the VBAT operating with the backup power supply, and use the hibernation control of the VBAT Domain or the external circuit to turn off the VCC power supply while processes by the CPU are not necessary.
Page 278 CHAPTER 7-2: VBAT Domain(A) Not Linking with Clock Control Circuit but Waiting for Oscillation Stabilization It is necessary to not link the 32 kHz oscillation circuit with the clock control circuit when always using the backup power supply to keep the RTC operating. Nonetheless, the 32 kHz oscillation circuit and RTC in the VBAT Domain do not have the oscillation stabilization wait function.
Page 279: Procedure For Setting Vbat I/O Port
CHAPTER 7-2: VBAT Domain(A) Procedure for Setting VBAT I/O Port  When using VBAT I/O as a general-purpose I/O input ・Setting procedure example The following is a setting example of using P46, P47, P48 and P49 all as general-purpose I/O inputs. (1) Initiate the VBAT domain (see Figure 2-6).
Page 280 CHAPTER 7-2: VBAT Domain(A)  When using the VBAT I/O as a general-purpose I/O output: ・Setting procedure example The following is a setting example of using P46, P47, P48 and P49 all as general-purpose I/O outputs. (1) Initiate the VBAT domain (see Figure 2-6). (2) Set the general-purpose IO port to use it as the GPIO pin.
Page 281 CHAPTER 7-2: VBAT Domain(A)  When using the VBAT I/O as a peripheral function: ・Setting procedure example The following is a setting example of using P48 and P49 as peripheral function. (1) Initiate the VBAT domain (see Figure 2-6). (2) Set the general-purpose IO port to use it as the peripheral function. (3) Set the pull-up.
Page 282: Registers
CHAPTER 7-2: VBAT Domain(A) Registers This section explains the register list of the VBAT Domain unit. Table 7-1 shows the registers of the VBAT Domain unit. Table 7-1 Registers of VBAT Domain Unit. Abbreviation Register Name Reference VB_CLKDIV VB_CLKDIV Register WTOSCCNT WTOSCCNT Register CCS/CCB...
Page 283: Vb_Clkdiv Register
CHAPTER 7-2: VBAT Domain(A) VB_CLKDIV Register VB_CLKDIV register set the frequency of transfer clock when the buck-up register and port register are transferred simultaneously. Field DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 Attribute Initial value The interface circuit type for this register is type 1. [bit7:0] DIV[7:0]: Transfer clock set bits for PREAD, PWRITE, BREAD, BWRITE These bits set the transfer clock cycle used in the batch transfer of the backup register and of the port register.
Page 284: Wtosccnt Register
CHAPTER 7-2: VBAT Domain(A) WTOSCCNT Register WTOSCCNT Register specifies the operation of 32 kHz Oscillation circuit. Field Reserved SOSCNTL SOSCEX Attribute Initial value The interface circuit type for this register is type 3. [bit7:2] Reserved: Reserved bits These bits read 0b000000. In a write access to these bits, write 0b000000 to them.
Page 285: Ccs/Ccb Register
CHAPTER 7-2: VBAT Domain(A) CCS/CCB Register CCS Register sets the current value when the oscillation sustains. CCB Register sets the boost current at the oscillation start. Field Attribute Initial value 00001000 The interface circuit type for this register is type 3. [bit7:0] CCS: Oscillation sustain current set bits These bits set the value of current for sustaining oscillation.
Page 286: Boost Register
CHAPTER 7-2: VBAT Domain(A) BOOST Register BOOST Register sets the clock value of oscillation boost. Field Reserved BOOST1 BOOST0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:2] Reserved: Reserved bits These bits read 0b000000. In a write access to these bits, write 0b000000 to them.
Page 287: Ewkup Register
CHAPTER 7-2: VBAT Domain(A) EWKUP Register EWKUP Register displays and clears the request state of the wakeup. Field Reserved WUP0 Attribute Initial value The interface circuit type for this register is type 4. [bit7:1] Reserved: Reserved bits These bits read "0b0000000". In a write access to these bits, write 0b0000000 to them.
Page 288: Hibrst Register
CHAPTER 7-2: VBAT Domain(A) HIBRST Register HIBRST Register sets the hibernation start. Field Reserved HIBRST Attribute Initial value The interface circuit type for this register is type 1. [bit7:1] Reserved: Reserved bits These bits read 0b0000000. In a write access to these bits, write 0b0000000 to them. [bit0] HIBRST: Hibernation start bit Description Reading...
Page 289: Vdet Register
CHAPTER 7-2: VBAT Domain(A) VDET Register VDET Register indicates the state of power-on circuit and clears the power-on signal. Field Reserved Attribute Initial value The interface circuit type for this register is type 4. [bit7] PON: Power-on bit This bit indicates the state of the power-on circuit and clears the power-on signal. Description Indicates that the initialization signal of the power-on circuit has been cleared.
Page 290: Port Function Set Register (Vbpfr)
CHAPTER 7-2: VBAT Domain(A) Port Function Set Register (VBPFR) VBPFR Register selects the usage of pins. Field Reserved SPSR1 SPSR0 VPFR3 VPFR2 VPFR1 VPFR0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:6] Reserved: Reserved bits These bits read 0b00.
Page 291 CHAPTER 7-2: VBAT Domain(A) VBPFR[5:2] setting combinations are as shown in Table 7-4. Table 7-4 VBPFR[5:2] Setting Combinations. VBPFR[5] VBPFR[4] VBPFR[3] VBPFR[2] GPIO 32kHz oscillation GPIO P46 external clock input To use the 32 kHz oscillation circuit, set the function setting bit (VBPFR[5:4]) of the oscillation pin to 0b01. This enables the 32 kHz oscillation circuit to be used without depending on VBPFR[3:2].
Page 292: Pull-Up Set Register (Vbpcr)
CHAPTER 7-2: VBAT Domain(A) Pull-up Set Register (VBPCR) VBPCR Register sets the pull-up of pins. Field Reserved VPCR3 VPCR2 VPCR1 VPCR0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:4] Reserved: Reserved bits These bits read 0b0000. In a write access to these bits, write 0b0000 to them.
Page 293: Port I/O Direction Set Register (Vbddr)
CHAPTER 7-2: VBAT Domain(A) Port I/O Direction Set Register (VBDDR) 7.10 VBDDR Register sets the I/O direction of pins. Field Reserved VDDR3 VDDR2 VDDR1 VDDR0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:4] Reserved: Reserved bits These bits read 0b0000.
Page 294: Port Input Data Register (Vbdir)
CHAPTER 7-2: VBAT Domain(A) Port Input Data Register (VBDIR) 7.11 VBDIR Register indicates the input data of pins. Field Reserved VDIR3 VDIR2 VDIR1 VDIR0 Attribute Initial value The interface circuit type for this register is type 4. [bit7:4] Reserved: Reserved bits These bits read 0b0000.
Page 295: Port Output Data Register (Vbdor)
CHAPTER 7-2: VBAT Domain(A) Port Output Data Register (VBDOR) 7.12 VBDOR Register sets the data output to pins. Field Reserved VDOR3 VDOR2 VDOR1 VDOR0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:4] Reserved: Reserved bits These bits read 0b0000.
Page 296: Port Pseudo-Open Drain Set Register (Vbpzr)
CHAPTER 7-2: VBAT Domain(A) Port Pseudo-Open Drain Set Register (VBPZR) 7.13 VBPZR Register sets the port pseudo-open drain of a pin. Field Reserved VPZR1 VPZR0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:2] Reserved: Reserved bits These bits read 0b000000.
Page 297: Usage Precautions
CHAPTER 7-2: VBAT Domain(A) Usage Precautions Note the following when using the backup power supply. − Charging a primary battery or overcharging a secondary battery may cause battery leakage or fire. Check the features of the battery to be used before deciding the configuration of the circuit around the battery.
Page 298 CHAPTER 7-2: VBAT Domain(A) FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 299: Chapter 7-3: Vbat Domain(B)
CHAPTER 7-3: VBAT Domain(B) This chapter explains the functions and operations of the VBAT power domain(B). 1. Overview of VBAT Domain 2. Configuration of VBAT Domain 3. Chip Power Supply Control 4. Hibernation Control 5. Procedure for Setting 32 kHz Clock 6.
Page 300: Overview Of Vbat Domain
CHAPTER 7-3: VBAT Domain(B) Overview of VBAT Domain The power consumed while the RTC is in operation can be reduced by using the VBAT power supply pin, which provides independent power supply for the RTC (calendar circuit) and the 32 kHz oscillator. Configuration of Power Supply Domain This family consists of the following three power supply domains.
Page 301 CHAPTER 7-3: VBAT Domain(B) On-chip Power Gating In deep standby RTC mode and deep standby stop mode, this family cuts off the power supply for the CPU Domain by using the power switch function built in the chip. The Always-ON Domain keeps the power supply on even in deep standby RTC mode and deep standby stop mode.
Page 302: Configuration Of Vbat Domain
CHAPTER 7-3: VBAT Domain(B) Configuration of VBAT Domain This section explains the internal configuration of the VBAT Domain. Internal Configuration of VBAT Domain Figure 2-1 shows the internal configuration of the VBAT Domain and the connection between the VBAT Domain and the Always-on Domain. Figure 2-1 Internal Configuration of VBAT Domain and Connection between VBAT Domain and Always-on Domain VBAT Domain Always-on Domain...
Page 303: Interfacing With Always-On Domain
CHAPTER 7-3: VBAT Domain(B) Interfacing with Always-on Domain This section explains the methods of interfacing the VBAT Domain withe the Always-on Domain. Overview of Interfacing The VBAT Domain is driven by the 32 kHz oscillation circuit or a clock divided from PCLK. Therefore, if an internal bus is directly connected to a register belonging to the VBAT Domain, a bus master such as the CPU is made to wait when accessing such register.
Page 304 CHAPTER 7-3: VBAT Domain(B) Types of Interface Circuit There are four types of interface circuit as shown in Table 2-1. Table 2-1 Types of Interface Circuit Always-on VBAT Circuit Type Transfer Clock Figure Number Domain Domain Type 1 FF available FF unavailable Figure 2-2 Type 2...
Page 305 CHAPTER 7-3: VBAT Domain(B)  Interface circuit type 2 Figure 2-3 Configuration of Interface Circuit Type 2 VBAT Domain Always-on Domain (Register) (Buffer) Transfer Peripheral 32KHz control function Use this circuit type if the register has to retain data even when the VCC power supply is off. Table 2-3 Behavior of Register of Interface Circuit Type 2 Behavior of Register/Buffer Initialization of register...
Page 306 CHAPTER 7-3: VBAT Domain(B) The difference between Type 2 Circuit and Type 3 Circuit is the clock for the recall operation and save operation.  Interface circuit type 4 Figure 2-5 Configuration of Interface Circuit Type 4 VBAT Domain Always-on Domain (Register) Peripheral function...
Page 307 CHAPTER 7-3: VBAT Domain(B) Circuit Connected to Interface Circuit The major circuits in the VBAT Domain are the RTC(Calendar function), the VBAT port and the buffer register. The VBAT Domain executes the save operation or the recall operation on the buffer and registers of each circuit together.
Page 308 CHAPTER 7-3: VBAT Domain(B) − CWRITE operation waveform Transfer clock Save data The save data is output from the buffer at a rising edge of the transfer clock and is written to the register at a falling edge of the transfer clock. Three transfer clocks are required for preprocessing before the start of a transfer and two transfer clocks are also required for postprocessing after the end of a transfer.
Page 309 CHAPTER 7-3: VBAT Domain(B)  PWRITE/PREAD Performs a bulk save/recall operation for the registers shown in Table 2-7, which are included in the VBAT port circuit. Table 2-7 List of Registers Transferred by PWRITE/PREAD Register Name Reference Register Name Reference WTCAL0 [RTCCLK] WTCAL1...
Page 310 CHAPTER 7-3: VBAT Domain(B) − PWRITE operation waveform Transfer clock Save data The save data is output from the buffer at a falling edge of the transfer clock and is written to the register at a rising edge of the transfer clock. One transfer clock is required for preprocessing before the start of a transfer.
Page 311 CHAPTER 7-3: VBAT Domain(B)  BWRITE/BREAD The backup registers refer to the 32-byte register area from BREG00 to BREG1F. For the functions of the backup registers, see 2.5 Backup Registers. The interface circuit type for the backup registers is type 3. A save operation is started if 1 is written to Back up register save control bit (BWRITE) in the WTCR20 Register.
Page 312 CHAPTER 7-3: VBAT Domain(B)  Allowed transfer combination Though it should be checked that the TRANS bit in the WTCR0 Register is 0 before the start of a recall operation or of a save operation, the transfers in a combination with the "o" mark in the following table can be executed exceptionally.
Page 313: Rtc
CHAPTER 7-3: VBAT Domain(B) The RTC of the FM4 Family is a calendar circuit with a 32 kHz frequency compensation function. Overview of RTC Functions The RTC has the following functions. − Clock function − Alarm function − Timer function (It exists in Always on domain) −...
Page 314: 32 Khz Oscillation Circuit
CHAPTER 7-3: VBAT Domain(B) 32 kHz Oscillation Circuit The 32 kHz oscillation circuit is an oscillation circuit exclusively for the crystal oscillator for the clock, and creates the subclock. Overview of Functions of 32 kHz Oscillation Circuit The 32 kHz oscillation circuit has the following functions. −...
Page 315 CHAPTER 7-3: VBAT Domain(B) Application of 32 kHz Oscillation Circuit See 5 Procedure for Setting 32 kHz Clock for details of application. Registers Used for 32 kHz Oscillation Circuit TYPE1-M4, TYPE2-M4, TYPE3-M4 products 31 - 24 23 - 16 15 - 8 7 - 0 Initial Value Attribute...
Page 316: Power-On Circuit
CHAPTER 7-3: VBAT Domain(B) Power-on Circuit The FM4 Family has a power-on circuit independent of the VCC power supply pin detecting the power-on of the VBAT Domain. Overview of Function of Power-on Circuit The power-on circuit in the VBAT Domain has the following function. VBAT power supply pin rising edge detection function While the power-on circuit is outputting the power-on signal, Power-on bit (PON) in the VDET Register reads 1.
Page 317: Backup Registers
CHAPTER 7-3: VBAT Domain(B) Backup Registers The FM4 Family has 32-byte backup registers retaining data with the VBAT power supply. Overview of Function of Backup Registers A backup register retains values written to it while power is being supplied to the VBAT power supply pin. The backup register is reset by the power-on circuit immediately after the VBAT power supply has been turned on.
Page 318 CHAPTER 7-3: VBAT Domain(B) Details of Backup Registers  List of backup registers 31 - 24 23 - 16 15 - 8 7 - 0 Initial Value Attribute BREG03 BREG02 BREG01 BREG00 0x00000000 BREG07 BREG06 BREG05 BREG04 0x00000000 BREG0B BREG0A BREG09 BREG08 0x00000000...
Page 319: Vbat I/O Ports
CHAPTER 7-3: VBAT Domain(B) VBAT I/O Ports The FM4 Family has four I/O ports assigned to the VBAT Domain. These I/O ports (VBAT I/O ports) are controlled by the port control circuit (VBAT port control circuit) of the VBAT Domain, and continued operating even when the VCC power supply is turned off.
Page 320 CHAPTER 7-3: VBAT Domain(B) The interface circuit type of the VBDIR Register is type 4. The interface circuit type of the other registers are type 3. The save operation and recall operation of the 32 kHz oscillation circuit are PWRITE and PREAD respectively.
Page 321 CHAPTER 7-3: VBAT Domain(B) Registers of VBAT I/O Ports  List of registers of VBAT I/O ports 31 - 24 23 - 16 15 - 8 7 - 0 Initial Value Attribute Reserved Reserved Reserved VBPFR 0x0000001C Reserved Reserved Reserved VBPCR 0x00000000 Reserved...
Page 322: Chip Power Supply Control
CHAPTER 7-3: VBAT Domain(B) Chip Power Supply Control This section explains details of applying and cutting off chip power supply. Table of Combinations of VCC Power Supply and VBAT Power Supply Table 3-1 shows the respective states of the VCC power supply and the VBAT power supply. Table 3-1 Combination of VCC Power Supply State and VBAT Power Supply State VBAT Power Supply on VBAT Power Supply off...
Page 323 CHAPTER 7-3: VBAT Domain(B) Driving VBAT Power Supply with battery  Transition of power supply state Figure 3-2 shows how the state of power supply transits when a battery is used as the VBAT power supply. Figure 3-3 shows the respective waveforms of circuits. Power-on bit (PON) in the VDET Register indicates whether the system power supply has been turned on for the first time.
Page 324 CHAPTER 7-3: VBAT Domain(B)  Examples of power supply configuration Figure 3-4 Example of Using Primary Battery as Backup Power Supply On-board regulator On-chip regulator VBAT Power switch Always-on Domain VBAT Domain CPU Domain Figure 3-5 Example of Using Secondary Battery as Backup Power Supply On-board regulator On-chip regulator VBAT...
Page 325: Hibernation Control
CHAPTER 7-3: VBAT Domain(B) Hibernation Control This section shows an example of circuit configuration for controlling off-chip power gating through the microcontroller and an example of the sequence of controlling off-chip gating through the microcontroller. Overview of Hibernation Control Hibernation control turns on or off the VCC power supply (for both Always-on Domain and CPU Domain) by controlling the standby function of the on-board regulator through the VBAT Domain.
Page 326 CHAPTER 7-3: VBAT Domain(B) Table 4-1 Operation of On-board Regulator SYS_STBY VREGCTL = L VREGCTL = H "L" Standby mode Standby mode "H" Standby mode Normal operation mode Figure 4-2 Example of External Connection with Input Voltage (VI) of On-board Regulator Higher than 5.5 V On-chip regulator On-board regulator VBuf...
Page 327 CHAPTER 7-3: VBAT Domain(B) Block Configuration of Hibernation Controller The hibernation controller is part of the RTC circuit. Figure 4-3 shows the configuration of the hibernation controller. Figure 4-3 Hibernation Controller VBAT Domain Always-on Domain CALENDAR (alarm interrupt) EWKUP[0] P49/VWAKEUP P48/VREGCTL HIBRST[0] Example of Hibernation Operation Flow...
Page 328 CHAPTER 7-3: VBAT Domain(B)  Initial settings of hibernation operation Below are the initial settings required for the hibernation operation. − Alarm setting of the RTC For the method of setting the alarm, refer to Chapter 4-1: RTC Count Block in FM4 Family Peripheral Manual Timer Part.
Page 329: Procedure For Setting 32 Khz Clock
CHAPTER 7-3: VBAT Domain(B) Procedure for Setting 32 kHz Clock This section explains recommended sequences of setting the 32 kHz oscillation circuit when using the RTC. Features of 32 kHz Oscillation Circuit in VBAT Domain With the 32 kHz oscillation circuit incorporated in the VBAT Domain, even when the CPU Domain and the Always-on Domain are turned off, the 32 kHz oscillation circuit can continue operating and the RTC can continue counting the time.
Page 330 CHAPTER 7-3: VBAT Domain(B)  Examples of operation − No backup power supply is used. VBAT 32KHz Oscillation boost time Oscillation boost time − The backup power supply is used, and the 32 kHz oscillation circuit is linked with the clock control circuit.
Page 331 CHAPTER 7-3: VBAT Domain(B) Not Linking with Clock Control Circuit If always using the backup power supply to keep the RTC operating, do not link the 32 kHz oscillation circuit with the clock control circuit. The average power consumption of the entire system can be reduced by executing the following operations: keep only the VBAT operating with the backup power supply, and use the hibernation control of the VBAT Domain or the external circuit to turn off the VCC power supply while processes by the CPU are not necessary.
Page 332 CHAPTER 7-3: VBAT Domain(B) Not Linking with Clock Control Circuit but Waiting for Oscillation Stabilization It is necessary to not link the 32 kHz oscillation circuit with the clock control circuit when always using the backup power supply to keep the RTC operating. Nonetheless, the 32 kHz oscillation circuit and RTC in the VBAT Domain do not have the oscillation stabilization wait function.
Page 333: Procedure For Setting Vbat I/O Port
CHAPTER 7-3: VBAT Domain(B) Procedure for Setting VBAT I/O Port  When using VBAT I/O as a general-purpose I/O input ・Setting procedure example The following is a setting example of using P46, P47, P48 and P49 all as general-purpose I/O inputs. (1) Initiate the VBAT domain (see Figure 2-6).
Page 334 CHAPTER 7-3: VBAT Domain(B)  When using the VBAT I/O as a general-purpose I/O output: ・Setting procedure example The following is a setting example of using P46, P47, P48 and P49 all as general-purpose I/O outputs. (1) Initiate the VBAT domain (see Figure 2-6). (2) Set the general-purpose IO port to use it as the GPIO pin.
Page 335 CHAPTER 7-3: VBAT Domain(B)  When using the VBAT I/O as a peripheral function: ・Setting procedure example The following is a setting example of using P48 and P49 as peripheral function. (1) Initiate the VBAT domain (see Figure 2-6). (2) Set the general-purpose IO port to use it as the peripheral function. (3) Set the pull-up.
Page 336: Registers
CHAPTER 7-3: VBAT Domain(B) Registers This section explains the register list of the VBAT Domain unit. Table 7-1 shows the registers of the VBAT Domain unit. Table 7-1 Registers of VBAT Domain unit. Abbreviation Register Name Reference VB_CLKDIV VB_CLKDIV Register WTOSCCNT WTOSCCNT Register CCS/CCB...
Page 337: Vb_Clkdiv Register
CHAPTER 7-3: VBAT Domain(B) VB_CLKDIV Register VB_CLKDIV register set the frequency of transfer clock when the buck-up register and port register are transferred simultaneously. Field DIV7 DIV6 DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 Attribute Initial value The interface circuit type for this register is type 1. [bit7:0] DIV[7:0]: Transfer clock set bits for PREAD, PWRITE, BREAD, BWRITE These bits set the transfer clock cycle used in the batch transfer of the backup register and of the port register.
Page 338: Wtosccnt Register
CHAPTER 7-3: VBAT Domain(B) WTOSCCNT Register WTOSCCNT Register specifies the operation of 32 kHz Oscillation circuit. Field Reserved SOSCNTL SOSCEX Attribute Initial value The interface circuit type for this register is type 3. [bit7:2] Reserved: Reserved bits These bits read 0b000000. In a write access to these bits, write 0b000000 to them.
Page 339: Ccs/Ccb Register
CHAPTER 7-3: VBAT Domain(B) CCS/CCB Register CCS Register sets the current value when the oscillation sustains. CCB Register sets the boost current at the oscillation start. TYPE3-M4 products ■CCS Register Field Attribute Initial value 00001000 The interface circuit type for this register is type 3. [bit7:0] CCS: Oscillation sustain current set bits These bits set the value of current for sustaining oscillation.
Page 340 CHAPTER 7-3: VBAT Domain(B) TYPE4-M4 products ■CCS Register Field Attribute Initial value 11001110 The interface circuit type for this register is type 3. [bit7:0] CCS: Oscillation sustain current set bits These bits set the value of current for sustaining oscillation. ■CCB Register Field Attribute...
Page 341: Boost Register
CHAPTER 7-3: VBAT Domain(B) BOOST Register BOOST Register sets the clock value of oscillation boost. Field Reserved BOOST1 BOOST0 Attribute Initial value The interface circuit type for this register is type 1. [bit7:2] Reserved: Reserved bits These bits read 0b000000. In a write access to these bits, write 0b000000 to them.
Page 342: Ewkup Register
CHAPTER 7-3: VBAT Domain(B) EWKUP Register EWKUP Register displays and clears the request state of the wakeup. Field Reserved WUP0 Attribute Initial value The interface circuit type for this register is type 4. [bit7:1] Reserved: Reserved bits These bits read 0b0000000. In a write access to these bits, write 0b0000000 to them.
Page 343: Hibrst Register
CHAPTER 7-3: VBAT Domain(B) HIBRST Register HIBRST Register sets the hibernation start. Field Reserved HIBRST Attribute Initial value The interface circuit type for this register is type 1. [bit7:1] Reserved: Reserved bits These bits read 0b0000000. In a write access to these bits, write 0b0000000 to them. [bit0] HIBRST: Hibernation start bit Description Reading...
Page 344: Vdet Register
CHAPTER 7-3: VBAT Domain(B) VDET Register VDET Register indicates the state of power-on circuit and clears the power-on signal. Field Reserved Attribute Initial value The interface circuit type for this register is type 4. [bit7] PON: Power-on bit This bit indicates the state of the power-on circuit and clears the power-on signal. Description Indicates that the initialization signal of the power-on circuit has been cleared.
Page 345: Port Function Set Register (Vbpfr)
CHAPTER 7-3: VBAT Domain(B) Port Function Set Register (VBPFR) VBPFR Register selects the usage of pins. Field Reserved SPSR1 SPSR0 VPFR3 VPFR2 VPFR1 VPFR0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:6] Reserved: Reserved bits These bits read 0b00.
Page 346 CHAPTER 7-3: VBAT Domain(B) VBPFR[5:2] setting combinations are as shown in Table 7-. Table 7-5 VBPFR[5:2] Setting Combinations. VBPFR[5] VBPFR[4] VBPFR[3] VBPFR[2] GPIO 32 kHz oscillation GPIO P46 external clock input To use the 32 kHz oscillation circuit, set the function setting bit (VBPFR[5:4]) of the oscillation pin to 0b01. This enables the 32 kHz oscillation circuit to be used without depending on VBPFR[3:2].
Page 347: Pull-Up Set Register (Vbpcr)
CHAPTER 7-3: VBAT Domain(B) Pull-up Set Register (VBPCR) VBPCR Register sets the pull-up of pins. In TYPE4-M4 products, there is no pull-up function of P46/X0A pin and P47/X1A pin, therefore the settings of the VBPCR[3:2] are invalid. Field Reserved VPCR3 VPCR2 VPCR1 VPCR0...
Page 348: Port I/O Direction Set Register (Vbddr)
CHAPTER 7-3: VBAT Domain(B) Port I/O Direction Set Register (VBDDR) 7.10 VBDDR Register sets the I/O direction of pins. In TYPE4-M4 products, the GPIO function of P46/X0A pin and P47/X1A pin is an input only, therefore they cannot be used as an output port. Field Reserved VDDR3...
Page 349: Port Input Data Register (Vbdir)
CHAPTER 7-3: VBAT Domain(B) Port Input Data Register (VBDIR) 7.11 VBDIR Register indicates the input data of pins. Field Reserved VDIR3 VDIR2 VDIR1 VDIR0 Attribute Initial value The interface circuit type for this register is type 4. [bit7:4] Reserved: Reserved bits These bits read 0b0000.
Page 350: Port Output Data Register (Vbdor)
CHAPTER 7-3: VBAT Domain(B) Port Output Data Register (VBDOR) 7.12 VBDOR Register sets the data output to pins. In TYPE4-M4 products, the GPIO function of P46/X0A pin and P47/X1A pin is an input only, therefore the settings of the VBDOR[3:2] are invalid. Field Reserved VDOR3...
Page 351: Port Pseudo-Open Drain Set Register (Vbpzr)
CHAPTER 7-3: VBAT Domain(B) Port Pseudo-Open Drain Set Register (VBPZR) 7.13 VBPZR Register sets the port pseudo-open drain of a pin. Field Reserved VPZR1 VPZR0 Attribute Initial value The interface circuit type for this register is type 3. [bit7:2] Reserved: Reserved bits These bits read 0b000000.
Page 352: Usage Precautions
CHAPTER 7-3: VBAT Domain(B) Usage Precautions Note the following when using the backup power supply. − Charging a primary battery or overcharging a secondary battery may cause battery leakage or fire. Check the features of the battery to be used before deciding the configuration of the circuit around the battery.
Page 353: Chapter 8: Interrupts
CHAPTER 8: Interrupts This chapter explains details of the interrupt controller. 1. Overview 2. Configuration 3. Lists of Interrupts 4. Registers 5. Usage Precautions FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 354: Overview
CHAPTER 8: Interrupts Overview The Cortex-M4 CPU core is equipped with the Nested Vectored Interrupt Controller (NVIC) inside the core. The NVIC supports reserved system exceptions and 128 peripheral interrupts, and can set the priority order of 16 interrupt priority levels (with a built-in 4-bit register). This section explains interrupt signals from peripheral functions installed in the microcontroller and the connection between the NVIC and the interrupt signals.
Page 355 CHAPTER 8: Interrupts Figure 2-1 illustrates how the NVIC is connected to the interrupt signals input from peripheral functions, the DMAC and the DSTC. Details of the connection are explained below. NVIC The NVIC supports reserved system exceptions and 128 peripheral interrupts. For details of the NVIC, refer to Cortex-M4 Technical Reference Manual.
Page 356 CHAPTER 8: Interrupts DMAC Transfer Request Connection Selection Certain interrupt signals from peripheral functions can be used as DMA transfer request signals to the DMAC. The output selector circuit (SEL in Figure 2-1) determines whether such interrupt signals are connected to the NVIC or are connected to the DMAC as DMA transfer request signals (IDREQ to DMAC in Figure 2-1).
Page 357 CHAPTER 8: Interrupts Transfer request signal from peripheral is not inputted to the NVIC Transfer request signal from peripheral is inputted to the DSTC, start the transfer. HWINT[n] from the DSTC is inputted to the NVIC, notify transfer completion. In the case of this type, the input port of NVIC is separated the interrupt from peripheral and HWINT[n] interrupt of the transfer completion from the DSTC.
Page 358: Lists Of Interrupts
CHAPTER 8: Interrupts Lists of Interrupts This section shows a list of sources of exceptions and interrupt sources input to the NVIC, a list of interrupts that can be transferred by the DMA transfer by the DMAC, and a list of interrupts that can be transferred by the DMA transfer by the DSTC.
Page 359 CHAPTER 8: Interrupts Table 3-1 List of Exception Sources and Interrupt Sources (TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE5-M4, TYPE6-M4 Products) Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x000 (Stack pointer initial value) 0x004 Reset Non-maskable interrupt (NMI) 0x008 Hardware watchdog timer interrupt 0x00C...
Page 360 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source QPRC ch.0 PC match & RC match interrupt QPRC ch.0 out-of-range interrupt QPRC ch.0 count inversion interrupt QPRC ch.0 overflow interrupt 0x08C QPRC ch.0 underflow interrupt QPRC ch.0 zero index interrupt QPRC ch.0 PC &...
Page 361 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source MFT unit 1 FRT ch.2 zero detection interrupt 0x0B4 MFT unit 1 FRT ch.1 zero detection interrupt MFT unit 1 FRT ch.0 zero detection interrupt MFT unit 1 ICU ch.3 input edge detection interrupt MFT unit 1 ICU ch.2 input edge detection interrupt 0x0B8...
Page 362 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source Base timer ch.7 source 1 (IRQ1) interrupt 0x0F8 Base timer ch.7 source 0 (IRQ0) interrupt Dual timer ch.2 interrupt 0x0FC Dual timer ch.1 interrupt 0x100 Watch counter interrupt 0x104 External bus error output interrupt...
Page 363 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source A/D converter unit 1 range comparison result interrupt A/D converter unit 1 conversion result comparison interrupt 0x174 A/D converter unit 1 FIFO overrun interrupt A/D converter unit 1 scan conversion interrupt A/D converter unit 1 priority conversion interrupt USB ch.0 function endpoint 5 DRQ interrupt USB ch.0 function endpoint 4 DRQ interrupt...
Page 364 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source External pin interrupt ch.23 External pin interrupt ch.22 0x1B4 External pin interrupt ch.21 External pin interrupt ch.20 External pin interrupt ch.27 External pin interrupt ch.26 0x1B8 External pin interrupt ch.25 External pin interrupt ch.24...
Page 365 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x1EC MFS ch.10 reception interrupt MFS ch.10 status interrupt 0x1F0 MFS ch.10 transmission interrupt 0x1F4 MFS ch.11 reception interrupt MFS ch.11 status interrupt 0x1F8 MFS ch.11 transmission interrupt A/D converter unit 2 range comparison result interrupt A/D converter unit 2 conversion result comparison interrupt 0x1FC...
Page 366 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x228 MFS ch.13 reception interrupt MFS ch.13 status interrupt 0x22C MFS ch.13 transmission interrupt 0x230 MFS ch.14 reception interrupt MFS ch.14 status interrupt 0x234 MFS ch.14 transmission interrupt 0x238 MFS ch.15 reception interrupt MFS ch.15 status interrupt...
Page 367 CHAPTER 8: Interrupts Table 3-2 List of Exception Sources and Interrupt Sources (TYPE4-M4 Product) Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x000 (Stack pointer initial value) 0x004 Reset Non-maskable interrupt (NMI) 0x008 Hardware watchdog timer interrupt 0x00C Hard fault 0x010...
Page 368 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x090 Reserved MFT unit 0 WFG timer 54 interrupt MFT unit 0 WFG timer 32 interrupt 0x094 MFT unit 0 WFG timer 10 interrupt MFT unit 0 DTIF (motor emergency stop) interrupt 0x098 Reserved 0x09C...
Page 369 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source Base timer ch.4 source 1 (IRQ1) interrupt 0x0EC Base timer ch.4 source 0 (IRQ0) interrupt Base timer ch.5 source 1 (IRQ1) interrupt 0x0F0 Base timer ch.5 source 0 (IRQ0) interrupt Base timer ch.6 source 1 (IRQ1) interrupt 0x0F4 Base timer ch.6 source 0 (IRQ0) interrupt...
Page 370 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x158 MFS ch.5 reception interrupt MFS ch.5 status interrupt 0x15C MFS ch.5 transmission interrupt 0x160 MFS ch.6 reception interrupt MFS ch.6 status interrupt 0x164 MFS ch.6 transmission interrupt 0x168 MFS ch.7 reception interrupt MFS ch.7 status interrupt...
Page 371 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x188 Reserved 0x18C DMAC ch.0 interrupt 0x190 DMAC ch.1 interrupt 0x194 DMAC ch.2 interrupt 0x198 DMAC ch.3 interrupt 0x19C DMAC ch.4 interrupt 0x1A0 DMAC ch.5 interrupt 0x1A4 DMAC ch.6 interrupt 0x1A8...
Page 372 CHAPTER 8: Interrupts Exc. No. IRQ no. Vector Offset DMAC DSTC Exception and Interrupt Source 0x20C Reserved 0x210 Reserved S ch.1 interrupt 0x214 Programmable CRC interrupt S ch.0 interrupt SD card interrupt 0x218 Aggregation of all SD I/F interrupt sources 0x21C Flash I/F 0x220...
Page 373 CHAPTER 8: Interrupts DMA Transfer Request Signals Input to DMAC Table 3-3 shows the interrupt signal names input as DMA transfer request signals to the DMAC. Numbers in the table correspond to the bit numbers of the DRQSEL Register (IDREQ numbers of the DMAC). Table 3-3 List of DMA Transfer Request Signals Input to DMAC Number Interrupt Signal Name...
Page 374 CHAPTER 8: Interrupts DMA Transfer Request Signals Input to DSTC Table 3-4 (TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE5-M4, TYPE6-M4 Products) and Table 3-5 (TYPE4-M4 Product) show interrupt signal names input as DMA transfer request signals to the DSTC. Numbers in the table correspond to the numbers of the DREQENB[n] Registers of the DSTC. In case of Separated type peripheral, it is described as DMA request signals name (Speparated) Table 3-4 List of Interrupt Signals Input to DSTC (TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE5-M4, TYPE6-M4 Products)
Page 375 CHAPTER 8: Interrupts Number Interrupt Signal Name MFT unit 0 OCU ch.0 match detection interrupt MFT unit 0 OCU ch.1 match detection interrupt MFT unit 0 OCU ch.2 match detection interrupt MFT unit 0 OCU ch.3 match detection interrupt MFT unit 0 OCU ch.4 match detection interrupt MFT unit 0 OCU ch.5 match detection interrupt MFT unit 1 WFG timer 10 interrupt MFT unit 1 WFG timer 32 interrupt...
Page 376 CHAPTER 8: Interrupts Number Interrupt Signal Name MFS ch.4 transmission interrupt MFS ch.5 reception interrupt MFS ch.5 transmission interrupt MFS ch.6 reception interrupt MFS ch.6 transmission interrupt MFS ch.7 reception interrupt MFS ch.7 transmission interrupt USB ch.0 function endpoint 1 DRQ interrupt USB ch.0 function endpoint 2 DRQ interrupt USB ch.0 function endpoint 3 DRQ interrupt USB ch.0 function endpoint 4 DRQ interrupt...
Page 377 CHAPTER 8: Interrupts Number Interrupt Signal Name MFT unit 2 WFG timer 54 interrupt MFT unit 2 FRT ch.0 peak value detection interrupt MFT unit 2 FRT ch.1 peak value detection interrupt MFT unit 2 FRT ch.2 peak value detection interrupt MFT unit 2 FRT ch.0 zero detection interrupt MFT unit 2 FRT ch.1 zero detection interrupt MFT unit 2 FRT ch.2 zero detection interrupt...
Page 378 CHAPTER 8: Interrupts Number Interrupt Signal Name MFS ch.15 transmission interrupt Reserved I2S reception DSTC transfer request (Separated type) I2S transmission DSTC transfer request (Separated type) Hi-Speed Quad SPI reception DSTC transfer request (Separated type) Hi-Speed Quad SPI transmission DSTC transfer request (Separated type) Programmable CRC DSTC transfer request (Separated type) CAN-FD DSTC transfer request (Separated type) 224 to 255...
Page 379 CHAPTER 8: Interrupts Table 3-5 List of Interrupt Signals Input to DSTC (TYPE4-M4 Product) Number Interrupt Signal Name External pin interrupt ch.0 External pin interrupt ch.1 External pin interrupt ch.2 External pin interrupt ch.3 External pin interrupt ch.4 External pin interrupt ch.5 External pin interrupt ch.6 External pin interrupt ch.7 External pin interrupt ch.8...
Page 380 CHAPTER 8: Interrupts Number Interrupt Signal Name MFT unit 0 OCU ch.1 match detection interrupt MFT unit 0 OCU ch.2 match detection interrupt MFT unit 0 OCU ch.3 match detection interrupt MFT unit 0 OCU ch.4 match detection interrupt MFT unit 0 OCU ch.5 match detection interrupt 51 to 69 Reserved PPG ch.0 interrupt...
Page 381 CHAPTER 8: Interrupts Number Interrupt Signal Name I2S ch.1 transmission DSTC transfer request (Separated type) GDC HS-SPICNT reception DSTC transfer request (Separated type) GDC HS-SPICNT transmission DSTC transfer request (Separated type) Programmable CRC DSTC transfer request (Separated type) CAN-FD DSTC transfer request (Separated type) 128 to 255 Reserved FM4 Peripheral Manual, Doc.
Page 382: Registers
CHAPTER 8: Interrupts Registers This section explains the respective details of registers. Register List Abbreviation Register Name Reference DRQSEL DMAC DMA Request Selection Register IRQ003SEL Relocate Interrupt Selection Register IRQ004SEL Relocate Interrupt Selection Register IRQ005SEL Relocate Interrupt Selection Register IRQ006SEL Relocate Interrupt Selection Register IRQ007SEL Relocate Interrupt Selection Register...
Page 383 CHAPTER 8: Interrupts Abbreviation Register Name Reference IRQ036MON IRQ036 Batch Read Register IRQ037MON IRQ037 Batch Read Register 4.15 IRQ038MON IRQ038 Batch Read Register IRQ039MON IRQ039 Batch Read Register IRQ040MON IRQ040 Batch Read Register IRQ041MON IRQ041 Batch Read Register IRQ042MON IRQ042 Batch Read Register 4.16 IRQ043MON IRQ043 Batch Read Register...
Page 384 CHAPTER 8: Interrupts Abbreviation Register Name Reference IRQ083MON IRQ083 Batch Read Register IRQ084MON IRQ084 Batch Read Register IRQ085MON IRQ085 Batch Read Register IRQ086MON IRQ086 Batch Read Register 4.30 IRQ087MON IRQ087 Batch Read Register IRQ088MON IRQ088 Batch Read Register IRQ089MON IRQ089 Batch Read Register IRQ090MON IRQ090 Batch Read Register IRQ091MON...
Page 385: Dmac Dma Request Selection Register (Drqsel)
CHAPTER 8: Interrupts DMAC DMA Request Selection Register (DRQSEL) The DMA Request Selection Register (DRQSEL) enables using an interrupt signal from a peripheral function as a transfer request to the DMAC. Such interrupt signal can be transferred through the DMA transfer by the DMAC.
Page 386 CHAPTER 8: Interrupts Notes: − If an interrupt signal is selected as a transfer request to the DMAC, the read value of the bit in the interrupt request batch read register (IRQxxxMON, xxx = 000 to 127) corresponding to that interrupt signal is 0, regardless of whether the interrupt of that interrupt signal occurs.
Page 387: Relocate Interrupt Selection Register (Irqxxxsel)
CHAPTER 8: Interrupts Relocate Interrupt Selection Register (IRQxxxSEL) The Relocate Interrupt Selection Register (IRQxxxSEL) is a register selecting a relocate interrupt to be input to one of the exceptions between exception no. 19 and exception no. 26 (IRQ003 to IRQ010). There are eight Relocate Interrupt Selection Registers, IRQ003SEL to IRQ010SEL.
Page 388 CHAPTER 8: Interrupts [bit15:8] Reserved: Reserved bits A reserved bit reads 0. [bit7:0] SELIRQ[7:0] The SELIRQ[7:0] bits specify the IRQ no. of a peripheral interrupt to be relocated. For the IRQ no., see the column of IRQ no. in Table 3-1 and Table 3-2. Value Description 11 to 127...
Page 389: Exc02 Batch Read Register (Exc02Mon)
CHAPTER 8: Interrupts EXC02 Batch Read Register (EXC02MON) The EXC02 Batch Read Register (EXC02MON) can read out at once all interrupts (NMI and hardware watchdog interrupt) assigned to exception no. 2. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved HWINT Attribute...
Page 390: Irq000 Batch Read Register (Irq000Mon)
CHAPTER 8: Interrupts IRQ000 Batch Read Register (IRQ000MON) The IRQ000 Batch Read Register (IRQ000MON) can read out the interrupt (clock supervisor anomalous frequency detection interrupt) assigned to exception no. 16. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved FCSINT Attribute Initial value...
Page 391: Irq001 Batch Read Register (Irq001Mon)
CHAPTER 8: Interrupts IRQ001 Batch Read Register (IRQ001MON) The IRQ001 Batch Read Register (IRQ001MON) can read out the interrupt (software watchdog interrupt) assigned to exception no. 17. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved SWWDTINT Attribute Initial value 0000000 Register function [bit31:1] Reserved: Reserved bits...
Page 392: Irq002 Batch Read Register (Irq002Mon)
CHAPTER 8: Interrupts IRQ002 Batch Read Register (IRQ002MON) The IRQ002 Batch Read Register (IRQ002MON) can read out the interrupt (low-voltage detection interrupt) assigned to exception no. 18. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved LVDINT Attribute Initial value 0000000 Register function [bit31:1] Reserved: Reserved bits...
Page 393: Irq003/004/005/006/007/008/009/010 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts IRQ003/004/005/006/007/008/009/010 Batch Read Register (IRQxxxMON) The IRQ003MON to IRQMON010 Registers can read out at once the interrupts (relocate interrupts) assigned to exception no. 19 to no. 26 respectively. Register configuration Field Reserved Attribute Initial value 0x000000 Field IRQBIT[7:0] Attribute Initial value...
Page 394: Irq011/012/013/014/015/016/017/018/051/052/053/054/055/056/057/058 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts IRQ011/012/013/014/015/016/017/018/051/052/053/054/055/056/057/058 Batch Read Register (IRQxxxMON) The IRQ011MON to IRQ018MON Registers can read out at once the interrupts (external pin interrupt ch.0 to ch.7) assigned to exception no. 27 to no. 34 respectively. The IRQ051MON to IRQ058MON Registers can read out at once the interrupts (external pin interrupt ch.8 to ch.15) assigned to exception no.
Page 395: Irq019/020/096/097 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts IRQ019/020/096/097 Batch Read Register (IRQxxxMON) The IRQ019MON, IRQ020MON, IRQ096MON and IRQ097MON Registers can read out at once the interrupts (QPRC ch.0 to ch.3, GDC) assigned to exception no. 35, no. 36, no. 112 and no. 113 respectively. Register configuration Field Reserved...
Page 396 CHAPTER 8: Interrupts [bit5:0] QUDINT Value Description There is no PC match & RC match interrupt request of a QPRC channel corresponding to the IRQxxxMON Register. A PC match & RC match interrupt request of a QPRC channel corresponding to the IRQxxxMON Register has been made.
Page 397: Irq021/022/023 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.10 IRQ021/022/023 Batch Read Register (IRQxxxMON) The IRQ021MON to IRQ023MON Registers can read out at once the interrupts (WFG timer interrupts and DTIF interrupts of MFT unit 0 to MFT unit 2) assigned to exception no. 37 to no. 39 respectively. Register configuration Field Reserved...
Page 398: Irq024/028/032 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.11 IRQ024/028/032 Batch Read Register (IRQxxxMON) The IRQ024MON, IRQ028MON and IRQ032MON Registers can read out at once the interrupts (FRT ch.0 to ch.2 peak detection interrupts of MFT unit 0 to unit 2) assigned to exception no. 40, no. 44 and no. 48 respectively.
Page 399: Irq025/029/033 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.12 IRQ025/029/033 Batch Read Register (IRQxxxMON) The IRQ025MON, IRQ029MON and IRQ033MON Registers can read out at once the interrupts (FRT ch.0 to ch.2 zero detection interrupts of MFT unit 0 to unit 2) assigned to exception no. 41, no. 45 and no. 49 respectively.
Page 400: Irq026/030/034 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.13 IRQ026/030/034 Batch Read Register (IRQxxxMON) The IRQ026MON, IRQ030MON and IRQ034MON Registers can read out at once the interrupts (ICU ch.0 to ch.2 input edge detection interrupts of MFT unit 0 to unit 2) assigned to exception no. 42, no. 46 and no. 50 respectively.
Page 401: Irq027/031/035 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.14 IRQ027/031/035 Batch Read Register (IRQxxxMON) The IRQ027MON, IRQ031MON and IRQ053MON Registers can read out at once the interrupts (OCU ch.0 to ch.2 match detection interrupts of MFT unit 0 to unit 2) assigned to exception no. 43, no. 47 and no.
Page 402: Irq036/037/038 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.15 IRQ036/037/038 Batch Read Register (IRQxxxMON) The IRQ036MON to IRQ038MON Registers can read out at once the interrupts (PPG ch.0 to ch.20) assigned to exception no. 52 to no. 54 respectively. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved...
Page 403: Irq039/040/041/042/043/044/045/046/098/099/100/101 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.16 IRQ039/040/041/042/043/044/045/046/098/099/100/101 Batch Read Register (IRQxxxMON) The IRQ039MON to IRQ046MON Registers can read out at once the interrupts (interrupts of base timer ch.0 to ch.7) assigned to exception no. 55 to no. 62 respectively. The IRQ098MON to IRQ101MON Registers can read out at once the interrupts (interrupts of base timer ch.8 to ch.11, GDC) assigned to exception no.
Page 404 CHAPTER 8: Interrupts [bit1:0] BTINT Value Description There is no interrupt request of source 1 (IRQ1) of the base timer channel corresponding to the IRQxxxMON Register. An interrupt request of source 1 (IRQ1) of the base timer channel corresponding to the IRQxxxMON Register has been made. There is no interrupt request of source 0 (IRQ0) of the base timer channel corresponding to the IRQxxxMON Register.
Page 405: Irq047 Batch Read Register (Irq047Mon)
CHAPTER 8: Interrupts 4.17 IRQ047 Batch Read Register (IRQ047MON) The IRQ047 Batch Read Register (IRQ047MON) can read out at once the interrupts (dual timer interrupts) assigned to exception no. 63. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved TIMINT Attribute Initial value...
Page 406: Irq048 Batch Read Register (Irq048Mon)
CHAPTER 8: Interrupts 4.18 IRQ048 Batch Read Register (IRQ048MON) The IRQ048 Batch Read Register (IRQ048MON) can read out the interrupt (watch counter interrupt) assigned to exception no. 64. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved WCINT Attribute Initial value 0000000 Register function...
Page 407: Irq049 Batch Read Register (Irq049Mon)
CHAPTER 8: Interrupts 4.19 IRQ049 Batch Read Register (IRQ049MON) The IRQ049 Batch Read Register (IRQ049MON) can read out the interrupt (external bus output error interrupt, GDC) assigned to exception no. 65. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved GSDRAM BMEMCS...
Page 408: Irq050 Batch Read Register (Irq050Mon)
CHAPTER 8: Interrupts 4.20 IRQ050 Batch Read Register (IRQ050MON) The IRQ050 Batch Read Register (IRQ050MON) can read out the interrupt (RTC interrupt) assigned to exception no. 66. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved RTCINT Attribute Initial value 0000000 Register function [bit31:1] Reserved: Reserved bits...
Page 409: Irq059 Batch Read Register (Irq059Mon)
CHAPTER 8: Interrupts 4.21 IRQ059 Batch Read Register (IRQ059MON) The IRQ059 Batch Read Register (IRQ059MON) can read out at once the interrupts (main clock oscillation stabilization wait completion interrupt, sub clock oscillation stabilization wait completion interrupt, main PLL oscillation stabilization wait completion interrupt, and PLL of USB / Ethernet oscillation stabilization wait completion interrupt / PLL of I S oscillation stabilization wait completion interrupt / PLL of GDC oscillation stabilization wait completion interrupt ) assigned to exception no.
Page 410: Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.22 IRQ060/062/064/066/068/070/072/074/103/105/107/109/120/122/124/126 Batch Read Register (IRQxxxMON) The IRQ060MON, IRQ062MON, IRQ064MON and IRQ066MON Registers can read out at once the interrupts (MFS ch.0 to ch.3 reception interrupts) assigned to exception no. 76, no. 78, no.80 and no. 82 respectively.
Page 411 CHAPTER 8: Interrupts [bit7:1] Reserved: Reserved bits A reserved bit reads 0. [bit0] MFSRINT Value Description There is no reception interrupt request of the MFS channel corresponding to the IRQxxxMON Register. A reception interrupt request of the MFS channel corresponding to the IRQxxxMON Register has been made.
Page 412: Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.23 IRQ061/063/065/067/069/071/073/075/104/106/108/110/121/123/125/127 Batch Read Register (IRQxxxMON) The IRQ061MON, IRQ063MON, IRQ065MON and IRQ067MON Registers can read out at once the interrupts (transmission interrupts and status interrupts of MFS ch.0 to ch.3) assigned to exception no. 77, no. 79, no. 81 and no. 83 respectively. The IRQ069MON, IRQ071MON, IRQ073MON and IRQ075MON Registers can read out at once the interrupts (transmission interrupts and status interrupts of MFS ch.4 to ch.7) assigned to exception no.
Page 413 CHAPTER 8: Interrupts [bit7:2] Reserved: Reserved bits A reserved bit reads 0. [bit1:0] MFSINT Value Description There is no status interrupt request of the MFS channel corresponding to the IRQxxxMON Register. A status interrupt request of the MFS channel corresponding to the IRQxxxMON Register has been made.
Page 414: Irq076/077/111 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.24 IRQ076/077/111 Batch Read Register (IRQxxxMON) The IRQ076MON, IRQ077MON and IRQ111MON Registers can read out at once the interrupts (interrupts of A/D converter unit 0 to unit 2) assigned to exception no. 92, no. 93 and no. 127 respectively. Register configuration Field Reserved...
Page 415: Irq078/113 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.25 IRQ078/113 Batch Read Register (IRQxxxMON) The IRQ078MON and IRQ113MON Registers can read out at once the interrupts (DRQ interrupts of endpoint 0 to endpoint 5 of USB ch.0, and DRQ interrupts of endpoint 0 to endpoint 5 of USB ch.1, HDMI-CEC remote control reception ch.0 interrupt) assigned to exception no.
Page 416: Irq079/114 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.26 IRQ079/114 Batch Read Register (IRQxxxMON) The IRQ079MON and IRQ114MON Registers can read out at once the interrupts (interrupts of USB ch.0 and ch.1, HDMI-CEC remote control reception ch.1 interrupt) assigned to exception no. 95 and no. 130 respectively.
Page 417 CHAPTER 8: Interrupts [bit5:0] USB_INT Value Description There is no SOFIRQ / CMPIRQ interrupt request of the USB channel corresponding to the IRQxxxMON Register. An SOFIRQ / CMPIRQ interrupt request of the USB channel corresponding to the IRQxxxMON Register has been made. There is no DIRQ / URIRQ / RWKIRQ / CNNIRQ interrupt request of the USB channel corresponding to the IRQxxxMON Register.
Page 418: Irq080 Batch Read Register (Irq080Mon)
CHAPTER 8: Interrupts 4.27 IRQ080 Batch Read Register (IRQ080MON) The IRQ080MON Register can read out at once the interrupts (interrupts of CAN ch.0 ) assigned to exception no. 96 respectively. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved CANINT Attribute Initial value...
Page 419: Irq081 Batch Read Register (Irq081Mon)
CHAPTER 8: Interrupts 4.28 IRQ081 Batch Read Register (IRQ081MON) The IRQ081 Batch Read Register (IRQ081MON) can read at once the interrupts (interrupts of CAN ch.1 and CAN-FD) assigned to exception no. 97. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved CAN1INT...
Page 420: Irq082 Batch Read Register (Irq082Mon)
CHAPTER 8: Interrupts 4.29 IRQ082 Batch Read Register (IRQ082MON) The IRQ082 Batch Read Register (IRQ082MON) can read at once the interrupts (interrupts of Ethernet MAC) assigned to exception no. 98. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved MACLPI MACPMT MACSBD...
Page 421: Irq083/084/085/086/087/088/089/090 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.30 IRQ083/084/085/086/087/088/089/090 Batch Read Register (IRQxxxMON) The IRQ083MON to IRQMON090 Registers can read out at once the interrupts (interrupts of DMAC ch.0 to ch.7) assigned to exception no. 99 to no. 106 respectively. Register configuration Field Reserved Attribute Initial value 0x000000...
Page 422: Irq091 Batch Read Register (Irq091Mon)
CHAPTER 8: Interrupts 4.31 IRQ091 Batch Read Register (IRQ091MON) The IRQ091 Batch Read Register (IRQ091MON) can read out at once the interrupts (DSTC interrupts) assigned to exception no. 107. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved DSTCINT Attribute Initial value 000000...
Page 423: Irq092/093/094/095 Batch Read Register (Irqxxxmon)
CHAPTER 8: Interrupts 4.32 IRQ092/093/094/095 Batch Read Register (IRQxxxMON) The IRQ092MON to IRQ095MON Registers can read out at once the interrupts (external pin interrupt ch.16 to ch.31, GDC) assigned to exception no. 108 to no. 111 respectively. Register configuration Field Reserved GDCINT Attribute...
Page 424: Irq102 Batch Read Register (Irq102Mon)
CHAPTER 8: Interrupts 4.33 IRQ102 Batch Read Register (IRQ102MON) The IRQ102 Batch Read Register (IRQ102MON) can read out at once the interrupts (interrupts of base timer ch.12 to ch.15, GDC) assigned to exception no. 118. Register configuration Field Reserved GDCINT Attribute Initial value 00000000000000000000000...
Page 425: Irq112 Batch Read Register (Irq112Mon)
CHAPTER 8: Interrupts 4.34 IRQ112 Batch Read Register (IRQ112MON) The IRQ112MON Register can read out at once the interrupts (DSTC transfer end interrupts of I Hi-Speed Quad SPI, Programmable CRC, CAN-FD) assigned to exception no. 128. Register configuration Field Reserved GQSPIDINT Attribute Initial value...
Page 426 CHAPTER 8: Interrupts [bit4] PCRCDINT Value Description There is no DSTC transfer end interrupt of Programmable CRC. An interrupt request of DSTC transfer end interrupt of Programmable CRC has been made. [bit3:2] QSPIDINT Value Description There is no DSTC transfer end interrupt of Hi-Speed Quad SPI(data transmission).
Page 427: Irq115 Batch Read Register (Irq115Mon)
CHAPTER 8: Interrupts 4.35 IRQ115 Batch Read Register (IRQ115MON) The IRQ115MON Register can read out at once the interrupts (Hi-Speed Quad SPI interrupt) assigned to exception no. 131. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved QSPIINT Attribute Initial value 00000 Register function...
Page 428: Irq117 Batch Read Register (Irq117Mon)
CHAPTER 8: Interrupts 4.36 IRQ117 Batch Read Register (IRQ117MON) The IRQ117MON Register can read out at once the interrupts (interrupts of I S, Programmable CRC, Smart Card Interface) assigned to exception no. 133. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved...
Page 429: Irq118 Batch Read Register (Irq118Mon)
CHAPTER 8: Interrupts 4.37 IRQ118 Batch Read Register (IRQ118MON) The IRQ118 Batch Read Register (IRQ118MON) can read out at once the interrupts (SD I/F interrupts) assigned to exception no. 134. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved SDINT Attribute Initial value...
Page 430: Irq119 Batch Read Register (Irq119Mon)
CHAPTER 8: Interrupts 4.38 IRQ119 Batch Read Register (IRQ119MON) The IRQ119 Batch Read Register (IRQ119MON) can read out the interrupt (Flash I/F interrupt) assigned to exception no. 135. Register configuration Field Reserved Attribute Initial value 0x000000 Field Reserved FLINT Attribute Initial value 0000000 Register function...
Page 431: Irq116 Batch Read Register (Irq116Mon)
CHAPTER 8: Interrupts 4.39 IRQ116 Batch Read Register (IRQ116MON) The IRQ116MON Register is reserved register. Register configuration Field Reserved Attribute Initial value 0x00000000 Register function [bit31:0] Reserved: Reserved bits A reserved bit reads 0. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 432: Usb Ch.0 Odd Packet Size Dma Enable Register (Oddpks)
CHAPTER 8: Interrupts 4.40 USB ch.0 Odd Packet Size DMA Enable Register (ODDPKS) If data is transferred in the IN direction in USB ch.0 automatic transfer in which the DMAC is used, only in the last data in the last packet, the effective bit width is compulsorily converted into 1 byte (8 bits) before the data is written to a USB endpoint.
Page 433 CHAPTER 8: Interrupts [bit0] ODDPKS0 Value Description There is no conversion of the bit width for the DMA transfer by the DMAC. If the transfer destination address in the DMAC is USB.EP1DT, the bit width of the last transfer data is converted into one byte. Notes: −...
Page 434: Usb Ch.1 Odd Packet Size Dma Enable Register (Oddpks1)
CHAPTER 8: Interrupts 4.41 USB ch.1 Odd Packet Size DMA Enable Register (ODDPKS1) If data is transferred in the IN direction in USB ch.1 automatic transfer in which the DMAC is used, only in the last data in the last packet, the effective bit width is compulsorily converted into 1 byte (8 bits) before the data is written to a USB endpoint.
Page 435 CHAPTER 8: Interrupts [bit0] ODDPKS10 Value Description There is no conversion of the bit width for the DMA transfer by the DMAC. If the transfer destination address in the DMAC is USB.EP1DT, the bit width of the last transfer data is converted into one byte. Notes: −...
Page 436: Usage Precautions
CHAPTER 8: Interrupts Usage Precautions Note the following when using the interrupt controller. − The interrupt controller is notified of the interrupt request signals from peripheral functions in terms of level. When exiting the processing of an interrupt, always clear the interrupt request for that interrupt.
Page 437: Chapter 9: External Interrupt And Nmi Control Sections
CHAPTER 9: External Interrupt and NMI Control Sections This chapter explains the functions and operations of the external interrupt and NMI control sections. 1. Overview 2. Block Diagram 3. Operations and Setting Procedure Examples 4. Registers FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 438: Overview
CHAPTER 9: External Interrupt and NMI Control Sections Overview The external interrupt and NMI control sections have the following features. − Has up to 32 external interrupt input pins and one NMI input pin mounted. − Possible to select the H level, L level, rising edge, or falling edge to detect an external interrupt. Possible to select the both rising and falling edges in TYPE5-M4 and TYPE6-M4 products.
Page 439: Operations And Setting Procedure Examples
CHAPTER 9: External Interrupt and NMI Control Sections Operations and Setting Procedure Examples This section explains operations and setting procedure examples. 3.1. Operations of External Interrupt Control Section 3.2. Operations of NMI Control Section 3.3. Returning from the Timer, Stop, RTC Mode FM4 Peripheral Manual, Doc.
Page 440: Operations Of External Interrupt Control Section
CHAPTER 9: External Interrupt and NMI Control Sections Operations of External Interrupt Control Section This section shows the operations of the external interrupt control section. Overview of Operations in External Interrupt Control Section The external interrupt control section outputs an external interrupt request to the interrupt controller in the following procedure.
Page 441 CHAPTER 9: External Interrupt and NMI Control Sections Canceling an External Interrupt Request When the external interrupt detection condition is set to the H or L level, an interrupt factor is held in the External Interrupt Factor Register (EIRR) even if an external interrupt request input (INTxx) is canceled. Therefore, an external interrupt request (INTIRQxx) remains output to the interrupt controller.
Page 442: Operations Of Nmi Control Section
CHAPTER 9: External Interrupt and NMI Control Sections Operations of NMI Control Section This section shows the operations of the NMI control section. Overview of NMI Control Section The NMI control section outputs an NMI interrupt request (NMIIRQ) to the CPU if the edge or level is detected from the signal input to the NMI input pin (NMIX).
Page 443: Returning From Timer Or Stop Mode
CHAPTER 9: External Interrupt and NMI Control Sections Returning from the Timer, Stop, RTC Mode This section shows a return from the Timer, Stop, RTC mode. Overview An external interrupt and NMI requests can be used to return from the Timer, Stop, RTC mode. In timer or stop mode, the signal first input to pin INTxx or NMIX is input asynchronously, and the device can return from these modes to RUN mode.
Page 444: Registers
CHAPTER 9: External Interrupt and NMI Control Sections Registers This section provides a list of registers. Register List The following shows a list of registers in the external interrupt and NMI control sections. Table 4-1 Registers in External Interrupt and NMI Control Sections Abbreviation Register Name Reference...
Page 445: External Interrupt Enable Register (Enir)
CHAPTER 9: External Interrupt and NMI Control Sections External Interrupt Enable Register (ENIR) The ENIR register is used to control masking an external interrupt request output. Register configuration Field EN[31:16] Attribute Initial value 0x0000 Field EN[15:0] Attribute Initial value 0x0000 Register functions [bit31:0] EN31 to EN0: External interrupt enable bits EN31 to EN0 bits correspond to pins INT31 to INT00.
Page 446: External Interrupt Factor Register (Eirr)
CHAPTER 9: External Interrupt and NMI Control Sections External Interrupt Factor Register (EIRR) The EIRR register indicates that an external interrupt request is detected. Register configuration Field ER[31:16] Attribute Initial value 0xXXXX Field ER[15:0] Attribute Initial value 0xXXXX Register functions [bit31:0] ER31 to ER0: External interrupt request detection bits ER31 to ER0 bits correspond to pins INT31 to INT00.
Page 447: External Interrupt Factor Clear Register (Eicl)
CHAPTER 9: External Interrupt and NMI Control Sections External Interrupt Factor Clear Register (EICL) The EICL register is used to clear the held interrupt factor. Register configuration Field ECL[31:16] Attribute Initial value 0xFFFF Field ECL[15:0] Attribute Initial value 0xFFFF Register functions [bit31:0] ECL31 to ECL0: External interrupt factor clear bits ECL31 to ECL0 bits correspond to pins INT31 to INT00.
Page 448: External Interrupt Factor Level Register (Elvr)
CHAPTER 9: External Interrupt and NMI Control Sections External Interrupt Factor Level Register (ELVR) The ELVR is used to select the level or edge of the signal detected as an external interrupt request. Register configuration Field LB15 LA15 LB14 LA14 LB13 LA13 LB12 LA12 LB11 LA11 LB10 LA10 Attribute Initial value Field...
Page 449: External Interrupt Factor Level Register 1 (Elvr1)
CHAPTER 9: External Interrupt and NMI Control Sections External Interrupt Factor Level Register 1 (ELVR1) The ELVR1 is used to select the level or edge of the signal detected as an external interrupt request. Register configuration Field LB31 LA31 LB30 LA30 LB29 LA29 LB28 LA28 LB27 LA27 LB26 LA26 LB25 LA25 LB24 LA24 Attribute Initial value Field...
Page 450: Non Maskable Interrupt Factor Register (Nmirr)
CHAPTER 9: External Interrupt and NMI Control Sections Non Maskable Interrupt Factor Register (NMIRR) The NMIRR Register indicates that a non maskable interrupt (NMI) request is detected. Register configuration Field Reserved Attribute Initial value Register functions [bit15:1] Reserved: Reserved bits The read value is undefined.
Page 451: Non Maskable Interrupt Factor Clear Register (Nmicl)
CHAPTER 9: External Interrupt and NMI Control Sections Non Maskable Interrupt Factor Clear Register (NMICL) The NMICL register is used to clear the held interrupt factor. Register configuration Field Reserved Attribute Initial value Register functions [bit15:1] Reserved: Reserved bits The read value is undefined. They have no effect in write mode.
Page 452: External Interrupt Factor Level Register 2 (Elvr2)
CHAPTER 9: External Interrupt and NMI Control Sections External Interrupt Factor Level Register 2 (ELVR2) The ELVR2 is used to select the both rising and falling edges of the signal detected as an external interrupt request. This register is equipped in TYPE5-M4 and TYPe6-M4 products. Register configuration Field LC31 LC30 LC29 LC28 LC27 LC26 LC25 LC24 LC23 LC22 LC21 LC20 LC19 LC18 LC17 LC16...
Page 453: Chapter 10: Dmac
CHAPTER 10: DMAC This chapter explains DMAC. 1. Overview of DMAC 2. Configuration of DMAC 3. Functions and Operations of DMAC 4. DMAC Control 5. Registers of DMAC 6. Usage Precautions FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 454: Overview Of Dmac
CHAPTER 10: DMAC Overview of DMAC DMAC (Direct Memory Access Controller) is a function block that transfers data at high speed without CPU. Using DMAC improves the system performance. Overview of DMAC − DMAC has its own bus which is independent from the CPU bus; therefore, it allows for transfer operation even when the CPU bus is accessed.
Page 455: Configuration Of Dmac
CHAPTER 10: DMAC Configuration of DMAC This section explains the system configuration of DMAC and the I/O signals of DMAC. 2.1. DMAC and System Configuration 2.2. I/O Signals of DMAC FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 456: Dmac And System Configuration
CHAPTER 10: DMAC DMAC and System Configuration This section explains DMAC and its system configuration. Block Diagram Figure 2-1 shows a diagram of DMAC and its system configuration. Figure 2-1 Block Diagram of DMAC and System Configuration DMAC cｈ.０ cｈ.1 cｈ.2 IDREQ[31:0] cｈ.3...
Page 457 CHAPTER 10: DMAC Explanation of Block Diagram  DMAC DMAC is in maximum 8-ch configuration. Each channel performs independent transfer. The priority controller controls the transfer operations of these channels, when there is a conflict among them.  Connection to the system The diagram of the system configuration in the figure has been simplified for explanation purposes.
Page 458: I/O Signals Of Dmac
CHAPTER 10: DMAC I/O Signals of DMAC This section explains the I/O signals of DMAC. Transfer Request Signals to be Input to DMAC Table 2-1 shows a list of the transfer request signals to be input to DMAC and the interrupt signals from the corresponding Peripherals.
Page 459 CHAPTER 10: DMAC Interrupt Signals Output from DMAC Table 2-2 shows a list of the interrupt signals output from DMAC. Table 2-2 List of Interrupt Signals from DMAC Name of Interrupt Signal Interrupt Factor Register Interrupt Enable Register Interrupt Type DMACB0.CI ch.0 successful transfer completion interrupt DIRQ0...
Page 460: Functions And Operations Of Dmac
CHAPTER 10: DMAC Functions and Operations of DMAC This section explains the operations of DMAC in each transfer mode. 3.1. Software-Block Transfer 3.2. Software-Burst Transfer 3.3. Hardware-Demand Transfer 3.4. Hardware-Block Transfer & Burst Transfer 3.5. Channel Priority Control FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 461: Software-Block Transfer
CHAPTER 10: DMAC Software-Block Transfer This section explains Software-Block transfer. Figure 3-1 shows an example of the operation of Software-Block transfer. In this example, the following settings apply. − Transfer mode: Software request Block transfer (ST=1, IS[5:0]=000000, MS=00) − Transfer source start address: SA(DMACSA=SA) −...
Page 462 CHAPTER 10: DMAC DMAC performs the following operation, when the transfer content is set from CPU and then the start of the transfer is instructed. − Due to the specification of the transfer data width, each transfer is performed by half-word (16bits). −...
Page 463: Software-Burst Transfer
CHAPTER 10: DMAC Software-Burst Transfer This section explains Software-Burst transfer. Figure 3-2 shows an example of the operation of Software-Burst transfer. In this example, the following settings apply. − Transfer mode: Software request Burst transfer (ST=1, IS[5:0]=000000, MS=01) − Transfer source start address: SA(DMACSA=SA) −...
Page 464: Hardware-Demand Transfer
CHAPTER 10: DMAC Hardware-Demand Transfer This section explains Hardware-Demand transfer. Hardware-Demand transfer is used when performing DMA transfer by the transfer request signal from the Peripherals of USB, MFS and ADC. Hardware-Demand transfer is a method used to receive the transfer request signal from Peripherals on a signal level.
Page 465: Hardware-Block Transfer & Burst Transfer
CHAPTER 10: DMAC Hardware-Block Transfer & Burst Transfer This section explains Hardware-Block transfer and Burst transfer. Hardware-Block transfer or Hardware-Burst transfer is used when performing DMA transfer by the transfer request signal from the Peripheral of the base timer or external interrupt. Hardware-Block transfer and Hardware-Burst transfer are methods used to receive the transfer request signal at the rising edge of the signal.
Page 466 CHAPTER 10: DMAC Figure 3-5 shows an example of the operation of Hardware-Burst transfer. In this example, the following settings apply. The settings of the addresses of the transfer source and transfer destination as well as the transfer data width are omitted. −...
Page 467: Channel Priority Control
CHAPTER 10: DMAC Channel Priority Control This section explains the channel priority control. Channel Priority Control If multiple channels have transfer requests, DMAC switches the channel subject to the transfer among them at the timing of the Transfer Gap of each channel. At this point, the next channel to which the transfer will be performed is determined according to the priority control.
Page 468: Dmac Control
CHAPTER 10: DMAC DMAC Control This section explains DMAC control methods in details. 4.1. Overview of DMAC Control 4.2. DMAC Operation and Control Procedure for Software Transfer 4.3. DMAC Operation and Control Procedure for Hardware (EM=0) Transfer 4.4. DMAC Operation and Control Procedure for Hardware (EM=1) Transfer FM4 Peripheral Manual, Doc.
Page 469: Overview Of Dmac Control
CHAPTER 10: DMAC Overview of DMAC Control This section provides an overview of DMAC control. The control register of each channel of DMAC has EB (individual-channel operation enable bit) and PB (individual-channel pause bit). By manipulating these bits, the start of DMA transfer operation (operation enabled), the forced termination of transfer operation (operation disabled) and the pause of transfer operation can be controlled by channel.
Page 470: Dmac Operation And Control Procedure For Software Transfer
CHAPTER 10: DMAC DMAC Operation and Control Procedure for Software Transfer This section explains DMAC operation and control procedure for software transfer. Figure 4-1 Transitional Diagram of Software DMA Transfer State Reset Disable DE=0 or EB=0 or DH!=0000 or PB=1 1 , 7 , 1 1 initial : SS=000 after stop : SS=code...
Page 471 CHAPTER 10: DMAC Description of Each State  Disable state In this state, the transfer of the channel to be controlled is prohibited. Channels in this state do nothing and wait for instruction from CPU. At the system reset, DE=0, EB=0, DH=0000 and PB=0 apply to this Disable state.
Page 472 CHAPTER 10: DMAC Figure 4-2 Example of Operation of Software-Block Transfer Example of Block transfer mode (software DMA operation) start / normal end / error stop / force stop Example 1 :normal end DMA status Disable Transfer Disable Transfer action TC(no reload) 101 (normal end) Start request from CPU...
Page 473 CHAPTER 10: DMAC 6. Transfer state, Pause state => Disable state / Forced transfer stop If an instruction to disable individual-channel operation or an instruction to disable all-channel operation is issued from CPU to a channel in Transfer state or Pause state, the transfer operation of that channel can be forced to stop (for the operation when an instruction to disable operation is issued to a channel in Disable state, see Step 11 in the software procedure).
Page 474 CHAPTER 10: DMAC Even if instructed from CPU, the transfer may not be put on pause, and instead, it may be successfully completed due to factors such as transfer mode (Burst/Block/Demand) and transfer status (the number of transfers performed, the timing of instruction to put the operation on pause). Also, if a transfer error occurs before the transfer stops, error stop applies to the transfer.
Page 475 CHAPTER 10: DMAC At the beginning, three channels, namely ch.0, ch.1 and ch.2, perform their transfer operations in Block transfer mode. ch.2 successfully completes its transfer, moves to Disable state and sets SS[2:0]=101. Then, ch.0 and ch.1 perform transfers alternately. If an instruction to put all-channel operation on pause is issued from CPU at this point, the following operation applies.
Page 476 CHAPTER 10: DMAC A certain channel is performing transfer operation. CPU issues an instruction to put individual-channel operation on pause to that channel. The instruction is issued after the transfer is completed and it moves to Disable state (DE=1, DH=0000, EB=0, PB=0). This phenomenon can occur, because the channel currently performing transfer operation changes its state outside CPU’s intention.
Page 477: Dmac Operation And Control Procedure For Hardware (Em=0) Transfer
CHAPTER 10: DMAC DMAC Operation and Control Procedure for Hardware (EM=0) Transfer This section explains DMAC operation and control procedure for hardware (EM=0) transfer. Figure 4-5 Transitional Diagram of Hardware (EM=0) Transfer State Reset Disable DE=0 or EB=0 or 1 , 9 , 1 3 DH!=0000 or PB=1 initial : SS=000 after stop : SS=code...
Page 478 CHAPTER 10: DMAC Description of Each State  Disable state See Explanation of Control Procedure in "4.2 DMAC Operation and Control Procedure for Software Transfer".  Wait-1st-trigger state In this state, the channel to be controlled is enabled to perform transfer. A channel in this state waits for the first transfer request from a Peripheral to be asserted.
Page 479 CHAPTER 10: DMAC excessive transfer request signals are not cleared from DMAC, the asserted state continues (Example 2 in Figure 4-6). If the number of transfer requests generated from the Peripheral is smaller than DMAC’s setting for the number of transfers, DMAC waits for the remaining number of transfer requests in Transfer state (Example 3 in Figure 4-6).
Page 480 CHAPTER 10: DMAC Figure 4-7 shows a case of Block transfer. In the case of Block transfer, the number of transfer requests required to complete the transfer is TC+1. Unless the number of transfer requests goes over or below the requirement, CPU does not have to intervene (Example 1 in Figure 4-7). Figure 4-7 Operation of Hardware-Block Transfer Block transfer mode (hardware DMA operation) Example1: (TC+1)== Transfer request from Peripheral...
Page 481 CHAPTER 10: DMAC excessive transfer request signals are not cleared from DMAC, the asserted state continues, In this case, deassert the transfer request signal from CPU (Example 2 in Figure 4-7). If the number of transfer requests generated from the Peripheral is smaller than DMAC’s setting for the number of transfers, DMAC waits for the remaining number of transfer requests in Transfer state (Example 3 in Figure 4-7).
Page 482 CHAPTER 10: DMAC When an instruction to cancel the pause is issued while it is in Pause state, it returns to Transfer state. If the transfer request signal was asserted in the previous Pause state, the operation to follow varies as shown below, depending on the transfer mode. In the case of Demand transfer mode, the transfer request signal remains asserted from the Pause state.
Page 483 CHAPTER 10: DMAC 13. Operation in Disable state and Wait-1st-trigger state See Step 11 in the software transfer procedure. If the transfer request signal is not asserted to the channel in Disable state, the specifications of the transfer content can be changed freely (rewriting to registers DMACSA, DMACDA, DMACA[29:0], and DMACB).
Page 484 CHAPTER 10: DMAC Figure 4-11 Operation of Demand Transfer in Disable State Case of no transfer request be asserted during disable state Wait 1st DMA status Disable Transfer trigger Transfer request Transfer action Case of transfer request be asserted during disable state Wait 1st DMA status Disable...
Page 485 CHAPTER 10: DMAC − Additional Matter 1 See Additional Matter 1 in the software transfer procedure. In the case of hardware transfer, always write 0 to ST. − Additional Matter 2 See Additional Matter 2 in the software transfer procedure. −...
Page 486: Dmac Operation And Control Procedure For Hardware (Em=1) Transfer
CHAPTER 10: DMAC DMAC Operation and Control Procedure for Hardware (EM=1) Transfer This section explains DMAC operation and control procedure for hardware (EM=1) transfer. Figure 4-13 Transitional Diagram of Hardware (EM=1) Transfer State Reset Disable DE=0 or EB=0 or 1 , 1 1 , 1 5 DH!=0000 or PB=1 initial : SS=000 after stop : SS=code...
Page 487 CHAPTER 10: DMAC Description of Each State  Disable state See the hardware transfer (EM=0) procedure.  Wait-1st-trigger state See the hardware transfer (EM=0) procedure.  Transfer state In this state, the channel to be controlled has received the first transfer request from the Peripheral.
Page 488 CHAPTER 10: DMAC 8. Wait-1st-trigger state / Post-transfer process In the case of EM=1, EB is not cleared upon the completion of the transfer. (DE=1, EB=1, DH=0000, PB=0) is set and it moves to Wait-1st-trigger state. When the next transfer request is generated from the Peripheral, therefore, the next transfer starts without an instruction from CPU.
Page 489 CHAPTER 10: DMAC − Additional Matter 1 See Additional Matter 1 in the hardware transfer (EM=0) procedure. − Additional Matter 2 See Additional Matter 2 in the hardware transfer (EM=0) procedure. In the case of EM=1, Additional Matter 2 does not apply, because EB is not cleared during the transfer operation.
Page 490: Registers Of Dmac
CHAPTER 10: DMAC Registers of DMAC This section explains each register function of DMAC. 5.1. List of Registers 5.2. Entire DMAC Configuration Register (DMACR) 5.3. Configuration A Register (DMACA) 5.4. Configuration B Register (DMACB) 5.5. Transfer Source Address Register (DMACSA) 5.6.
Page 491: List Of Registers
CHAPTER 10: DMAC List of Registers Table 5-1 shows a list of DMAC control registers. Table 5-1 List of DMAC Control Registers Abbreviation Ch. Controlled Register Name Reference DMACR Entire DMAC configuration register DMACA0 Configuration A register DMACB0 Configuration B register ch.0 DMACSA0 Transfer source address register...
Page 492: Entire Dmac Configuration Register (Dmacr)
CHAPTER 10: DMAC Entire DMAC Configuration Register (DMACR) This section explains entire DMAC configuration register (DMACR). Field Reserved DH[3:0] Reserved Attribute Initial Value 0000 Field Reserved Attribute Initial Value [bit31] DE : DMA Enable (all-channel operation enable bit) This bit controls the enabling and disabling of transfer operations for all of the channels. When "1"...
Page 493 CHAPTER 10: DMAC [bit29] Reserved: Reserved bit "0" is read out from this bit. When writing this bit, set it to "0". [bit28] PR : Priority Rotation This bit controls the order of transfer priority among channels. When this bit is set to "0", the priority order is fixed for all of the channels. When this bit is set to "1", the priority order is determined in a rotation method for all of the channels.
Page 494: Configuration A Register (Dmaca)
CHAPTER 10: DMAC Configuration A Register (DMACA) This section explains configuration A register (DMACA). Field IS[5:0] Reserved BC[3:0] Attribute Initial Value 000000 0000 Field TC[15:0] Attribute Initial Value 0x0000 [bit31] EB : Enable bit (individual-channel operation enable bit) This bit controls the enabling and disabling of the transfer operation of an individual channel. When this bit is set to "1", the relevant channel is enabled to operate and waits for a trigger to start its transfer operation (the DMACR:DE must be set to "1").
Page 495 CHAPTER 10: DMAC [bit29] ST : Software Trigger This bit is used to generate a software transfer request for an individual channel. When this bit is set to "1", a trigger is generated by the software transfer request and the relevant channel starts its transfer.
Page 496 CHAPTER 10: DMAC bit28:23 Function 111011 IDREQ[27] 111100 IDREQ[28] 111101 IDREQ[29] 111110 IDREQ[30] 111111 IDREQ[31] Setting other than Setting is prohibited. above [bit22:20] Reserved: Reserved bits "0" is read out from these bits. When writing these bits, set them to "0". [bit19:16] BC[3:0] : Block Count These bits specify the number of blocks for Block/Burst transfer.
Page 497: Configuration B Register (Dmacb)
CHAPTER 10: DMAC Configuration B Register (DMACB) This section explains configuration B register (DMACB). Field Reserved MS[1:0] TW[1:0] SS[2:0] Attribute Initial Value Field Reserved Attribute Initial Value 000000000000000 [bit31:30] Reserved: Reserved bits "0" is read out from these bits. When writing these bits, set them to "0". [bit29:28] MS[1:0] : Mode Select These bits select the transfer mode.
Page 498 CHAPTER 10: DMAC [bit23] RC : Reload Count (BC/TC reload) This bit controls the reload function of BC[3:0] and TC[15:0]. When this bit is set to "1", the value set when the transfer started is reloaded to BC[3:0] and TC[15:0] upon completion of the transfer.
Page 499 CHAPTER 10: DMAC [bit18:16] SS[2:0] : Stop Status (stop status notification) These bits represent a code that indicates the stop status or completion status of a transfer. The following table shows the available codes. If a successful transfer completion interrupt or unsuccessful transfer completion interrupt is issued, the interrupt signal is deasserted by writing "000"...
Page 500: Transfer Source Address Register (Dmacsa)
CHAPTER 10: DMAC Transfer Source Address Register (DMACSA) This section explains transfer source address register (DMACSA). Field DMACSA[31:16] Attribute Initial Value 0x0000 Field DMACSA[15:0] Attribute Initial Value 0x0000 [bit31:0] DMACSA[31:0] : DMAC Source Address These bits specify the transfer start address of the transfer source. It is not possible to set unaligned address to transfer data width (TW[1:0]).
Page 501: Transfer Destination Address Register (Dmacda)
CHAPTER 10: DMAC Transfer Destination Address Register (DMACDA) This section explains transfer destination address register (DMACDA). Field DMACDA[31:16] Attribute Initial Value 0x0000 Field DMACDA[15:0] Attribute Initial Value 0x0000 [bit31:0] DMACDA[31:0] : DMAC Destination Address These bits specify the transfer start address of the transfer destination. It is not possible to set unaligned address to transfer data width (TW[1:0]).
Page 502: Usage Precautions
CHAPTER 10: DMAC Usage Precautions This section explains the precautions on using DMAC. Precautions on Register Setting When setting DMAC register, please note the following matters. − The DMACR, DMACA, DMACB, DMACSA and DMACDA registers can be accessed by byte, half-word and word.
Page 503: Chapter 11: Dstc
CHAPTER 11: DSTC This chapter explains details of the DSTC (Descriptor System data Transfer Controller). 1. Overview of DSTC 2. DSTC Operations Overview and DSTC System Configuration 3. Functions and Operations of DSTC 4. Examples of DSTC Operations and Control 5.
Page 504: Overview Of Dstc
CHAPTER 11: DSTC Overview of DSTC This section provides an overview of the DSTC (Descriptor System data Transfer Controller). Overview The DSTC (Descriptor System data Transfer Controller), like the DMAC, is a function block that can transfer data at high speed bypassing the CPU. Using the Descriptor (to be called DES later in this document) System Method, it directly accesses memory or a peripheral device according to the content specified in a DES created on the memory, and executes a data transfer operation.
Page 505: Dstc Operations Overview And Dstc System Configuration
CHAPTER 11: DSTC DSTC Operations Overview and DSTC System Configuration This section provides an overview of operations of the DSTC and explains the DSTC system configuration. Operations Overview of DSTC DES System The DSTC executes a transfer operation according to the content specified in a DES built on the memory by the CPU.
Page 506 CHAPTER 11: DSTC In the following sections, "Start Trigger" represents all the above start triggers, SW Start, HW Start and Chain Start. Figure 2-1 DES System Method Configuration Diagram Memory DESTP 2. Initialize DES area 1. Write DESTP, HW-DESP[n] DESP 3.
Page 507: Dstc And System Configuration
CHAPTER 11: DSTC DSTC and System Configuration Figure 2-2 shows the block diagram illustrating the DSTC and system configuration. Figure 2-2 Block Diagram of DSTC and System Configuration DSTC SWINT, ERINT Output: Software transfer interrupt Transfer error interrupt DREQENB[255:0] Output: DMA request enalbe Output: HWINT[255:0]...
Page 508 CHAPTER 11: DSTC DREQENB[n] Register and Connection with DREQ[n] Signal and HWINT[n] Signal The DSTC supports up to 256 hardware transfer request signal inputs. The interrupt signal from a peripheral supporting DSTC hardware transfer is connected to the DSTC. The DSTC can start a transfer operation with the interrupt signal from a peripheral as a DMA transfer request signal (DREQ[255:0]).
Page 509 CHAPTER 11: DSTC For details of peripheral types, refer to the list of interrupts and the list of interrupt signals input to DSTC in the Interrupts chapter. Connection to Hardware Transfer Request Clear Signal Among peripherals supporting the hardware transfer, there are some for which a transfer request signal (interrupt signal) has to be cleared after a transfer has ended.
Page 510: Functions And Operations Of Dstc
CHAPTER 11: DSTC Functions and Operations of DSTC This section explains operations of the DSTC. 3.1. Settings of DES 3.2. Control Functions of DSTC 3.3. Operation Flows of DSTC FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 511: Settings Of Des
CHAPTER 11: DSTC Settings of DES This section explains setting details of the DES and operations of the DSTC. Specifying Transfer Data Size 3.1.1 TW, IRM, IIN, ORM The DSTC transfers data of the data width specified in TW in DES0 in a single transfer. There is a transfer number counter in the DSTC.
Page 512: Setting Transfer Addresses
CHAPTER 11: DSTC Setting Transfer Addresses 3.1.2 SA, DA, SAC[2:0], DAC[2:0] Set the start address of the transfer source area (SA) in DES2 and the start address of the transfer destination area (DA) in DES3. Align each transfer address to a specified data width (TW). The DSTC cannot execute an unaligned transfer.
Page 513 CHAPTER 11: DSTC Figure 3-1 Operations of Transfer Number Counter and Transfer Address Initial value in DES Start of transfer Update value from DSTC End of transfer Counter outer reload (ORL[0]=1) Outer loop counter remain value (ORM) Inner loop counter initial value (IIN) Inner loop counter remain value (IRM) 4 3 2 1 4 3 2 1...
Page 514: Specifying Outerreload
CHAPTER 11: DSTC Specifying OuterReload 3.1.3 ORL[2:0] Table 3-3 shows the method of specifying the transfer number counter and transfer address for OuterReload. As shown in Figure 3-1, after IIN×ORM times of transfer have ended, for the next transfer, the transfer number counter (ORM/IRM/IIN) of DES1, the transfer source address (SA) of DES2 and the transfer destination address (DA) of DES3 can be reset (OuterReload) to their respective values at the start of the transfer.
Page 515 CHAPTER 11: DSTC DES Values after Transfer End The DES area can be saved when the OuterReload function is not used. If InnerReload is enabled for the transfer address, OuterReload does not need to be enabled for the transfer address because the values at the start of the transfer are stored in the DES.
Page 516 CHAPTER 11: DSTC The values of DES3 (transfer destination address) after the end of the transfer are updated according to the values of MODE, DAC[2:0] and ORL[2] of DES0 at the start of the transfer as shown in Table 3-7. "X" in Table 3-7 indicates that value has no effect on operation.
Page 517: Setting Chain Start And Transfer End Notification
CHAPTER 11: DSTC Setting Chain Start and Transfer End Interrupt Notification 3.1.4 CHRS[5:0], CHLK The DSTC executes transfers for the number of times specified in each DES (IIN times if MODE = 0, 1 time if MODE = 1) after receiving a Start Trigger. After executing transfers, the DSTC the next process according to the value of CHRS[5:0] in DES0.
Page 518 CHAPTER 11: DSTC Operations of Chain Start Using the Chain Start enables making a Start Trigger for different transfers set in multiple DES. Figure 3-3 illustrates how the DES reference and transfer operation are executed when the DSTC executes a Chain Start on the next DES. 1st-DES is located at the position of DESP0. The size of 1st-DES is defined by the value of ORL[2:0] of 1st-DES.
Page 519: Other Des Settings
CHAPTER 11: DSTC Other DES Settings 3.1.5 DV[1:0] The DSTC refers to the DES area and updates it while executing a transfer operation. If the CPU updates a DES area that the DSTC is using, the DSTC may executes an illegal transfer operation, which is not set in a program.
Page 520 CHAPTER 11: DSTC If details of a transfer defined in a DES are fixed, and the CPU has to reuse details of the DES, setting DV to"11" grants the ownership of the DES to the DSTC. In this situation, since the DES close process is not executed after the transfer, the process of CPU transferring the ownership of the DES again can be omitted.
Page 521 CHAPTER 11: DSTC ACK[1:0] ACK[1:0] (Acknowledge) sets the value for adjusting the timing of DSTC outputting the DMA transfer request acknowledge signal to a peripheral device when the HW transfer is used. If the HW transfer is used, set ACK to 01 for a DES to be directly started by the HW Start from a peripheral device.
Page 522: Control Functions Of Dstc
CHAPTER 11: DSTC Control Functions of DSTC This section explains the control functions of the DSTC. DSTC internal Block Diagram 3.2.1 Figure 3-5 illustrates the connection between control blocks and control registers (shaded rectangles) in the DSTC that can be accessed from the CPU. The CPU starts DSTC transfer and controls end notifications via accesses to control registers.
Page 523: Control Of Hw Transfer
CHAPTER 11: DSTC Control of HW Transfer 3.2.4 If a peripheral makes a transfer request (assertion of DREQ[n]), the DSTC starts the HW Transfer. The DSTC controls the HW Transfer on a transfer channel using the following registers whose number corresponds to the number of transfer channels.
Page 524: Arbitration Of Transfer Requests
CHAPTER 11: DSTC Arbitration of Transfer Requests 3.2.5 The DSTC arbitrates start triggers if multiple HW Start requests conflict with an SW Start request, and executes transfers sequentially. The arbitration of start requests are processed by two blocks, Arbiter 1 and Arbiter 2, shown in Figure 3-5.
Page 525 CHAPTER 11: DSTC 1 selects one from HW[A] transfer and HW[B] transfer according to the preceding rotation status. The following description assumes that Arbiter 1 has selected HW[A] transfer. Arbiter 2 arbitrates the conflict between HW[A] transfer and SW transfer. Arbiter 2 selects one from HW[A] transfer and SW transfer according to the preceding rotation status.
Page 526: Read Skip Buffer Function
CHAPTER 11: DSTC Read Skip Buffer Function 3.2.6 The transfer engine of the DSTC refers to the transfer information of the DES on the memory while executing a transfer. If all transfers do not end in one Start Trigger, the DSTC writes back to each DES the number of executed transfers of a DES and transfer addresses.
Page 527: Moners Register
CHAPTER 11: DSTC MONERS Register 3.2.8 If a transfer error occurs, details of that error are recorded in the MONERS Register. Table 3-12 shows details the MONERS Register displays. Table 3-12 Details of MONERS Area Name Name Details Indicate details of an error that has occurred. 000: No error has occurred.
Page 528 CHAPTER 11: DSTC − One of the two bits of the reserved area of DES0 is 1. (abnormal specified value) − TW[1:0]==11 (abnormal specified value) − CHRS[5:4]==11 (abnormal specified value) − (CHRS[5]==0) &&(CHRS[3]==0)&&(CHRS[1]==0) &&(CHLK ==1) (abnormal Chain setting) − (MODE==0) && (CHRS[1:0] != 00) (abnormal setting) −...
Page 529: Standby Function
CHAPTER 11: DSTC information (EST ≠ 000), if a transfer caused by another transfer request ends due to an error, the DSTC sets the DER (double error) bit to 1. The DER bit is a bit that indicates a double error has occurred. As for the second error, the DSTC notifies the CPU of only its occurrence.
Page 530 CHAPTER 11: DSTC In the transition state 2, if the DSTC does not execute any transfer, it immediately transits to the standby state. But, if the DSTC executes a transfer, it transits to the standby state after that transfer has been compulsorily ended.
Page 531: Operation Flows Of Dstc
CHAPTER 11: DSTC Operation Flows of DSTC This section explains the operation of the DSTC with flow charts. SW Transfer Flow 3.3.1 The operations the DSTC executes after receiving an SW Start Trigger from the CPU are explained below. Figure 3-8 shows a flow chart of the operations of the DSTC. Numbers in the figure correspond to those used in the explanation after the figure.
Page 532 CHAPTER 11: DSTC #1 Start the SW Start transfer from a write access to the SWTR Register from the CPU. #2 If the SWTR Register, the MONERS Register and the CMD Register are (SWTR:SWREQ==0)&&(MONERS:ESTOP==0)&&(CMD==00), the DSTC proceeds to #3. Otherwise the DSTC proceeds to #26.
Page 533 CHAPTER 11: DSTC #21 The DSTC ends the transfer caused by the SW Start trigger in #1. The DSTC waits for either a new Start Trigger or a succeeding Start Trigger. The DESP of the DES whose transfer has ended is kept in SWTR:SWDESP.
Page 534: Hw Transfer Flow
CHAPTER 11: DSTC HW Transfer Flow 3.3.2 The operations the DSTC executes after receiving an HW Start Trigger from a peripheral are explained below. Figure 3-9 shows a flow chart of the operations of the DSTC. Numbers in the figure correspond to those used in the explanation after the figure.
Page 535 CHAPTER 11: DSTC #1 The DSTC starts the HW Transfer from the assertion of the DREQ[n] signal from a peripheral. #2 If the DREQENB[n] Register, the DQMSK[n] Register and the MONERS Register are (DREQENB[n]==1)&& (DQMSK[n]==0) &&(MONERS:ESTOP==0), the DSTC proceeds to #3. If the DQMSK[n] Register or ESTOP Register is set to 1, the DSTC ignores the DREQ[n] signal from a peripheral and holds the start of the HW Transfer.
Page 536: Operation Flow After Specifying Of Desp
CHAPTER 11: DSTC Operation Flow after Specifying of DESP 3.3.3 The operations the DSTC executes after a DESP has been executed are explained below. Figure 3-10 shows a flow chart of the operations the DSTC executes after a DESP has been specified. Numbers in the figure correspond to those used in the explanation after the figure.
Page 537 CHAPTER 11: DSTC #1 The DSTC starts its operation from referring to a DESP specified by Arbiter 2. #2 If the read skip buffer function is enabled (CFG:RBDIS = 0) and the DESP to which the DSTC refers is the same as the one it referred to, the DSTC skips referring to the DES in the memory area and proceeds to #7.
Page 538 CHAPTER 11: DSTC #29 If MODE is 0, the DSTC always proceeds to #30. If MODE is 1 and transfers for the times of the inner loop count have ended (ORM !=1 and IRM ==1 ), the DSTC proceeds to #30. Otherwise the DSTC proceeds to #32.
Page 539: Examples Of Dstc Operations And Control
CHAPTER 11: DSTC Examples of DSTC Operations and Control This section describes examples of DSTC operations and control. 4.1. Transfer Operation Example 1 4.2. Transfer Operation Example 2 4.3. Transfer Operation Example 3 4.4. Transfer Operation Example 4 4.5. Transfer Operation Example 5 4.6.
Page 540: Transfer Operation Example 1
CHAPTER 11: DSTC Transfer Operation Example 1 This section describes transfer operation example 1. Transfer operation example 1 is an example on SW Transfer in mode 0. DES Values at Transfer Start Table 4-1 shows the settings of the DES in transfer operation example 1. As ORL[2:0] are set to 101, there is no DES5 area.
Page 541 CHAPTER 11: DSTC The DSTC starts the transfer of the DES due to the Start Trigger of (A). Values inside rectangles in Figure 4-1 are transfer source addresses and transfer destination addresses. The DSTC starts from a 32-bit transfer to the area from address 0x0000 to address 0x1000. The DSTC executes three times (IIN = 3) of 32-bit transfer successively.
Page 542 CHAPTER 11: DSTC After Start Trigger of (B): * The DSTC read the instruction from DES0. * The DSTC read (1,3) from DES1. * The DSTC read 0x0000 from DES2. * The DSTC read 0x100C from DES3. After 2nd transfer: The DSTC copy (2,3) to DES1 from DES4 for OuterReload.
Page 543: Transfer Operation Example 2
CHAPTER 11: DSTC Transfer Operation Example 2 This section describes transfer operation example 2. Transfer operation example 2 is an example on HW Transfer in mode 1. DES Values at Transfer Start Table 4-3 shows the settings of the DES in transfer operation example 2. As ORL[2:0] are set to 000, there are no DES4 area, DES5 area or DES6 area.
Page 544 CHAPTER 11: DSTC The DSTC starts the transfer of the DES due to the Start Trigger of (A). The DSTC executes one 16-bit transfer to the area from address 0x0000 to address 0x1000. The transfer number counter reads (2,2). As IRM is not 1, according to the setting of CHRS[1:0] of the DES (CHRS[1:0] = 00), the DSTC does not set the HWINT[n] Register to 1.
Page 545: Transfer Operation Example 3
CHAPTER 11: DSTC Transfer Operation Example 3 This section describes transfer operation example 3. Transfer operation example 3 is an example on using the Chain Start of the succeeding DES. DES Values at Transfer Start In transfer operation example 3, the DSTC uses the Chain Start to re-arrange data at 0x0000 to 0x00FF and transfer data to the area between 0x0100 and 0x01FF.
Page 546 CHAPTER 11: DSTC Figure 4-3 Operation Flow in Transfer Operation Example 3 (A) Start Trigger Source area Destination area Write DESP (1st-DES) from CPU 0x0000 0x1003 Counter of 1st-DES:(1,64) 0x0000 0x1000 0x0004 0x1007 Counter of 1st-DES:(1,63) - - - - - 0x00FC 0x10FF Counter of 1st-DES:(1,1)
Page 547: Transfer Operation Example 4
CHAPTER 11: DSTC Transfer Operation Example 4 This section describes transfer operation example 4. DES Values at Transfer Start Below are details of transfer operation example 4. This example illustrates executing the Chain Start of the current DES again with CHRS set to 11. Table 4-6 shows settings of the DES. Table 4-6 DES Values at Transfer Start in Transfer Operation Example 4 DES No.
Page 548 CHAPTER 11: DSTC The DSTC starts the transfer of the DES due to the Start Trigger of (A). The DSTC executes 32768 (IIN = 32768) times of 32-bit transfer successively with the address increasing during transfers. The transfer number counter for the DES starts counting from (3,32768) and reads (3,1) after 32768 times of transfer. As CHRS[3:2] of the DES is 11, the Chain Start Trigger for the transfer of the same DES is issued again.
Page 549: Transfer Operation Example 5
CHAPTER 11: DSTC Transfer Operation Example 5 This section describes transfer operation example 5. DES Values at Transfer Start Below are details of transfer operation example 5. Table 4-8 DES Values at Transfer Start in Transfer Operation Example 5 Area DES No.
Page 550 CHAPTER 11: DSTC This example illustrates an operation in which relatively complicated Chain Start settings are done. Three DES are used in this example. Table 4-8 shows the respective values of 1st-DES, 2nd-DES and 3rd-DES. Transfer Operation Flow Figure 4-5 shows the transfer operation flow in transfer operation example 5. The Start Triggers of (A), (B), (D) and (E) in Figure 4-5 indicate HW Start transfers and correspond to the assertion of the transfer request signal from a peripheral.
Page 551 CHAPTER 11: DSTC CHRS[1:0] of 1st-DES (CHRS[1:0] = 00), the DSTC does not set the HWINT[n] Register to 1. The DSTC waits for the next Start Trigger. The DSTC starts the transfer of 1st-DES again due to the Start Trigger of (E). The DSTC executes one 32-bit transfer to the area from address 0x0004 to address 0x100C.
Page 552: Examples Of Controlling Dstc
CHAPTER 11: DSTC Examples of Controlling DSTC This section explains sample procedures for controlling the DSTC. Sample Procedures for Transition to Standby State and for Transition to Normal State The DSTC transits to the standby state upon a bus reset. To make the DSTC execute a transfer, it is necessary to make the DSTC first transit from the standby state to the normal state.
Page 553 CHAPTER 11: DSTC Sample Procedure for Controlling Transfer Operation Figure 4-7 illustrates a sample procedure for controlling the transfer operation of the DSTC. Numbers in the Figure 4-7 correspond to those used in the explanation after the figure. Figure 4-7 Sample Procedure for Controlling DSTC Transfer Operation #1 Start (DSTC normal state) #2 Setup DSTC registers.
Page 554 CHAPTER 11: DSTC #4 The DQMSK[n] Register has been cleared upon a bus reset. However, it may be set by an HW Transfer error, a standby transition command or a source specified in DMSET of the DES. Write 1 to the DQMSKCLR[n] Register to clear the DQMSK[n] Register.
Page 555 CHAPTER 11: DSTC Procedure to break off a Hardware Transfer of DSTC This section explains the procedure to break off a hardware transfer of DSTC, by using HW transfer triggered by ADC as an example. When performing the HW transfer triggered by ADC, setting DES0.DMSET=1 is required at the first build of DES before the transfer starts.
Page 556: Registers And Descriptors Of Dstc
CHAPTER 11: DSTC Registers and Descriptors of DSTC This section explains the functions of registers of the DSTC and the functions of descriptors. 5.1. Lists of Control Registers and DES 5.2. DESTP Register 5.3. HWDESP[n] Register 5.4. CMD Register 5.5. CFG Register 5.6.
Page 557: Lists Of Control Registers And Des
CHAPTER 11: DSTC Lists of Control Registers and DES This section shows the respective lists of control registers of the DSTC and DES. Table 5-1 shows a list of the control registers of the DSTC and Table 5-2 a list of DES. Table 5-1 List of Control Registers of DSTC Address Register Name...
Page 558: Destp Register
CHAPTER 11: DSTC DESTP Register The DESTP (Descriptor top address) Register sets the start address of the DES area. Register configuration Address: +0x00 Field DESTP[31:0] Attribute Initial value 0x00000000 Register function The DSTC refers to and updates the DES located at the address of "DESTP + DESP". Set the DES area in a memory area that is readable and writable.
Page 559: Hwdesp[N] Register
CHAPTER 11: DSTC HWDESP[n] Register The HWDESP[n] (Hardware DES pointer) Register sets the DESP of the DES that the DSTC refers to at a transfer request of HW channel n. Register configuration Address: +0x04 Field Reserved HWDESP[13:0] Reserved CHANNEL[7:0] Attribute Initial value XXXXXXXXXXXX00 00000000...
Page 560: Cmd Register
CHAPTER 11: DSTC CMD Register The CMD (Command) Register issues a command to the DSTC and reads the state of the DSTC. Register configuration Address: +0x08 Field CMD[7:0] Attribute Initial value Register function A command can be issued to the DSTC by writing a value to the CMD (Command) Register. Use an 8-bit (byte) access to write a value to this register.
Page 561: Cfg Register
CHAPTER 11: DSTC CFG Register The CFG (configuration) Register sets operation functions of the DSTC. Register configuration Address: +0x09 Field Reserved SWPR[2:0] ESTE RBDIS ERINTE SWINTE Attribute Initial value Register function The CFG (configuration) Register sets operation functions of the DSTC. Use an 8-bit (byte) access to write a value to this register.
Page 562 CHAPTER 11: DSTC HWDESP[n] Register has been modified, write "1" to the RBDIS bit. If the RBDIS bit is set to "1", the DSTC does not use the read skip buffer function or the HWDESPBUF function, but it operates referring to the DES value on the memory and the value of the HWDESP[n] Register.
Page 563: Swtr Register
CHAPTER 11: DSTC SWTR Register The SWTR (Software trigger) Register issues the Start Trigger of the SW Start transfer. Register configuration Address: +0x0A Field SWST SWREQ SWDESP[13:0] Attribute Initial value 00000000000000 Register function The SWTR (Software trigger) Register issues the Start Trigger of the SW Transfer if a write access to this register is made.
Page 564: Moners Register
CHAPTER 11: DSTC MONERS Register The MONERS Register shows details of a transfer error that has occurred. Register configuration Address: +0x0C Field Reserved EDESP[13:8] Attribute Initial value Field EDESP[7:0] Attribute Initial value Field ECH[7:0] Attribute Initial value Field Reserved Reserved ESTOP EST[2:0] Attribute...
Page 565 CHAPTER 11: DSTC bit[3] DER (Double error) The DER bit indicates whether a double error has occurred. With the EST[2:0] bits set to a value other than "000" and the DER bit set to "0", if a new transfer error occurs, the DER bit is set to "1". The DER bit is cleared to "0"...
Page 566 CHAPTER 11: DSTC bit[29:16] EDESP [13:0](Error DES pointer) The EDESP[13:0] bits indicate the DESP of the DES that has caused a transfer error. In the case of EST ≠ 000, even if a new transfer error occurs, the EDESP[13:0] bits keep the DESP of the DES of the previous transfer error.
Page 567: Dreqenb[N] Register
CHAPTER 11: DSTC DREQENB[n] Register The DREQENB[n] Register determines whether HW channel n is used. Register configuration Address 0x10 Field DREQENB[31:0] +0x14 Field DREQENB[63:32] +0x18 Field DREQENB[95:64] +0x1C Field DREQENB[127:96] +0x20 Field DREQENB[159:128] +0x24 Field DREQENB[191:160] +0x28 Field DREQENB[223:192] +0x2C Field DREQENB[255:224] Attribute...
Page 568: Hwint[N] Register
CHAPTER 11: DSTC HWINT[n] Register The HWINT[n] Register sends the HW Transfer end notification to the CPU. Register configuration Address +0x30 Field HWINT[31:0] +0x34 Field HWINT[63:32] +0x38 Field HWINT[95:64] +0x3C Field HWINT[127:96] +0x40 Field HWINT[159:128] +0x44 Field HWINT[191:160] +0x48 Field HWINT[223:192] +0x4C Field...
Page 569: Hwintclr[N] Register
CHAPTER 11: DSTC HWINTCLR[n] Register 5.10 The HWINTCLR[n] Register is a register for clearing the HWINT[n] Register. Register configuration Address +0x50 Field HWINTCLR[31:0] +0x54 Field HWINTCLR[63:32] +0x58 Field HWINTCLR[95:64] +0x5C Field HWINTCLR[127:96] +0x60 Field HWINTCLR[159:128] +0x64 Field HWINTCLR[191:160] +0x68 Field HWINTCLR[223:192] +0x6C Field...
Page 570: Dqmsk[N] Register
CHAPTER 11: DSTC DQMSK[n] Register 5.11 The DQMSK[n] Register indicates whether the HW Start transfer request is being suppressed. Register configuration Address +0x70 Field DQMSK[31:0] +0x74 Field DQMSK[63:32] +0x78 Field DQMSK[95:64] +0x7C Field DQMSK[127:96] +0x80 Field DQMSK[159:128] +0x84 Field DQMSK[191:160] +0x88 Field DQMSK[223:192]...
Page 571: Dqmskclr[N] Register
CHAPTER 11: DSTC DQMSKCLR[n] Register 5.12 The DQMSKCLR[n] Register is a register for clearing the DQMSK[n] Register. Register configuration Address +0x90 Field DQMSKCLR[31:0] +0x94 Field DQMSKCLR[63:32] +0x98 Field DQMSKCLR[95:64] +0x9C Field DQMSKCLR[127:96] +0xA0 Field DQMSKCLR[159:128] +0xA4 Field DQMSKCLR[191:160] +0xA8 Field DQMSKCLR[223:192] +0xAC Field...
Page 572: Descriptor 0 (Des0)
CHAPTER 11: DSTC Descriptor 0 (DES0) 5.13 This section explains details of Descriptor 0 (DES0). DES0 sets the basic settings of a transfer. Descriptor configuration Address: DESTP + DESP + 0x00 Field PCHK[3:0] Reserved ACK[1:0] C attribute D attribute Field CHLK DMSET CHRS[5:0]...
Page 573 CHAPTER 11: DSTC bit[3:2] ST[1:0] (Transfer status) After the transfer specified in a DES has ended, in a DES close process, the DSTC writes the end status value to the ST[1:0] bits. If the DSTC does not execute the DES close process, the value initially set by the CPU remains in the ST[1:0] bits.
Page 574 CHAPTER 11: DSTC bit[12:10] SAC[2:0] (Source Address Control) The SAC[2:0] specify the method of updating the transfer source address during a transfer. The DSTC does not modify the value of this area. The setting is that DES0.DV[1]=1 and DES2 is need to rebuild (DES2 is not returned to the start value), caused to notify a DES open error from the DSTC.
Page 575 CHAPTER 11: DSTC The status of the transfer number counter determines which of CHRS[5:4], CHRS[3:2] and CHRS[1:0] the DSTC follows when executing the next process after the current DES. If there is an interrupt flag set instruction, an SW Start Trigger, and a Chain Start Trigger after that SW Start Trigger set the SWST bit to the SWTR register to 1.
Page 576: Descriptor 1 (Des1)
CHAPTER 11: DSTC Descriptor 1 (DES1) 5.14 This section explains details of Descriptor 1 (DES1). DES1 sets the number of transfers. The configuration and functions of DES1 area in mode 0 (DES0.MODE=0) are different from those in mode 1 (DES0.MODE=1). Descriptor configuration (in mode 0) Address: DESTP + DESP + 0x04 Field...
Page 577 CHAPTER 11: DSTC Descriptor configuration (in mode 1) Address: DESTP + DESP + 0x04 Field ORM[15:0] IRM[7:0] IIN[7:0] C attribute D attribute Descriptor function (in mode 1) bit[7:0] IIN[7:0] (Inner loop initial) The IIN[15:0] bits specify the initial value of the inner loop counter in the transfer number counter. They can be set to a value in the range of "1"...
Page 578: Descriptor 2 (Des2)
CHAPTER 11: DSTC Descriptor 2 (DES2) 5.15 This section explains details of Descriptor 2 (DES2). DES2 Descriptor configuration Address: DESTP + DESP + 0x08 Field SA[31:0] C attribute D attribute DES2 Descriptor function bit[31:0] SA[31:0] (Source address) The SA[31:0] bits set the transfer source address. The SA[31:0] bits cannot be set to a value unaligned to the data size specified in DES0:TW.
Page 579: Descriptor 4 (Des4)
CHAPTER 11: DSTC Descriptor 4 (DES4) 5.17 This section explains details of Descriptor 4 (DES4). DES4 Descriptor configuration Address: DESTP + DESP + 0x10 (ORL[2:0] = xx1) Field DES4[31:0] C attribute D attribute DES4 Descriptor function bit[31:0] DES4[31:0] (Descriptor 4) DES4 sets the value to be loaded to DES1 (number of transfers) in OuterReload.
Page 580 CHAPTER 11: DSTC FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 581: Chapter 12: I/O Port
CHAPTER 12: I/O Port This chapter explains the I/O port. 1. Overview 2. Configuration, Block Diagram, and Operation 3. Setup Procedure Example 4. Registers 5. Usage Precautions FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 582: Overview
CHAPTER 12: I/O Port Overview This section provides an overview of the I/O port. The I/O port of this series provides the following features.  The I/O port of this series shares the following functions. − GPIO General-purpose I/O ports, which can read an input level and set an output level from the CPU. −...
Page 583: Configuration, Block Diagram, And Operation
CHAPTER 12: I/O Port Configuration, Block Diagram, and Operation This section explains the configuration, block diagram, and operation of the I/O port. Configuration of the I/O Port By setting registers of the I/O port, select Input/Output direction and select GPIO/peripheral. Figure 2-1 shows the details of the I/O port.
Page 584 CHAPTER 12: I/O Port *2: When one of the followings is set, the input value is fixed to 0. Otherwise, the pin is set as the digital input pin. − ADE/SPSR=1 − DAE=1 Notes: − USB pin does not have pull-up resistor. −...
Page 585 CHAPTER 12: I/O Port Table 2-1 Register Function Descriptions Register Name Function Description A register to set whether the I/O port will be used as a special pin (an analog input pin) or a digital input/output pin. SPSR A register to set whether the I/O port will be used as a special pin (USB or oscillation) or a digital input/output pin. A register to set whether the I/O port will be used as an input/output pin of GPIO function or an input/output pin of peripheral functions.
Page 586 CHAPTER 12: I/O Port Table 2-2 lists pin functions which availability depends on selected I/O port functions and register setting values. Table 2-2 I/O Port Functions and Register Setting Values I/O Port Function ADE/ SPSR EPFR PDSR Available Main Function Available Sub Function Special pin (Analog input,...
Page 587 CHAPTER 12: I/O Port Initially Selected Functions for the I/O Port Table 2-3 describes initially selected functions for each I/O port after reset is released. Table 2-3 Initially Selected Functions for Each I/O Port after Reset Is Released Initially Selected Function TRSTX, TCK, TDI, TMS, TDO JTAG pin is selected.
Page 588 CHAPTER 12: I/O Port − Which peripheral function is allocated to which pin depends on products. See the pin function list of Data Sheet of the product used. − Even if the input of one I/O port is connected to two or more peripheral functions, all peripheral inputs can be used by setting EPFR.
Page 589 CHAPTER 12: I/O Port Fixed Priority of EPFR Outputs Only one output pin function among two or more outputs is allocated to one I/O port. By setting the EPFR register, if more than one output is set, fixed priority is applied and output pins are selected.
Page 590 CHAPTER 12: I/O Port Operation in Deep Standby Mode GPIO function is selected in deep standby mode. Figure 2-5 shows I/O port operation in deep standby mode. Figure 2-5 I/O Port Operation in Deep Standby Mode Program I/O port (SPL=0) GPIO Program setting valid setting valid...
Page 591: Setup Procedure Example
CHAPTER 12: I/O Port Setup Procedure Example This section explains a procedure example of setting up the I/O port. Setup of the I/O Port By setting registers of the I/O port, select I/O direction and select GPIO/peripheral. Figure 3-1 shows a setup procedure example. Figure 3-1 Setup Procedure Example of the I/O Port Start The pin doubles as a...
Page 592: Registers
CHAPTER 12: I/O Port Registers This section provides the register list of the I/O port. Table 4-1 provides the register list. Table 4-1 Register List of the I/O Port Abbreviation Register Name Reference PFR0 Port function setting register 0 PFR1 Port function setting register 1 PFR2 Port function setting register 2...
Page 593 CHAPTER 12: I/O Port Abbreviation Register Name Reference DDR0 Port input/output direction setting register 0 DDR1 Port input/output direction setting register 1 DDR2 Port input/output direction setting register 2 DDR3 Port input/output direction setting register 3 DDR4 Port input/output direction setting register 4 DDR5 Port input/output direction setting register 5 DDR6...
Page 594 CHAPTER 12: I/O Port Abbreviation Register Name Reference Analog input setting register 4.41 SPSR Special Port Setting Register EPFR00 Extended pin function setting register 00 EPFR01 Extended pin function setting register 01 4.10 EPFR02 Extended pin function setting register 02 4.11 EPFR03 Extended pin function setting register 03...
Page 595 CHAPTER 12: I/O Port Abbreviation Register Name Reference PZRB Port pseudo open drain setting register B PZRC Port pseudo open drain setting register C 4.42 PZRD Port pseudo open drain setting register D PZRE Port pseudo open drain setting register E PZRF Port pseudo open drain setting register F PDSR0...
Page 596: Port Function Setting Register (Pfrx)
CHAPTER 12: I/O Port Port Function Setting Register (PFRx) The PFRx register selects usage of a pin. List of PFR Register Configuration Initial value Attribute Corresponding port Reserved PFR0 0x001F P0F to P00 Reserved PFR1 0x0000 P1F to P10 Reserved PFR2 0x0000 P2F to P20...
Page 597 CHAPTER 12: I/O Port Notes: − The "x" of PFRx is a wildcard. PFRx indicates PFR0, PFR1, PFR2, etc. − The "x" of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, etc. PxF indicates P0F, P1F, P2F, etc. −...
Page 598: Pull-Up Setting Register (Pcrx)
CHAPTER 12: I/O Port Pull-up Setting Register (PCRx) The PCRx register sets pull-up of a pin. List of PCR Register Configuration Initial value Attribute Corresponding port Reserved PCR0 0x001F P0F to P00 Reserved PCR1 0x0000 P1F to P10 Reserved PCR2 0x0000 P2F to P20 Reserved...
Page 599 CHAPTER 12: I/O Port Notes: − The "x" of PCRx is a wildcard. PCRx indicates PCR0, PCR1, PCR2, etc. − The "x" of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, etc. PxF indicates P0F, P1F, P2F, etc. −...
Page 600: Port Input/Output Direction Setting Register (Ddrx)
CHAPTER 12: I/O Port Port input/output Direction Setting Register (DDRx) The DDRx register sets input/output direction of a pin. List of DDR Register Configuration Initial value Attribute Corresponding port Reserved DDR0 0x0000 P0F to P00 Reserved DDR1 0x0000 P1F to P10 Reserved DDR2 0x0000...
Page 601 CHAPTER 12: I/O Port Notes: − The "x" of DDRx is a wildcard. DDRx indicates DDR0, DDR1, DDR2, etc. − The "x" of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, etc. PxF indicates P0F, P1F, P2F, etc. −...
Page 602: Port Input Data Register (Pdirx)
CHAPTER 12: I/O Port Port Input Data Register (PDIRx) The PDIRx register indicates input data of a pin. List of PDIR Register Configuration Initial value Attribute Corresponding port Reserved PDIR0 0x0000 P0F to P00 Reserved PDIR1 0x0000 P1F to P10 Reserved PDIR2 0x0000...
Page 603 CHAPTER 12: I/O Port Notes: − The "x" of PDIRx is a wildcard. PDIRx indicates PDIR0, PDIR1, PDIR2, etc. − The "x" of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, etc. PxF indicates P0F, P1F, P2F, etc. −...
Page 604: Port Output Data Register X (Pdorx)
CHAPTER 12: I/O Port Port Output Data Register x (PDORx) The PDORx register sets output data to a pin. List of PDOR Register Configuration Initial value Attribute Corresponding port Reserved PDOR0 0x0000 P0F to P00 Reserved PDOR1 0x0000 P1F to P10 Reserved PDOR2 0x0000...
Page 605 CHAPTER 12: I/O Port Notes: − The "x" of PDORx is a wildcard. PDORx indicates PDOR0, PDOR1, PDOR2, etc. − The "x" of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, etc. PxF indicates P0F, P1F, P2F, etc. −...
Page 606: Analog Input Setting Register (Ade)
CHAPTER 12: I/O Port Analog Input Setting Register (ADE) The ADE register sets an external pin as an analog signal input pin of ADC. Register Configuration Field Attribute Initial value 0xFFFFFFFF Register Function [bit31:0] ADE: Analog Input Setting Register Sets as an analog signal input pin. Description Reading Reads out the register value.
Page 607: Extended Pin Function Setting Register (Epfrx)
CHAPTER 12: I/O Port Extended Pin Function Setting Register (EPFRx) The EPFRx register assigns functions to a pin if there is more than one function. List of EPFRx Register Configuration Initial value Attribute Corresponding function EPFR00 0x00030000 System function EPFR01 0x00000000 EPFR02 0x00000000...
Page 608: Extended Pin Function Setting Register 00 (Epfr00)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 00 (EPFR00) The EPFR00 register assigns functions to a pin if there is more than one function. Register Configuration Field Reserved TRC3E TRC2E TRC1E TRC0E Attribute Initial value Field Reserved JTAGEN1S JTAGEN0B Attribute Initial value Field...
Page 609 CHAPTER 12: I/O Port [bit25] TRC1E: TRACED Function Select bit 1 Selects a function for TRACED2 and TRACED3 pins. Description Reading Reads out the register value. Does not use two pins of TRACED2 and TRACED3. [Initial value] (A shared pin is available) Writing Uses two pins of TRACED2 and TRACED3.
Page 610 CHAPTER 12: I/O Port [bit13] USBP1E: USB ch.1 Function Select bit 1 Selects a function for USB ch.1. Description Reading Reads out the register value. Does not produce output D+ resistor control signal (HCONTX) for USB ch.1. [Initial value] (A shared pin is available.) Writing Produces output D+ resistor control signal (HCONTX) for USB ch.1.
Page 611 CHAPTER 12: I/O Port [bit3] Reserved: Reserved bit 0 is read out from this bit. When writing this bit, set it to 0. [bit2:1] CROUTE: Internal high-speed CR Oscillation Output Function Select bit Selects internal high-speed CR oscillation output. Description Reading Reads out the register value.
Page 612: Extended Pin Function Setting Register 01 (Epfr01)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 01 (EPFR01) The EPFR01 register assigns functions to a pin of the multifunction timer Unit0. Register Configuration Field IC03S IC02S IC01S Attribute Initial value Field IC01S IC00S FRCK0S DTTI0S Attribute Initial value Field Reserved DTTI0C...
Page 613 CHAPTER 12: I/O Port [bit28:26] IC02S: IC02 Input Select bits Selects input for IC02. Description Reading Reads out the register value. Uses IC02_0 at the input pin of the input capture IC02. [Initial value] Same as Writing 000. Uses IC02_1 at the input pin of the input capture IC02. Uses IC02_2 at the input pin of the input capture IC02.
Page 614 CHAPTER 12: I/O Port [bit17:16] DTTI0S: DTTI0X Input Select bits Selects input for DTTI0X. Description Reading Reads out the register value. Uses DTTI0X_0 at the input pin of the waveform generator DTTI0X. [Initial value] Same as Writing 00. Writing Uses DTTI0X_1 at the input pin of the waveform generator DTTI0X. Uses DTTI0X_2 at the input pin of the waveform generator DTTI0X.
Page 615 CHAPTER 12: I/O Port [bit5:4] RTO02E: RTO02 Output Select bits Selects output for RTO02. bit5:4 Description Reading Reads out the register value. Does not produce output for the waveform generator RTO02. [Initial value] Uses RTO02_0 at the output pin of the waveform generator RTO02. Writing Uses RTO02_1 at the output pin of the waveform generator RTO02.
Page 616: Extended Pin Function Setting Register 02 (Epfr02)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 02 (EPFR02) 4.10 The EPFR02 register assigns functions to a pin of the multifunction timer Unit1. Register Configuration Field IC13S IC12S IC11S Attribute Initial value Field IC11S IC10S FRCK1S DTTI1S Attribute Initial value Field Reserved...
Page 617 CHAPTER 12: I/O Port [bit28:26] IC12S: IC12 Input Select bits Selects input for IC12. Description Reading Reads out the register value. Uses IC12_0 at the input pin of the input capture IC12. [Initial value] Same as Writing 000. Uses IC12_1 at the input pin of the input capture IC12. Setting is prohibited.
Page 618 CHAPTER 12: I/O Port [bit17:16] DTTI1S: DTTI1X Input Select bits Select input for DTTI1X. Description Reading Reads out the register value. Uses DTTI1X_0 at the input pin of the waveform generator DTTI1X. [Initial value] Same as Writing 00. Writing Uses DTTI1X_1 at the input pin of the waveform generator DTTI1X. Setting is prohibited.
Page 619 CHAPTER 12: I/O Port [bit5:4] RTO12E: RTO12 Output Select bits Selects output for RTO12. Description Reading Reads out the register value. Does not produce output for the waveform generator RTO12. [Initial value] Uses RTO12_0 at the output pin of the waveform generator RTO12. Writing Uses RTO12_1 at the output pin of the waveform generator RTO12.
Page 620: Extension Function Pin Setting Register 03 (Epfr03)
CHAPTER 12: I/O Port Extension Function Pin Setting Register 03 (EPFR03) 4.11 EPFR03 register sets the function assignment to the multi-function timer Unit2 pin. Register Configuration Field IC23S IC22S IC21S Attribute Initial value Field IC21S IC20S FRCK2S DTTI2S Attribute Initial value Field Reserved DTTI2C...
Page 621 CHAPTER 12: I/O Port [bit28:26] IC22S: IC22 input select bits Selects IC22 input. Description Reading Reads out the register value. Use IC22_0 as the input pin of input capture IC22. [initial value] Same as when writing 000 Use IC22_1 as the input pin of input capture IC22. Setting is prohibited.
Page 622 CHAPTER 12: I/O Port [bit17:16] DTTI2S: DTTI2X Input Select bits Selects input for DTTI2X. Description Reading Reads out the register value. Use DTTI2X_0 as the input pin of waveform generator DTTI2X. [Initial value] Same as Writing 00. Writing Use DTTI2X_1 as the input pin of waveform generator DTTI2X. Setting is prohibited.
Page 623 CHAPTER 12: I/O Port [bit5:4] RTO22E: RTO22 Output Select bits Selects output for RTO22. Description Reading Reads out the register value. Does not output waveform generator RTO22. [Initial value] Use RTO22_0 as the output pin of waveform generator RTO22. Writing Use RTO22_1 as the output pin of waveform generator RTO22.
Page 624: Extended Pin Function Setting Register 04 (Epfr04)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 04 (EPFR04) 4.12 The EPFR04 register assigns functions to pins of ch.0, ch.1, ch.2, and ch.3 of the base timer. Register Configuration Field Reserved TIOB3S TIOA3E TIOA3S Attribute Initial value Field Reserved TIOB2S TIOA2E...
Page 625 CHAPTER 12: I/O Port [bit25:24] TIOA3S: TIOA3 Input Select bits Selects input for TIOA3. Description Reading Reads out the register value. Uses TIOA3_0 at the input pin of BT ch.3 TIOA. [Initial value] Same as Writing 00. Writing Uses TIOA3_1 at the input pin of BT ch.3 TIOA. Uses TIOA3_2 at the input pin of BT ch.3 TIOA.
Page 626 CHAPTER 12: I/O Port [bit11:10] TIOA1E: TIOA1 Output Select bits Selects output for TIOA1. Description Reading Reads out the register value. Does not produce output for BT ch.1 TIOA. [Initial value] Uses TIOA1_0 at the output pin of BT ch.1 TIOA. Writing Uses TIOA1_1 at the output pin of BT ch.1 TIOA.
Page 627 CHAPTER 12: I/O Port [bit1:0] Reserved: Reserved bits 0b00 is read out from these bits. When writing these bits, set them to 0b00. Notes: − TIOA Even channels are for output only. Odd channels are for both input and output. −...
Page 628: Extended Pin Function Setting Register 05 (Epfr05)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 05 (EPFR05) 4.13 The EPFR05 register assigns functions to pins of ch.4, ch.5, ch.6, and ch.7 of the base timer. Register Configuration Field Reserved TIOB7S TIOA7E TIOA7S Attribute Initial value Field Reserved TIOB6S TIOA6E...
Page 629 CHAPTER 12: I/O Port [bit25:24] TIOA7S: TIOA7 Input Select bits Selects input for TIOA7. Description Reading Reads out the register value. Uses TIOA7_0 at the input pin of BT ch.7 TIOA. [Initial value] Same as Writing 00. Writing Uses TIOA7_1 at the input pin of BT ch.7 TIOA. Uses TIOA7_2 at the input pin of BT ch.7 TIOA.
Page 630 CHAPTER 12: I/O Port [bit11:10] TIOA5E: TIOA5 Output Select bits Selects output for TIOA5. bit11:10 Description Reading Reads out the register value. Does not produce the output of the BT ch.5 TIOA. [Initial value] Uses TIOA5_0 at the output pin of BT ch.5 TIOA. Writing Uses TIOA5_1 at the output pin of BT ch.5 TIOA.
Page 631 CHAPTER 12: I/O Port Notes: − TIOA Even channels are for output only. Odd channels are for both input and output. − TIOB Input only. − TIOA1, TIOA3, TIOA5, TIOA7(odd number of "A") are not bidirectional pins so that choose either input pin or output pin for them.
Page 632: Extended Pin Function Setting Register 06 (Epfr06)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 06 (EPFR06) 4.14 The EPFR06 register assigns functions to external interrupt pins. Register Configuration Field EINT15S EINT14S EINT13S EINT12S Attribute Initial value Field EINT11S EINT10S EINT09S EINT08S Attribute Initial value Field EINT07S EINT06S EINT05S...
Page 633 CHAPTER 12: I/O Port [bit27:26] EINT13S: External Interrupt Input Select bits Selects input for EINT13. Description Reading Reads out the register value. Uses INT13_0 at the input pin of EINT ch.13. [Initial value] Same as Writing 00 Writing Uses INT13_1 at the input pin of EINT ch.13. Uses INT13_2 at the input pin of EINT ch.13.
Page 634 CHAPTER 12: I/O Port [bit17:16] EINT08S: External Interrupt Input Select bits Selects input for EINT08. Description Reading Reads out the register value. Uses INT08_0 at the input pin of EINT ch.8. [Initial value] Same as Writing 00. Writing Uses INT08_1 at the input pin of EINT ch.8. Uses INT08_2 at the input pin of EINT ch.8.
Page 635 CHAPTER 12: I/O Port [bit7:6] EINT03S: External Interrupt Input Select bits Selects input for EINT03. Description Reading Reads out the register value. Uses INT03_0 at the input pin of EINT ch.3. [Initial value] Same as Writing 00. Writing Uses INT03_1 at the input pin of EINT ch.3. Uses INT03_2 at the input pin of EINT ch.3.
Page 636: Extended Pin Function Setting Register 07 (Epfr07)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 07 (EPFR07) 4.15 The EPFR07 register assigns functions of multi-function serial ch.0 to ch.3. Register Configuration Field Reserved SCK3B SOT3B Attribute Initial value Field SIN3S SCK2B SOT2B SIN2S Attribute Initial value Field SCK1B SOT1B...
Page 637 CHAPTER 12: I/O Port [bit25:24] SOT3B: SOT3 Input/Output Select bits Selects input/output for SOT3. Description Reading Reads out the register value. Uses SOT3_0 at the input pin of MFS ch.3 SOT. Does not produce output. [Initial value] Uses SOT3_0 at the input pin of MFS ch.3 SOT. Uses SOT3_0 at the output pin.
Page 638 CHAPTER 12: I/O Port [bit17:16] SIN2S: SIN2 Input Select bits Selects input for SIN2. Description Reading Reads out the register value. Uses SIN2_0 at the input pin of MFS ch.2 SIN. [Initial value] Same as Writing 00. Writing Uses SIN2_1 at the input pin of MFS ch.2 SIN. Uses SIN2_2 at the input pin of MFS ch.2 SIN.
Page 639 CHAPTER 12: I/O Port [bit9:8] SCK0B: SCK0 Input/Output Select bits Selects input/output for SCK0. Description Reading Reads out the register value. Uses SCK0_0 at the input pin of MFS ch.0 SCK. Does not produce output. [Initial value] Uses SCK0_0 at the input pin of MFS ch.0 SCK. Uses SCK0_0 at the output pin.
Page 640: Extended Pin Function Setting Register 08 (Epfr08)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 08 (EPFR08) 4.16 The EPFR08 register assigns functions of multi-function serial ch.4 to ch.7. Register Configuration Field CTS5S RTS5E SCK7B SOT7B Attribute Initial value Field SIN7S SCK6B SOT6B SIN6S Attribute Initial value Field SCK5B SOT5B...
Page 641 CHAPTER 12: I/O Port [bit27:26] SCK7B: SCK7 Input/Output Select bits Selects input/output for SCK7. Description Reading Reads out the register value. Uses SCK7_0 at the input pin of MFS ch.7 SCK. Does not produce output. [Initial value] Uses SCK7_0 at the input pin of MFS ch.7 SCK. Uses SCK7_0 at the output pin.
Page 642 CHAPTER 12: I/O Port [bit19:18] SOT6B: SOT6 Input/Output Select bits Selects input/output for SOT6. Description Reading Reads out the register value. Uses SOT6_0 at the input pin of MFS ch.6 SOT. Does not produce output. [Initial value] Uses SOT6_0 at the input pin of MFS ch.6 SOT. Uses SOT6_0 at the output pin.
Page 643 CHAPTER 12: I/O Port [bit11:10] SIN5S: SIN5 Input Select bits Selects input for SIN5. Description Reading Reads out the register value. Uses SIN5_0 at the input pin of MFS ch.5 SIN. [Initial value] Same as Writing 00. Writing Uses SIN5_1 at the input pin of MFS ch.5 SIN. Uses SIN5_2 at the input pin of MFS ch.5 SIN.
Page 644 CHAPTER 12: I/O Port [bit3:2] CTS4S: CTS4 Input Select bits Selects input for CTS4. Description Reading Reads out the register value. Uses CTS4_0 at the input pin of MFS ch.4 CTS. [Initial value] Same as Writing 00. Writing Uses CTS4_1 at the input pin of MFS ch.4 CTS. Uses CTS4_2 at the input pin of MFS ch.4 CTS.
Page 645: Extended Pin Function Setting Register 09 (Epfr09)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 09 (EPFR09) 4.17 The EPFR09 register assigns functions to CAN, ADC trigger, and QPRC peripheral pins. Register Configuration Field CTX1E CRX1S CTX0E CRX0S Attribute Initial value Field ADTRG2S ADTRG1S Attribute Initial value 0000 0000 Field...
Page 646 CHAPTER 12: I/O Port [bit27:26] CTX0E: CTX0E Output Select bits Selects output for CAN TX0. Description Reading Reads out the register value. Does not produce output for CAN ch.0 TX. [Initial value] Sets the output pin of CAN ch.0 TX to TX0_0. Writing Sets the output pin of CAN ch.0 TX to TX0_1.
Page 647 CHAPTER 12: I/O Port [bit19:16] ADTRG1S: ADTRG1 Input Select bits Selects input for ADTRG1. Description Reading Reads out the register value. 0000 Uses ADTG_0 at the input pin of ADC unit 1’s startup trigger. [Initial value] 0001 Same as Writing 0000. 0010 Uses ADTG_1 at the input pin of ADC unit 1’s startup trigger.
Page 648 CHAPTER 12: I/O Port [bit7:6] QAIN1S: QAIN1S Input Select bits Selects input for QPRC AIN1. bit7:6 Description Reading Reads out the register value. Uses AIN1_0 at the input pin of QPRC ch.1’s AIN. [Initial value] Same as Writing 00. Writing Uses AIN1_1 at the input pin of QPRC ch.1’s AIN.
Page 649: Extended Pin Function Setting Register 10 (Epfr10)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 10 (EPFR10) 4.18 The EPFR10 register assigns functions to external bus peripheral pins. Register Configuration Field UEA24E UEA23E UEA22E UEA21E UEA20E UEA19E UEA18E UEA17E Attribute Initial value Field UEA16E UEA15E UEA14E UEA13E UEA12E UEA11E...
Page 650 CHAPTER 12: I/O Port [bit28] UEA21E: UEA21E Output Select bit Selects output for external bus Address21. Description Reading Reads out the register value. Does not produce output for user external bus MAD21. [Initial value] Writing Produces output for user external bus MAD21. [bit27] UEA20E: UEA20E Output Select bit Selects output for external bus Address20.
Page 651 CHAPTER 12: I/O Port [bit22] UEA15E: UEA15E Output Select bit Selects output for external bus Address15. Description Reading Reads out the register value. Does not produce output for user external bus MAD15. [Initial value] Writing Produces output for user external bus MAD15. [bit21] UEA14E: UEA14E Output Select bit Selects output for external bus Address14.
Page 652 CHAPTER 12: I/O Port [bit16] UEA09E: UEA09E Output Select bit Selects output for external bus Address09. Description Reading Reads out the register value. Does not produce output for user external bus MAD09. [Initial value] Writing Produces output for user external bus MAD09. [bit15] UEA08E: UEA08E Output Select bit Selects output for external bus Address08.
Page 653 CHAPTER 12: I/O Port [bit10] UECS4E: UECS4E Output Select bit Selects output for external bus CS4. Description Reading Reads out the register value. Does not produce output for user external bus MCSX4. [Initial value] Writing Produces output for user external bus MCSX4. [bit9] UECS3E: UECS3E Output Select bit Selects output for external bus CS3.
Page 654 CHAPTER 12: I/O Port [bit4] UEDQME: UEDQME Output Select bit Selects output for external bus DQM. Description Reading Reads out the register value. Does not produce output for user external bus MDQM1or MDQM0. [Initial value] Writing Produces output for user external bus MDQM1 and MDQM0. [bit3] UEWEXE: UEWEXE Output Select bit Selects output for external bus WEX.
Page 655 CHAPTER 12: I/O Port Notes: − I/O selection of the external bus data[15:8] can be controlled collectively with EPFR10.bit1. I/O selection of the external bus data[15:8] can be controlled by each bit also with EPFR11.bit[24:17]. EPFR10.bit1 setting has the higher priority than EPFR11.bit[24:17] setting. To control I/O selection by setting EPFR11.bit[24:17], it is necessary to set EPFR10.bit1=0.
Page 656: Extended Pin Function Setting Register 11 (Epfr11)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 11 (EPFR11) 4.19 The EPFR11 register assigns functions to external bus peripheral pins. Register Configuration Field Reserved Reserved UED15B Attribute Initial value Field UED14B UED13B UED12B UED11B UED10B UED09B UED08B UED07B Attribute Initial value Field...
Page 657 CHAPTER 12: I/O Port Does not produce output for user external bus MADATA14. [Initial value] Input of user external bus MADATA 14 is connected to the pin. Writing Produces output for user external bus MADATA 14. Input of user external bus MADATA 14 is connected to the pin. [bit22] UED13B: UED13B Output Select bit Selects output for external bus data 13.
Page 658 CHAPTER 12: I/O Port [bit18] UED09B: UED09B Output Select bit Selects output for external bus data 09. Description Reading Reads out the register value. Does not produce output for user external bus MADATA09. [Initial value] Input of user external bus MADATA09 is connected to the pin. Writing Produces output for user external bus MADATA09.
Page 659 CHAPTER 12: I/O Port [bit13] UED04B: UED04B Output Select bit Selects output for external bus data 04. Description Reading Reads out the register value. Does not produce output for user external bus MADATA04. [Initial value] Input of user external bus MADATA04 is connected to the pin. Writing Produces output for user external bus MADATA04.
Page 660 CHAPTER 12: I/O Port [bit8] UEA07E: UEA07E Output Select bit Selects output for external bus address07. Description Reading Reads out the register value. Does not produce output for user external bus MAD07. [Initial value] Writing Produces output for user external bus MAD07. [bit7] UEA06E: UEA06E Output Select bit Selects output for external bus address06.
Page 661 CHAPTER 12: I/O Port [bit2] UEA01E: UEA01E Output Select bit Selects output for external bus address01. Description Reading Reads out the register value. Does not produce output for user external bus MAD01. [Initial value] Writing Produces output for user external bus MAD01. [bit1] UECS0E: UECS0E Output Select bit Selects output for external bus CS0.
Page 662: Extended Pin Function Setting Register 12 (Epfr12)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 12 (EPFR12) 4.20 The EPFR12 register assigns functions to pins of ch.8, ch.9, ch.10, and ch.11 of the base timer. Register Configuration Field Reserved TIOB11S TIOA11E TIOA11S Attribute Initial value Field Reserved TIOB10S TIOA10E...
Page 663 CHAPTER 12: I/O Port [bit25:24] TIOA11S: TIOA11 Input Select bits Selects input for TIOA11. Description Reading Reads out the register value. Uses TIOA11_0 at the input pin of BT ch.11 TIOA. [Initial value] Same as Writing 00. Writing Uses TIOA11_1 at the input pin of BT ch.11 TIOA. Uses TIOA11_2 at the input pin of BT ch.11 TIOA.
Page 664 CHAPTER 12: I/O Port [bit11:10] TIOA9E: TIOA9 Output Select bits Selects output for TIOA9. Description Reading Reads out the register value. Does not produce the output of the BT ch.9 TIOA. [Initial value] Uses TIOA9_0 at the output pin of BT ch.9 TIOA. Writing Uses TIOA9_1 at the output pin of BT ch.9 TIOA.
Page 665 CHAPTER 12: I/O Port Notes: − TIOA Even channels are for output only. Odd channels are for both input and output. − TIOB Input only. − TIOA9, TIOA11, TIOA13, TIOA15 (odd number of "A") are not bidirectional pins so that choose either input pin or output pin for them.
Page 666: Extended Pin Function Setting Register 13 (Epfr13)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 13 (EPFR13) 4.21 The EPFR13 register assigns functions to pins of ch.12, ch.13, ch.14, and ch.15 of the base timer. Register Configuration Field Reserved TIOB15S TIOA15E TIOA15S Attribute Initial value Field Reserved TIOB14S TIOA14E...
Page 667 CHAPTER 12: I/O Port [bit25:24] TIOA15S: TIOA15 Input Select bits Selects input for TIOA15. bit25:24 Description Reading Reads out the register value. Uses TIOA15_0 at the input pin of BT ch.15 TIOA. [Initial value] Same as Writing 00. Writing Uses TIOA15_1 at the input pin of BT ch.15 TIOA. Uses TIOA15_2 at the input pin of BT ch.15 TIOA.
Page 668 CHAPTER 12: I/O Port [bit11:10] TIOA13E: TIOA13 Output Select bits Selects output for TIOA13. Description Reading Reads out the register value. Does not produce the output of the BT ch.13 TIOA. [Initial value] Uses TIOA13_0 at the output pin of BT ch.13 TIOA. Writing Uses TIOA13_1 at the output pin of BT ch.13 TIOA.
Page 669 CHAPTER 12: I/O Port Notes: − TIOA Even channels are for output only. Odd channels are for both input and output. − TIOB Input only. − TIOA9, TIOA11, TIOA13, TIOA15 (odd number of "A") are not bidirectional pins so that choose either input pin or output pin for them.
Page 670: Extended Pin Function Setting Register 14 (Epfr14)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 14 (EPFR14) 4.22 EPFR14 register sets the function assignment to QPRC/Ethernet-MAC pins. Register Configuration Field Reserved E_SPLC E_PSE E_CKE E_MD1B E_MD0B Attribute Initial value Field E_MC1B E_MC0E E_TE1E E_TE0E E_TD1E E_TD0E Reserved Attribute Initial value...
Page 671 CHAPTER 12: I/O Port [bit26] E_CKE: E_COUT Output Select bit Selects output for E_COUT. Description Reading Reads out the register value. E_COUT is not output. [Initial value] Writing E_COUT is output. [bit25] E_MD1B :E_MDO1 I/O Select bit Selects I/O for E_MDO1. Description Reading Reads out the register value.
Page 672 CHAPTER 12: I/O Port [bit20] E_TE0E: E_TXEN0 Output Select bit Selects output for E_TXEN0. Description Reading Reads out the register value. E_TXEN0 is not output. [Initial value] Writing E_TXEN0 is output. [bit19] E_TD1E: E_TX02_TX10, E_TX03_TX11 Output Select bit Selects output for E_TX02_TX10, E_TX03_TX11. Description Reading Reads out the register value.
Page 673 CHAPTER 12: I/O Port Selects input for QDU-ch.2 as AIN. Description Reading Reads out the register value. AIN2_0 is used as AIN, the input pin of QDU ch.2. [Initial value] AIN2_0 is used as AIN, the input pin of QDU ch.2. Writing AIN2_1 is used as AIN, the input pin of QDU ch.2.
Page 674: Extended Pin Function Setting Register 15 (Epfr15)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 15 (EPFR15) 4.23 EPFR15 register sets the function assignment to external interrupt pins. Register Configuration Field EINT31S EINT30S EINT29S EINT28S Attribute Initial value Field EINT27S EINT26S EINT25S EINT24S Attribute Initial value Field EINT23S EINT22S...
Page 675 CHAPTER 12: I/O Port [bit27:26] EINT29S: External Interrupt Input Select bits Selects input for EINT29. Description Reading Reads out the register value. Uses INT29_0 at the input pin of EINT ch.29. [Initial value] Same as Writing 00. Writing Uses INT29_1 at the input pin of EINT ch.29. Uses INT29_2 at the input pin of EINT ch.29.
Page 676 CHAPTER 12: I/O Port [bit17:16] EINT24S: External Interrupt Input Select bits Selects input for EINT24. Description Reading Reads out the register value. Uses INT24_0 at the input pin of EINT ch.24. [Initial value] Same as Writing 00. Writing Uses INT24_1 at the input pin of EINT ch.24. Uses INT24_2 at the input pin of EINT ch.24.
Page 677 CHAPTER 12: I/O Port [bit7:6] EINT19S: External Interrupt Input Select bits Selects input for EINT19. Description Reading Reads out the register value. Uses INT19_0 at the input pin of EINT ch.19. [Initial value] Same as Writing 00. Writing Uses INT19_1 at the input pin of EINT ch.19. Uses INT19_2 at the input pin of EINT ch.19.
Page 678: Extended Pin Function Setting Register 16 (Epfr16)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 16 (EPFR16) 4.24 The EPFR16 register assigns functions of multi-function serial channel 6, channel 7, channel 8, channel 9, channel 10, and channel 11. Register Configuration Field Reserved SFMPBC SFMPAC SCK11B SOT11B Attribute Initial value...
Page 679 CHAPTER 12: I/O Port [bit27:26] SCK11B: SCK11 Input/Output Select bits Selects input/output for SCK11. Description Reading Reads out the register value. Uses SCK11_0 at the input pin of MFS ch.11 SCK. Does not produce output. [Initial value] Uses SCK11_0 at the input pin of MFS ch.11 SCK. Uses SCK11_0 at the output pin.
Page 680 CHAPTER 12: I/O Port [bit19:18] SOT10B: SOT10 Input/Output Select bits Selects input/output for SOT10. Description Reading Reads out the register value. Uses SOT10_0 at the input pin of MFS ch.10 SOT. Does not produce output. [Initial value] Uses SOT10_0 at the input pin of MFS ch.10 SOT. Uses SOT10_0 at the output pin.
Page 681 CHAPTER 12: I/O Port [bit11:10] SIN9S: SIN9 Input Select bits Selects input for SIN9. Description Reading Reads out the register value. Uses SIN9_0 at the input pin of MFS ch.9 SIN. [Initial value] Same as Writing 00. Writing Uses SIN9_1 at the input pin of MFS ch.9 SIN. Uses SIN9_2 at the input pin of MFS ch.9 SIN.
Page 682 CHAPTER 12: I/O Port [bit3:2] SCS7B : SCS7 Input/Output Select bits Selects input/output for SCS7. The setting method of this bit is different from product TYPE.  TYPE1-M4 and TYPE2-M4 products. Description Reading Reads out the register value. Uses SCS7_0 at the input pin of MFS ch.7 SCS. Does not produce output.
Page 683 CHAPTER 12: I/O Port  TYPE3-M4, TYPE4-M4, TYPE5-M4 products. Description Reading Reads out the register value. Uses SCS60_0 at the input pin of MFS ch.6 SCS. Does not produce output. [Initial value] Uses SCS60_0 at the input pin of MFS ch.6 SCS Uses SCS60_0 at the output pin.
Page 684: Extended Pin Function Setting Register 17 (Epfr17)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 17 (EPFR17) 4.25 The EPFR08 register assigns functions of multi-function serial channel 12, channel 13, channel 14, and channel 15. Register Configuration Field Reserved SCK15B SOT15B Attribute Initial value Field SIN15S SCK14B SOT14B SIN14S...
Page 685 CHAPTER 12: I/O Port [bit25:24] SOT15B: SOT15 Input/Output Select bits Selects input/output for SOT15. Description Reading Reads out the register value. Uses SOT15_0 at the input pin of MFS ch.15 SOT. Does not produce output. [Initial value] Uses SOT15_0 at the input pin of MFS ch.15 SOT. Uses SOT15_0 at the output pin.
Page 686 CHAPTER 12: I/O Port [bit17:16] SIN14S: SIN14 Input Select bits Selects input for SIN14. Description Reading Reads out the register value. Uses SIN14_0 at the input pin of MFS ch.14 SIN. [Initial value] Same as Writing 00. Writing Uses SIN14_1 at the input pin of MFS ch.14 SIN. Uses SIN14_2 at the input pin of MFS ch.14 SIN.
Page 687 CHAPTER 12: I/O Port [bit9:8] SCK12B: SCK12 Input/Output Select bits Selects input/output for SCK12. Description Reading Reads out the register value. Uses SCK12_0 at the input pin of MFS ch.12 SCK. Does not produce output. [Initial value] Uses SCK12_0 at the input pin of MFS ch.12 SCK. Uses SCK12_0 at the output pin.
Page 688: Extended Pin Function Setting Register 18 (Epfr18)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 18 (EPFR18) 4.26 The EPFR18 register assigns functions of QPRC and SD Card IF and HDMI-CEC peripheral pins. Register Configuration Field Reserved SDWPS SDCDS SDDATA3B Attribute Initial value Field SDDATA2B SDDATA1B SDDATA0B SDCMDB Attribute...
Page 689 CHAPTER 12: I/O Port [bit25:24] SDDATA3B: SDDATA3 input/output select bits Selects input/output for S_DATA3. Description Reading Reads out the register value. Uses S_DATA3_0 at the input pin of SD CARD IF. [Initial value] Does not produce output. Uses S_DATA3_0 at the input pin of SD CARD IF. Writing Uses S_DATA3_0 at the output pin.
Page 690 CHAPTER 12: I/O Port [bit17:16] SDCMDB: S_CMD input/output select bits Selects input/output for S_CMD. Description Reading Reads out the register value. Uses S_CMD_0 at the input pin of SD CARD IF. [Initial value] Does not produce output. Uses S_CMD_0 at the input pin of SD CARD IF. Writing Uses S_CMD_0 at the output pin.
Page 691 CHAPTER 12: I/O Port [bit5:4] QAIN3S: QDU-ch3 AIN input select bits Selects input for QDU-ch3 AIN. Description Reading Reads out the register value. Uses AIN3_0 at the input pin of AIN of QDU-ch.3. [Initial value] Uses AIN3_0 at the input pin of AIN of QDU-ch.3. (Same as writing 00.) Writing Uses AIN3_1 at the input pin of AIN of QDU-ch.3.
Page 692: Extended Pin Function Setting Register 19 (Epfr19)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 19 (EPFR19) 4.27 The EPFR19 register is the reserved register. Register Configuration Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Register Function [bit31:0] Reserved: Reserved bits 0x00000000 is read from these bits.
Page 693: Extended Pin Function Setting Register 20 (Epfr20)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 20 (EPFR20) 4.28 The EPFR 20 register assigns functions of external bus peripheral pins. Register Configuration Field Reserved UED31B Attribute Initial value Field UED30B UED29B UED28B UED27B UED26B UED25B UED24B UED23B Attribute Initial value Field...
Page 694 CHAPTER 12: I/O Port [bit22] UED29B: UED29B input/output select bit Selects input/output for external bus data 29. Description Reading Reads out the register value. Does not produce output of user external bus MADATA29 [Initial value] Connects the input of user external bus MADATA29 to the pin. Writing Produces output of user external bus MADATA29.
Page 695 CHAPTER 12: I/O Port Selects input/output for external bus data 24. Description Reading Reads out the register value. Does not produce output of user external bus MADATA24. [Initial value] Connects the input of user external bus MADATA24 to the pin. Writing Produces output of user external bus MADATA24.
Page 696 CHAPTER 12: I/O Port Description Reading Reads out the register value. Does not produce output of user external bus MADATA19. [Initial value] Connects the input of user external bus MADATA19 to the pin. Writing Produces output of user external bus MADATA19. Connects the input of user external bus MADATA19 to the pin.
Page 697 CHAPTER 12: I/O Port [bit7] UEDQM3E: UEDQM3E output select bit Selects output for external bus MDQM3. Description Reading Reads out the register value. Does not produce output of user external bus MDQM3. [Initial value] Writing Produces output of user external bus MDQM3. [bit6] UEDQM2E: UEDQM2E output select bit Selects output for external bus MDQM2.
Page 698 CHAPTER 12: I/O Port [bit1] UESMCEE: UESMCEE output select bit Selects output for external bus SDRAM MSDCKE. Description Reading Reads out the register value. Does not produce output of user external bus MSDCKE [Initial value] Writing Produces output of user external bus MSDCKE. [bit0] UESMCKE: UESMCKE output select bit Selects output for external bus SDRAM MADCLK.
Page 699: Extended Pin Function Setting Register 21 (Epfr21)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 21 (EPFR21) 4.29 The EPFR21 register is the reserved register. Register Configuration Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Register Function [bit31:0] Reserved: Reserved bits 0x00000000 is read from these bits.
Page 700: Extended Pin Function Setting Register 22 (Epfr22)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 22 (EPFR22) 4.30 The EPFR22 register is the reserved register. Register Configuration Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Register Function [bit31:0] Reserved: Reserved bits 0x00000000 is read from these bits.
Page 701: Extended Pin Function Setting Register 23 (Epfr23)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 23 (EPFR23) 4.31 The EPFR23 register assigns functions of multi-function serial ch.6 to ch.7. Register Configuration Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field SCS73E SCS72E SCS71E SCS70E Attribute Initial value Field...
Page 702 CHAPTER 12: I/O Port [bit11:10] SCS71E: SCS71 Input Select bits Selects input/output for SCS71. For TYPE3-M4, TYPE5-M4 products, set this bit with SCS7B of EPFR16. Description Reading Reads out the register value. Does not produce output of MFS ch7 SCS71. [Initial value] Uses SCS71_0 at the output pin of MFS ch.7 SCS71.
Page 703 CHAPTER 12: I/O Port Selects input/output for SCS60. For TYPE3-M4, TYPE4-M4, TYPE5-M4 products, set this bit with SCS6B of EPFR16. Description Reading Reads out the register value. Does not produce output of MFS ch6 SCS60. [Initial value] Uses SCS60_0 at the output pin of MFS ch.6 SCS60. Writing Uses SCS60_1 at the output pin of MFS ch.6 SCS60.
Page 704: Extended Pin Function Setting Register 24 (Epfr24)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 24 (EPFR24) 4.32 The EPFR24 register assigns functions of I2S. Register Configuration Field Reserved I2SM4_SDO1E I2SM4_SDI1S Attribute Initial value Field I2SM4_WS1B I2SM4_SCK1B I2SM4_MCLK1E I2SM4_MCLK1S Attribute Initial value Field Reserved I2SM4_SDO0E I2SM4_SDI0S Attribute Initial value Field...
Page 705 CHAPTER 12: I/O Port [bit23:22] I2SM4_WS1B: I2SWS1 Input/Output Select bits Selects input/output for I2SWS1. Description Reading Reads out the register value. Does not produce input/output of I2S ch.1 I2SWS. [Initial value] Uses I2SWS1_0 at the input/output pin of I2S ch.1 I2SWS. Writing Setting is prohibited.
Page 706 CHAPTER 12: I/O Port [bit11:10] I2SM4_SDO0E: I2SDO0 Output Select bits Selects output for I2SDO0. Description Reading Reads out the register value. Does not produce output of I2S ch.0 I2SDO. [Initial value] Uses I2SDO0_0 at the output pin of I2S ch.0 I2SDO. Writing Setting is prohibited.
Page 707 CHAPTER 12: I/O Port [bit3:2] I2SM4_MCLK0E: I2SMCLK0 Output Select bits Selects output for I2SMCLK0. Description Reading Reads out the register value. Does not produce output of I2S ch.0 I2SMCLK. [Initial value] Uses I2SMCLK0_0 at the output pin of I2S ch.0 I2SMCLK. Writing Setting is prohibited.
Page 708: Extended Pin Function Setting Register 25 (Epfr25)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 25 (EPFR25) 4.33 The EPFR25 register assigns functions of CAN-FD. Register Configuration Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved MCTX2E MCRX2S Attribute Initial value Register Function...
Page 709: Extended Pin Function Setting Register 26 (Epfr26)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 26 (EPFR26) 4.34 The EPFR26 register assigns functions of Hi-Speed SPI controller. Register Configuration Field Reserved Attribute Initial value Field Reserved Q_IO3B Attribute Initial value Field Q_IO2B Q_IO1B Q_IO0B Q_IO3E Attribute Initial value Field Q_IO2E...
Page 710 CHAPTER 12: I/O Port [bit13:12] Q_IO1B: Q_IO1 (GE_SPDQ1) Input/Output Select bits Selects input/output for Q_IO1. TYPE4-M4 products signal in parentheses are eligible. Description Reading Reads out the register value. Does not produce input/output of Hi-Speed SPI controller Q_IO1. [Initial value] Uses Q_IO1_0 at the input/output pin of Hi-Speed SPI controller Q_IO1.
Page 711 CHAPTER 12: I/O Port [bit3:2] Q_CS0E: Q_CS0 (GE_SPCSX0) Output Select bits Selects output for Q_CS0 (GE_SPCSX0). TYPE4-M4 products signal in parentheses are eligible. Description Reading Reads out the register value. Does not produce output of Hi-Speed SPI controller Q_CS0. [Initial value] Uses Q_CS0_0 at the output pin of Hi-Speed SPI controller Q_CS0.
Page 712: Extended Pin Function Setting Register 27 (Epfr27)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 27 (EPFR27) 4.35 EPFR27 register sets the function assignment to HyperBus Interface pins. Register Configuration Field HBINTXS HBRSTOXS HBRESETXE HBWPXE Attribute Initial value Field HBDQ7B HBDQ6B HBDQ5B HBDQ4B Attribute Initial value Field HBDQ3B HBDQ2B...
Page 713 CHAPTER 12: I/O Port [bit27:26] HBRESETXE: GE_HBRESETX Output Select bits Selects output for GE_HBRESETX. Description Reading Reads out the register value. Does not produce output of HyperBus Interface GE_HBRESETX. [Initial value] Uses GE_HBRESETX_0 at the output pin of HyperBus Interface GE_HBRESETX. Writing Setting is prohibited.
Page 714 CHAPTER 12: I/O Port [bit17:16] HBDQ4B: GE_HBDQ4 Input/Output Select bits Selects input/output for GE_HBDQ4. Description Reading Reads out the register value. Does not produce input/output of HyperBus Interface GE_HBDQ4. [Initial value] Uses GE_HBDQ4_0 at the input/output pin of HyperBus Interface GE_HBDQ4. Writing Setting is prohibited.
Page 715 CHAPTER 12: I/O Port [bit7:6] HBRWDSB: GE_ HBRWDS Input/Output Select bits Selects input/output for GE_ HBRWDS. Description Reading Reads out the register value. Does not produce input/output of HyperBus Interface GE_ HBRWDS. [Initial value] Uses GE_ HBRWDS_0 at the input/output pin of HyperBus Interface GE_ HBRWDS. Writing Setting is prohibited.
Page 716: Extended Pin Function Setting Register 28 (Epfr28)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 28 (EPFR28) 4.36 EPFR28 register sets the function assignment to GDC Panel pins. Register Configuration Field PNL_PD15E PNL_PD14E PNL_PD13E PNL_PD12E Attribute Initial value Field PNL_PD11E PNL_PD10E PNL_PD9E PNL_PD8E Attribute Initial value Field PNL_PD7E PNL_PD6E...
Page 717 CHAPTER 12: I/O Port [bit27:26] PNL_PD13E: PNL_PD13 Output Select bits Selects output for PNL_PD13. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_PD13. [Initial value] Uses PNL_PD13_0 at the output pin of GDC Panel PNL_PD13. Writing Setting is prohibited.
Page 718 CHAPTER 12: I/O Port [bit17:16] PNL_PD8E: PNL_PD8 Output Select bits Selects output for PNL_PD8. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_PD8. [Initial value] Uses PNL_PD8_0 at the output pin of GDC Panel PNL_PD8. Writing Setting is prohibited.
Page 719 CHAPTER 12: I/O Port [bit7:6] PNL_PD3E: PNL_PD3 Output Select bits Selects output for PNL_PD3. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_PD3. [Initial value] Uses PNL_PD3_0 at the output pin of GDC Panel PNL_PD3. Writing Setting is prohibited.
Page 720: Extended Pin Function Setting Register 29 (Epfr29)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 29 (EPFR29) 4.37 EPFR29 register sets the function assignment to GDC Panel pins. Register Configuration Field PNL_TSIG11E PNL_TSIG10E PNL_TSIG9E PNL_TSIG8E Attribute Initial value Field PNL_TSIG7E PNL_TSIG6E PNL_TSIG5E Reserved Attribute Initial value Field PNL_PD23E PNL_PD22E...
Page 721 CHAPTER 12: I/O Port [bit27:26] PNL_TSIG9E: PNL_TSIG9 Output Select bits Selects output for PNL_TSIG9. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_TSIG9. [Initial value] Uses PNL_TSIG9_0 at the output pin of GDC Panel PNL_TSIG9. Writing Setting is prohibited.
Page 722 CHAPTER 12: I/O Port [bit17:16] Reserved: Reserved bits 0b00 is read from these bits. When writing these bits, set them to 0b00. [bit15:14] PNL_PD23E: PNL_PD23 Output Select bits Selects output for PNL_PD23. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_PD23. [Initial value] Uses PNL_PD23_0 at the output pin of GDC Panel PNL_PD23.
Page 723 CHAPTER 12: I/O Port [bit7:6] PNL_PD19E: PNL_PD19 Output Select bits Selects output for PNL_PD19. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_PD19. [Initial value] Uses PNL_PD19_0 at the output pin of GDC Panel PNL_PD19. Writing Setting is prohibited.
Page 724: Extended Pin Function Setting Register 30 (Epfr30)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 30 (EPFR30) 4.38 EPFR30 register sets the function assignment to GDC Panel pins. Register Configuration Field Reserved PNL_TSIG4E Attribute Initial value Field PNL_TSIG3E PNL_TSIG2E PNL_TSIG1E PNL_TSIG0E Attribute Initial value Field Reserved PNL_LH_SYNCE PNL_FV_SYNCE Attribute...
Page 725 CHAPTER 12: I/O Port [bit21:20] PNL_TSIG2E: PNL_TSIG2 Output Select bits Selects output for PNL_TSIG2. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_TSIG2. [Initial value] Uses PNL_TSIG2_0 at the output pin of GDC Panel PNL_TSIG2. Writing Setting is prohibited.
Page 726 CHAPTER 12: I/O Port [bit9:8] PNL_FV_SYNCE: PNL_ FV_SYNC Output Select bits Selects output for PNL_FV_SYNC. Description Reading Reads out the register value. Does not produce output of GDC Panel PNL_FV_SYNC. [Initial value] Uses PNL_FV_SYNC_0 at the output pin of GDC PNL_FV_SYNC. Writing Setting is prohibited.
Page 727 CHAPTER 12: I/O Port Notes: − This register does not exist in TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE5-M4, TYPE6-M4 products. − This register is not initialized by deep standby transition reset. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 728: Extended Pin Function Setting Register 33 (Epfr33)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 33 (EPFR33) 4.39 The EPFR33 register assigns functions of Smart Card Interface. Register Configuration Field Reserved CLK1E VCC1E Attribute Initial value Field VPEN1E RST1E DATA1B CIN1S Attribute Initial value Field Reserved CLK0E VCC0E Attribute...
Page 729 CHAPTER 12: I/O Port [bit23:22] VPEN1E: IC1_VPEN Output Select bits Selects output for IC1_VPEN. Description Reading Reads out the register value. Does not produce output of Smart Card Interface ch.1 VPEN. [Initial value] Uses IC1_VPEN_0 at the output pin of Smart Card Interface ch.1 VPEN. Writing Uses IC1_VPEN_1 at the output pin of Smart Card Interface ch.1 VPEN.
Page 730 CHAPTER 12: I/O Port [bit11:10] CLK0E: IC0_CLK Output Select bits Selects output for IC0_CLK. Description Reading Reads out the register value. Does not produce output of Smart Card Interface ch.0 CLK. [Initial value] Uses IC0_CLK_0 at the output pin of Smart Card Interface ch.0 CLK. Writing Uses IC0_CLK_1 at the output pin of Smart Card Interface ch.0 CLK.
Page 731 CHAPTER 12: I/O Port [bit1:0] CIN0S: IC0_CIN Input Select bits Selects input for IC0_CIN. Description Reading Reads out the register value. Uses IC0_CIN_0 at the input pin of Smart Card Interface ch.0 CIN. [Initial value] Uses IC0_CIN_0 at the input pin of Smart Card Interface ch.0 CIN. Writing Uses IC0_CIN_1 at the input pin of Smart Card Interface ch.0 CIN.
Page 732: Extended Pin Function Setting Register 35 (Epfr35)
CHAPTER 12: I/O Port Extended Pin Function Setting Register 35 (EPFR35) 4.40 The EPFR35 register assigns functions of MFS-I2S ch.1. Register Configuration Field Reserved SDO1E SDI1S Attribute Initial value Field WS1B SCK1B MCK1E MCK1S Attribute Initial value Field Reserved Attribute Initial value Field Reserved...
Page 733 CHAPTER 12: I/O Port [bit23:22] WS1B: MI2SWS1 Output Select bits Selects output for MI2SWS1. Description Reading Reads out the register value. Does not produce output of MFS-I2S ch.1 WS. [Initial value] Uses MI2SWS1_0 at the output pin of MFS-I2S ch.1 WS. Writing Uses MI2SWS1_1 at the output pin of MFS-I2S ch.1 WS.
Page 734: Special Port Setting Register (Spsr)
CHAPTER 12: I/O Port Special Port Setting Register (SPSR) 4.41 The SPSR register sets a pin as a signal pin of special functions. Register Configuration Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved USB1C...
Page 735 CHAPTER 12: I/O Port [bit3:2] MAINXC: Main Clock (Oscillation) Pin Setting Register These bits set a pin as a main clock (oscillation) pin. Description Reading Reads out the register value. Does not use two pins of X0 and X1 as main clock (oscillation) pins but as digital input/output pins.
Page 736: Port Pseudo Open Drain Setting Register (Pzrx)
CHAPTER 12: I/O Port Port Pseudo Open Drain Setting Register (PZRx) 4.42 PZRx register makes I/O port Hi-Z when output is High level and sets pseudo open drain control. List of PZR register configuration Initial value Attribute Reserved PZR0 0x0000 Reserved PZR1 0x0000...
Page 737 CHAPTER 12: I/O Port Notes: − The "x" description of PZRx is wildcard. It shows PZR0, PZR1, PZR2, and so on. − The function of the PZR register is implemented only in some specific pins. Only pins described as "PZR register control is enabled" in remarks column of I/O circuit type of Data Sheet can control open drain.
Page 738: Port Drive Capability Select Register (Pdsrx)
CHAPTER 12: I/O Port Port Drive capability Select Register (PDSRx) 4.43 PDSRx register selects drive capability of I/O port. List of PZR register configuration Corresponded Initial value Attribute port Reserved PDSR0 0x0000 P0F to P00 Reserved PDSR1 0x0000 P1F to P10 Reserved PDSR2 0x0000...
Page 739: Usage Precautions
CHAPTER 12: I/O Port Usage Precautions This section describes precautions for using the I/O port.  ON/OFF of the Pull-up Resistance When SPL=1 SPL is a signal for turning a pin into Hi-Z state during standby mode. − When SPL=0 Normal operations −...
Page 740 CHAPTER 12: I/O Port When there are some multi-function serial inputs/outputs, set each input/output to the port of the same group. "The port of the same group" means that relocate function numbers attached to the pin name are the same, just like xxx_0 or yyy_1. Table 5-1 shows an example setting.
Page 741: Chapter 13: Crc (Cyclic Redundancy Check)
CHAPTER 13: CRC (Cyclic Redundancy Check) This chapter explains the CRC functions. 1. Overview of CRC 2. CRC Operations 3. CRC Registers FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 742: Overview Of Crc
CHAPTER 13: CRC (Cyclic Redundancy Check) Overview of CRC The CRC (Cyclic Redundancy Check) is an error detection system. The CRC code is a remainder after an input data string is divided by the pre-defined generator polynomial, assuming the input data string is a high order polynomial.
Page 743: Crc Operations
CHAPTER 13: CRC (Cyclic Redundancy Check) CRC Operations This section provides an overview of CRC operations. CRC Definition  CCITT CRC16 Standard Generator polynomial 0x1021 (CRCCR:CRC32=0) Initial value 0xFFFF Final XOR value 0x0000 (CRCCR:FXOR=0) bit order MSB First (CRCCR:LSBFST=0) Output bit order MSB First (CRCCR:CRCLSF=0) (The input-output byte order can be specified arbitrarily.)
Page 744: Crc Calculation Sequence
CHAPTER 13: CRC (Cyclic Redundancy Check) CRC Calculation Sequence Figure 2-1 shows the CRC calculation sequence. In this section, it is assumed that the Initial Value Register (CRCINIT) setting, CRC16 or CRC32 mode selection (CRCCR:CRC32), and byte- or bit-order setting (CRCCR:LTLEND, CRCCR:LSBFST) have already been configured. If the initial value can be set to 0xFFFFFFFF, the Initial Value Register (CRCINIT) setting can be omitted.
Page 745: Crc Use Examples
CHAPTER 13: CRC (Cyclic Redundancy Check) CRC Use Examples Figure 2-2 to Figure 2-5 show CRC use examples. Use Example 1 CRC16, Byte Input Fixed Figure 2-2 Use Example 1 (CRC16, Byte Input Fixed, Core Byte Order : Big Endian) //********************************************* // CRC16 (CRC ITU-T) polynomial:...
Page 746 CHAPTER 13: CRC (Cyclic Redundancy Check) Use Example 2 CRC16, Different Input Bit Widths Mixed Figure 2-3 Use Example 2 (CRC16, Different Input Bit Widths Mixed, Core Byte Order: Big Endian) //********************************************* // CRC16 (CRC ITU-T) polynomial: 0x1021 (Assumed as follows) initial value: 0xFFFF CRCCR.CRC32:...
Page 747 CHAPTER 13: CRC (Cyclic Redundancy Check) Use Example 3 CRC32, Byte Order: Big Endian Figure 2-4 Use Example 3 (CRC32, Byte Order: Big Endian) //********************************************** // CRC32 (IEEE-802.3) // polynomial: 0x04C11DB7 (Assumed as follows) // initial value: 0xFFFF_FFFF // CRCCR.CRC32 1 // CRC32 // CRCCR.LTLEND: 0 // big endian...
Page 748 CHAPTER 13: CRC (Cyclic Redundancy Check) Use Example 4 CRC32, Byte Order: Little Endian Figure 2-5 Use Example 4 (CRC32, Byte Order: Little Endian) //********************************************** // CRC32 (IEEE-802.3) // polynomial: 0x04C11DB7 (Assumed as follows) // initial value: 0xFFFF_FFFF // CRCCR.CRC32 1 // CRC32 // CRCCR.LTLEND: 1 // little endian...
Page 749: Crc Registers
CHAPTER 13: CRC (Cyclic Redundancy Check) CRC Registers This section provides a list of CRC registers. CRC Registers Table 3-1 CRC Register List Abbreviation Register Name Reference CRCCR CRC Control Register CRCINIT Initial Value Register CRCIN Input Data Register CRCR CRC Register FM4 Peripheral Manual, Doc.
Page 750: Crc Control Register (Crccr)
CHAPTER 13: CRC (Cyclic Redundancy Check) CRC Control Register (CRCCR) The CRC Control Register (CRCCR) is used to control CRC calculation. Field Reserved FXOR CRCLSF CRCLTE LSBFST LTLEND CRC32 INIT Attribute Initial value [bit7] Reserved: Reserved bit The read value is "0". Be sure to write "0"...
Page 751 CHAPTER 13: CRC (Cyclic Redundancy Check) [bit3] LSBFST: bit-order setting bit This is a bit-order setting bit. This bit is used to specify the head bit of a byte (8 bits). Set "0" to specify MSB First and set "1" to specify LSB First.
Page 752: Initial Value Register (Crcinit)
CHAPTER 13: CRC (Cyclic Redundancy Check) Initial Value Register (CRCINIT) The Initial Value Register (CRCINIT) is used to save the initial values for CRC calculation. Field D[31:0] Attribute Initial value 0xFFFFFFFF [bit31:0] D[31:0] : Initial value bits These bits are used to save the initial values for CRC calculation. Write the initial values for CRC calculation to this register.
Page 753: Input Data Register (Crcin)
CHAPTER 13: CRC (Cyclic Redundancy Check) Input Data Register (CRCIN) The Input Data Register (CRCIN) is used to set input data for CRC calculation. Field D[31:0] Attribute Initial value 0x00000000 [bit31:0] D[31:0] : Input data bits These bits are used to set input data for CRC calculation. Write input data for CRC calculation to this register.
Page 754: Crc Register (Crcr)
CHAPTER 13: CRC (Cyclic Redundancy Check) CRC Register (CRCR) The CRC Register (CRCR) is used to output the CRC calculation result. This register must be initialized before start calculating. Field D[31:0] Attribute Initial value 0xFFFFFFFF [bit31:0] D[31:0] : CRC bits These bits are used to read the CRC calculation result.
Page 755: Chapter 14: External Bus Interface
CHAPTER 14: External Bus Interface This chapter explains the functions and operations of the external bus interface. 1. Overview of External Bus Interface 2. Block Diagram 3. Operations 4. Connection Examples 5. Setup Procedure Example 6. Registers 7. Usage Precautions FM4 Peripheral Manual, Doc.
Page 756: Overview Of External Bus Interface
CHAPTER 14: External Bus Interface Overview of External Bus Interface This section explains an overview of the external bus interface. The external bus interface allows connections with SRAM/Flash memory/SDRAM outside of the device. External Bus Interface Features The features of the external bus interface across the products are as follows: −...
Page 757 CHAPTER 14: External Bus Interface Access Timing and AC Specifications  Asynchronous Accesses The external bus interface performs read data latching to the timing of the output enable (MOEX) signal in reading data. Make the target device to perform the write data latching to the timing of the write enable (MWEX) signal in writing data.
Page 758: Block Diagram
CHAPTER 14: External Bus Interface Block Diagram This section explains the block diagram of the external bus interface. Figure 2-1 External Bus Interface Block Diagram This LSI AHB Bus APB Bus AHB Interface Register Block Control Block External Bus Interface External Memory Bus ...
Page 759 CHAPTER 14: External Bus Interface Figure 2-2 External Bus Interface Block Diagram (Clock System Overview Diagram) FM4 MCU External bus interface HCLK External Bus interface Logic part (between 1/1 and 1/16 frequency) MCLKOUT(*) MSDCLK(*) Notes: − HCLK indicates a master clock. For the details, see the chapter Clock. −...
Page 760 CHAPTER 14: External Bus Interface  Pin List The pin list of the external bus interface is shown in Table 2-1. Table 2-1 Pin List of External Bus Interface Pin Name Function MAD[24:0] Address output pins Data input/output pins MADATA[31:0] (These pins will be changed to input/output pins for address/data in multiplex mode.) MCSX[7:0] Chip select pins for SRAM and flash memory...
Page 761: Operations
CHAPTER 14: External Bus Interface Operations The section explains the operations of the external bus interface. 3.1. Bus Access Mode 3.2. SRAM and NOR Flash Memories Access 3.3. NAND Flash Memory Access 3.4. Issue of an 8-bit NAND Flash Memory Read/write Command 3.5.
Page 762: Bus Access Mode
CHAPTER 14: External Bus Interface Bus Access Mode The following explains bus access mode. Access Method The external bus interface allows selecting separate mode or multiplex mode with the register.  Separate Mode This mode outputs the address to the MAD[24:0] pins and inputs/outputs the data to the MADATA[31:0] pins.
Page 763 CHAPTER 14: External Bus Interface  Multiplex Mode This mode inputs/outputs the address/data to MADATA[15:0] pins in a time division manner. As the part of address pins and data pins are shared, fewer pins are used for accessing the external memories. An example of waveform in multiplex mode is shown in Figure 3-2.
Page 764 CHAPTER 14: External Bus Interface Bus Access Modes and Functions Setups Bus access modes and the functions setups are shown in Table 3-2. Table 3-2 Bus Access Modes and Functions Setups (Products other than TYPE0) Bus Access Mode Clock output External RDY Page read NAND Flash...
Page 765 CHAPTER 14: External Bus Interface Bus Size Conversion and Continuous Access If an access with an externals bus width narrower than the CPU access width is made, the access will be divided and converted into continuous accesses which continuously change the address only with holding MCSX="L".
Page 766 CHAPTER 14: External Bus Interface Table 3-3 shows the mapping between the CPU access width and the external bus width. Table 3-3 CPU Access Width and External Bus Width Mapping Access from CPU Access to External Bus External Output Value Valid Data at Output Value Bus Width...
Page 767: Sram And Nor Flash Memories Access
CHAPTER 14: External Bus Interface SRAM and NOR Flash Memories Access The following explains SRAM and NOR Flash memories access. Memory Access The target device for the SRAM and NOR Flash memories access will be determined with the MCSX [7:0]/address outputs. After that, outputting MOEX/MWEX will make a read/write to the target device. Pins Used SRAM and NOR Flash memory accesses require the pins shown in Table 3-4.
Page 768 CHAPTER 14: External Bus Interface Page Read for 16-bit NOR Flash Memories The page read operation is available for NOR Flash memories by setting PAGE bit which is the fifth bit of the mode register (MODE0 to MODE7) to 1. The page read will continue read cycle while in reading operation to the boundary of the 16 bytes with MOEX=L retained.
Page 769: Nand Flash Memory Access
CHAPTER 14: External Bus Interface NAND Flash Memory Access The following explains NAND Flash memory access. Memory Access Methods Accesses to the NAND Flash memories will be converted as shown below, based on the base address for the area set to NAND mode. A write access to +0x2000 is converted into the issue of an address for the NAND Flash memory (MNALE is asserted).
Page 770: Read Access To Nand Flash Memory
CHAPTER 14: External Bus Interface 3.3.1 Read Access to NAND Flash Memory Figure 3-6 shows the flowchart of read access to NAND Flash memory. Figure 3-6 Flowchart of Read Access to NAND Flash Memory Turn NAND mode ON  The corresponding chip select signal is fixed to L. Issue a read command 0x00 ...
Page 771: Write (Auto Program) Access
CHAPTER 14: External Bus Interface 3.3.2 Write (Auto Program) Access Figure 3-7 shows the flowchart of the write (auto program) access. Figure 3-7 Write (Auto Program) Access Flowchart  The corresponding chip select signal is fixed to L. Turn NAND mode ON Issue a write command 0x80 ...
Page 772: Auto Block Erase Access
CHAPTER 14: External Bus Interface 3.3.3 Auto Block Erase Access Figure 3-8 shows the flowchart of the auto block erase access. Figure 3-8 Auto Block Erase Access  The corresponding chip select signal is fixed to "L". Turn NAND mode ON Issue an auto block erase setting command ...
Page 773: Issue Of An 8-Bit Nand Flash Memory Read/Write Command
CHAPTER 14: External Bus Interface Issue of an 8-bit NAND Flash Memory Read/write Command Figure 3-9 shows waveforms of the issue of an 8-bit NAND Flash memory read/write command (byte access). Figure 3-9 Waveforms of the Issue of an 8-bit NAND Flash Memory Read/write Command MCLK (MCLKOUT) MCSX[0]...
Page 774: 8-Bit Nand Flash Memory Status Read
CHAPTER 14: External Bus Interface 8-bit NAND Flash Memory Status Read Figure 3-10 shows waveforms of an 8-bit NAND Flash memory status read (byte access). Figure 3-10 Waveforms of an 8-bit NAND Flash Memory Status Read MCLK (MCLKOUT) MCSX[0] MNCLE Read address setup cycle = (0) MNALE Read enable cycle...
Page 775: 8-Bit Nand Flash Memory Data Write
CHAPTER 14: External Bus Interface 8-bit NAND Flash Memory Data Write Figure 3-11 shows waveforms of an 8-bit NAND Flash memory data write. Figure 3-11 8-bit NAND Flash Memory Data Write MCLK (MCLKOUT) MCSX[0] MNCLE MNALE MNREX Write enable cycle Write enable cycle MNWEX MADATA[7:0]...
Page 776: Automatic Wait Setup
CHAPTER 14: External Bus Interface Automatic Wait Setup The following explains the automatic wait function. The automatic wait function sets an automatic wait time per MCSX area for external accesses with the register setups. The parameters to which the automatic wait can be set are shown in Table 3-6 and Table 3-7.
Page 777 CHAPTER 14: External Bus Interface Table 3-7 Automatic Wait Setup List (SDRAM) Available Point Register Name Available Cycle 1 to 3 cycles Number of CAS latency cycles SDTIM:CL (CL+1) Cycle Number of latency cycles between 1 to 8 cycles SDTIM:TRC RASs (TRC+1) Cycle 1 to 4 cycles...
Page 778 CHAPTER 14: External Bus Interface Figure 3-12 Chart Description for Automatic Wait Assignment (Separate Mode) RACC=3 WACC=4 WIDLC=0 RADC=2 RIDLC=0 WADC=2 WWEC=0 Addr ess Addr ess Addr ess Address Read access cycle Write access cycle Figure 3-13 Chart Description for Automatic Wait Assignment (Multiplex Mode) MCLK (MCLKOUT) ALC=2...
Page 779 CHAPTER 14: External Bus Interface Figure 3-15 Chart Description for Automatic Wait Assignment (NOR Flash Memory Page Read) MCLK (MCLKOUT) RACC=1 RACC=1 RACC=1 RACC=1 RACC=1 RACC=1 RACC=1 RACC=1 FRADC=3 MCSX[0] MOEX MAD[24:0] Dat00 Dat02 Dat04 Dat06 Dat08 Dat10 Dat12 MADATA[15:0] Read Read Read...
Page 780 CHAPTER 14: External Bus Interface Notes: − The automatic wait setup will be enabled for all the access modes of external bus interface except for ATIMn:ALES, ALC and ALEW. The setups for the read data and write data must meet the setup and hold specifications.
Page 781: External Rdy
CHAPTER 14: External Bus Interface External RDY The following explains the external RDY function. This function allows extended access cycle inserting wait cycles while L level is input to the MRDY pin. This enables accesses to the low speed external memories. The operation waveform of the RDY signal is shown in Figure 3-18.
Page 782: Sdram Access
CHAPTER 14: External Bus Interface SDRAM Access This section explains SDRAM access. Memory Access In SDRAM access, MCSX[8] address output determines the target device. Then, by outputting MRASX/ MCASX/MSDWEX/MSDCKE , read/write operation is executed to the target device. Pins Used For SDRAM access, use the pins in Table 3-8.
Page 783 CHAPTER 14: External Bus Interface SDRAM Read Access For the operation example of SDRAM read access, see Figure 3-19. Figure 3-19 SDRAM Read Access MSDCLK MCSX[8] MAD[15:0] MRASX TRAS=0 TREFC=2 MCASX TRP=0 TRCD=0 MSDWEX Read 32-bit data Read 8-bit or 16-bit data CL=1 MADATA[15:0] CPU Half Word access...
Page 784 CHAPTER 14: External Bus Interface SDRAM Write Access For the operation example of SDRAM read access, see Figure 3-20. Figure 3-20 SDRAM Write Access MSDCLK MCSX[8] TRAS=0 MRASX TREFC=2 MCASX TRCD=0 TRP=0 MSDWEX TDPL=0 Write 8-bit or 16-bit data Write 32-bit data MADATA CPU Half Word access CPU Word access...
Page 785 CHAPTER 14: External Bus Interface Power-on Sequence By changing SDON bit of SDRAM mode register (SDMODE) from 0 to 1, the power-on sequence is issued and the access to SDRAM is enabled. For the power-on sequence issued, see Figure 3-21. In Figure 3-21, “cycle”...
Page 786 CHAPTER 14: External Bus Interface Refresh Operation When ROFF bit of SDRAM mode register (SDMODE) is 0, the refresh is executed with the setting conditions of Refresh time register (REFTIM). The Refresh time register (REFTIME) can control the interval and count of the refresh and the preceding refresh. Refresh Interval Set the interval to execute refreshes with REFC bit of the Refresh time register (REFTIM).
Page 787 CHAPTER 14: External Bus Interface Power Down Mode Operation When PDON bit of SDRAM mode register (SDMODE) is set to 1, the mode is transferred to Power down mode if the access to SDRAM is not executed in the cycle (MADCLK) specified by Power down count register (PWRDWN).
Page 788: Interrupt Function
CHAPTER 14: External Bus Interface 3.10 Interrupt Function This section explains the error interrupt. SRAM/Flash Memory Error When the access is executed by SRAM/Flash memory error interrupt enable (MEMCERR.SFION=1) to SRAM/Flash memory address area where the mapping is not implemented with the area register, an error interrupt occurs.
Page 789: Access Mode
CHAPTER 14: External Bus Interface 3.11 Access Mode This section explains the access mode. For the read/write access to the external bus interface address area, the following functions area provided to improve the access efficiency: 1. At read access: Preceding access 2.
Page 790 CHAPTER 14: External Bus Interface Read Access To improve the efficiency of the read access of the external bus interface, the preceding read of the next read access is provided. If preceding access is enabled, it will improve read access efficiency because, when external bus interface read access is performed continuously, the internal bus requests received while the internal bus response is WAIT are read to the external device and data is preceded without waiting for internal bus response OK.
Page 791 CHAPTER 14: External Bus Interface Write Access To reduce the write access interval, the mode for implementing the continuous write request is provided. If continuous access is enabled, it will improve write access efficiency because, when write access to the external bus interface is performed continuously, it writes to the external device continuously without waiting for an error response.
Page 792: Sdram Buffer Read (Type3-M4, Type4-M4, Type5-M4, Type6-M4 Products)
CHAPTER 14: External Bus Interface 3.12 SDRAM Buffer Read (TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products) This function is equipped for TYPE3-M4, TYPE4-M4 products. This is not equipped for TYPE1-M4 products. The external bus interface is equipped with built-in buffer of 5 words at most in order to improve efficiency of serial read access to SDRAM.
Page 793 CHAPTER 14: External Bus Interface For the operation example of SDRAM buffer read, see Figure 3-29. Figure 3-29 Operation Example of SDRAM Buffer Read Access conditions − SDRAM 32-bit access − Buffer readout OFF (SDTIM:BOFF): 0b0 (In reading, buffer for SDRAM is enabled) −...
Page 794: Connection Examples
CHAPTER 14: External Bus Interface Connection Examples This section provides an example of connections with external devices. 8-bit SRAM Figure 4-1 shows an example of connecting an 8-bit SRAM. Figure 4-1 Example of 8-bit SRAM Connection 8-bit SRAM 8-bit SRAM  2 Figure 4-2 shows an example of connecting two 8-bit SRAMs.
Page 795 CHAPTER 14: External Bus Interface 16-bit SRAM Figure 4-3 shows an example of connecting a 16-bit SRAM. Figure 4-3 Example of 16-bit SRAM Connection This LSI X16 SRAM 16-bit SRAM MAD [24:1] MCSX [0] MOEX MWEX MDQM [1:0] DQM [1:0] MADATA [15:0] DQ [15:0] In the case where a target device employs a byte mask signal, using the MDQM control will read the data...
Page 796 CHAPTER 14: External Bus Interface 32-Kword x 16-bit SRAM Multiplex Mode Figure 4-5 shows an example of 32K-word x 16-bit SRAM connection for accessing with 16-bit width (in multiplex mode). Figure 4-5 Example of 32K-word x 16-bit SRAM Multiplex Mode Connection 32K-word x 8-bit SRAM Multiplex Mode Figure 4-6 shows an example of connecting two 32K-word x 8-bit SRAMs for accessing with 16-bit width (in multiplex mode).
Page 797 CHAPTER 14: External Bus Interface 16-bit SDRAM Figure 4-7 shows an example of connecting a 16-bit SDRAM. Figure 4-7 Example of 16-bit SDRAM Connection This LSI 16-bit SDRAM [15:14] MAD[15:0] BA[1:0] [11:0] A[11:0] MCSX[8] MRASX MCASX MSDWEX MSDCLK MSDCKE MDQM[1:0] DQM[1:0] MADATA[15:0] DQ[15:0]...
Page 798 CHAPTER 14: External Bus Interface 32-bit SDRAM Figure 4-9 shows an example of connecting a 32-bit SDRAM. Figure 4-9 Example of 32-bit SDRAM Connection This LSI 32-bit SDRAM [15:14] MAD[15:0] BA[1:0] [11:0] A[11:0] MCSX[8] MRASX MCASX MSDWEX MSDCLK MSDCKE MDQM[3:0] DQM[3:0] MADATA[31:0] DQ[31:0]...
Page 799: Setup Procedure Example
CHAPTER 14: External Bus Interface Setup Procedure Example The following explains an example of the external bus interface setup procedure. External bus setup start Executes external bus interface reset Access Peripheral Reset Control Register 0 (MRST0) of peripheral clock gating. Executes external bus interface reset (EXBRST = 1) Releases external bus interface reset (EXBRST = 0) Settings for MSDCLK output gating.
Page 800 CHAPTER 14: External Bus Interface Continue from previous page Settings for SRAM/Flash memory access mode Access SRAM/Flash memory Mode Register (MODE0 to MODE7) Set bus access mode. (MOEXEUP, MPXCSOF, MPXDOFF, ALEINV, MPXMODE, SHRTDOUT, WBMON, RBMON, WDTH[1:0]) Set page access mode (PAGE) Set NAND flash memory mode (NAND) When using multiplex mode, Access ALE Timing Register.
Page 801 CHAPTER 14: External Bus Interface  Setup procedure example of SDRAM refresh count bit Refresh count setup start Operating SDRAM? Use clock division? Is the division ratio of MSDCLK 1/2 ~ 1/8? Set APBC2 bit of APB2 Prescaler Register (APBC2_PSR) so that the frequency of PCLK2 becomes later than the frequency of MSDCLK REFC bit cannot set.
Page 802 CHAPTER 14: External Bus Interface  Setup procedure example of SDRAM command register SDRAM command setup start Use clock division? Is the division ratio of MSDCLK 1/2 to 1/8? SDRAM Command Register (SDCMD) cannot set. Stop SDRAM and set the division ratio of MSDCLK 1/1 to 1/8.
Page 803: Registers
CHAPTER 14: External Bus Interface Registers This section explains the configuration and functions of registers used for the external bus interface. The following explains the registers used for the external bus interface. The bit width of every register is 32. Each register can be accessed by the APB interface with 32-bit width (word). However, because external bus interface control is performed on the AHB side, the setting values are applied to the control registers on the AHB side immediately after the registers are written from the APB interface.
Page 804: Mode 0 Register To Mode 7 Register (Mode0 To Mode7)
CHAPTER 14: External Bus Interface Mode 0 Register to Mode 7 Register (MODE0 to MODE7) The MODE0 to MODE7.registers set the operation mode of SRAM/Flash memory access. Field Reserved Attribute Initial value Field Reserved Attribute Initial value Field Reserved MOEXEUP MPXCSOF MPXDOFF Reserved...
Page 805 CHAPTER 14: External Bus Interface [bit11] MPXDOFF: MPX Address Data OFF This bit is used to select whether or not the address is output to the data lines in multiplex mode. (The address is used from the MAD outputs but set this bit if you use the ALE signal.) Description Outputs the address to the data lines (Initial value).
Page 806 CHAPTER 14: External Bus Interface [bit5] PAGE (PAGE access mode): NOR Flash memory page access mode This bit controls the mode of NOR Flash memory page access. In NOR Flash memory page access mode, the first read access cycle (FRADC) setting can generate the first address cycle.
Page 807 CHAPTER 14: External Bus Interface [bit1:0] WDTH: Data Width These bits specify the data bit width of a device to be connected. Description bit1 bit0 TYPE1-M4, TYPE4-M4, TYPE5-M4, TYPE3-M4 products TYPE6-M4 products 8 bits [Initial value] 8 bits [Initial value] 16 bits 16 bits Setting is prohibited.
Page 808 CHAPTER 14: External Bus Interface Reference Information Specific effects and operations are shown as follows by setting the bits of this register.  MOEXEUP bit: MOEX Width Setup How to set up the MOEX width depends on the MOEXEUP bit setup. In case of MOEXEUP = 0 MCLK RACC...
Page 809 CHAPTER 14: External Bus Interface  MPXCSOF bit: CS Assert Timing Setup This bit is used to select MCSX assertion in multiplex mode from the start of accessing to the end of address output complete (ALC period). In case of MPXCSOF=0 MCLKOUT ALC=2 RACC=1...
Page 810 CHAPTER 14: External Bus Interface  SHRTDOUT bit: Write Data Retention Time in Idle Cycle The WIDLC setup will extend the idle cycle. The write data at that time will also be extended same as the specified period to become Hi-Z in the last cycle.
Page 811 CHAPTER 14: External Bus Interface  MPXDOFF bit: Address Output Availability Setup for Data Line This bit is used to select the address output availability for the data line in multiplex mode. In case of MPXDOFF = 0 MCLK (MCLKOUT) ALC=2 ALC=2 RACC=1...
Page 812: Timing Register 0 To Timing Register 7 (Tim0 To Tim7)
CHAPTER 14: External Bus Interface Timing Register 0 to Timing Register 7 (TIM0 to TIM7) The TIM0 to TIM7 registers set the auto wait time at SRAM/Flash memory access. Field WIDLC WWEC WADC WACC Attribute Initial value 0000 0101 0101 1111 Field RIDLC...
Page 813 CHAPTER 14: External Bus Interface [bit23:20] WADC: Write Address Setup cycle These bits set the number of setup cycles of write address. Write address setup will be used during (WADC+1) cycle. The address is output during the cycle set by these bits, but a write enable signal is not asserted until the set cycle starts.
Page 814 CHAPTER 14: External Bus Interface [bit11:8] FRADC: First Read Address Cycle The functions of these bits are changed by the settings of MODE:PAGE (Page read access setting) and MOEXEUP (MOEX width setting method selection). − When MODE:PAGE=0 (Page read access: OFF) and MOEXEUP=0 These bits do not affect the settings of Page read access and MPEX width.
Page 815 CHAPTER 14: External Bus Interface [bit3:0] RACC: Read Access Cycle These bits set the number of cycles required for read access. Read access cycle will be used during (RACC+1) cycle. The address remains unchanged during the cycle specified by these bits, and the data is captured at the last cycle.
Page 816: Area Register 0 To Area Register 7 (Area0 To Area7)
CHAPTER 14: External Bus Interface Area Register 0 to Area Register 7 (AREA0 to AREA7) The AREA0 to AREA7 registers set the address area by CS0 to CS7. Field Reserved MASK Attribute Initial value 0001111 (16MB width) Field Reserved ADDR Attribute Initial value (from MCSX[0])
Page 817 CHAPTER 14: External Bus Interface [bit7:0] ADDR: Address These bits specify the address to set the corresponding MCSX area. The address is in the fixed 256 MB area assigned to the SRAM/Flash memory interface. The address specified by bit7:0 corresponds to the internal address [27:20]. Notes: Address Space −...
Page 818 CHAPTER 14: External Bus Interface Setup Example ADDR = 0b0001_0000 ([27:20] of the first MCSX address. 0x6100_0000 in this setup.) MASK = 0b000_0011 (Mask bits [26:20] for MCSX. Address area for this setup: 4MB.) Select an area size with the mask setup values. In the example, setup range 0x6100_0000 to 0x613F_FFFF (4MB) will be selected.
Page 819: Ale Timing Register 0 To 7 (Atim0 To Atim7)
CHAPTER 14: External Bus Interface ALE Timing Register 0 to 7 (ATIM0 to ATIM7) The ATIM0 to ATIM7 registers set the automatic wait time of MALE. Field Reserved Attribute Initial value Field Reserved ALEW ALES Attribute Initial value 0100 0101 1111 [bit31:12]Reserved: Reserved bits The read value is undefined.
Page 820: Sdram Mode Register (Sdmode)
CHAPTER 14: External Bus Interface SDRAM Mode Register (SDMODE) This section explains the configuration of SDMODE. Field Reserved Attribute Initial value Field Reserved MSDCLK Attribute Initial value Field BASEL RASEL Attribute Initial value 0001 0011 Field Reserved CASEL Reserved ROFF PDON SDON Attribute...
Page 821 CHAPTER 14: External Bus Interface [bit11:8]RASEL: Row Address Select These bits select the address bit on the internal bus output as row address. Description 0000 MAD[13:0] = Internal address [19:6] 0001 MAD[13:0] = Internal address [20:7] 0010 MAD[13:0] = Internal address [21:8] 0011 MAD[13:0] = Internal address [22:9] [Initial value] 0100...
Page 822 CHAPTER 14: External Bus Interface The following shows the table indicating the relationship between internal address bit and MAD bit at the each setting of CASEL, RASEL, and, BASEL. Internal 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 address Bit name Value CASEL...
Page 823 CHAPTER 14: External Bus Interface [bit1]PDON: Power Down ON This bit set the power down mode. For the detailed operations, see 3.9 Power Down Mode. Description Power Down Mode OFF [Initial value] Power Down Mode ON [bit0] SDON: SDRAM ON This bit enables the access to SDRAM.
Page 824: Refresh Timer Register (Reftim)
CHAPTER 14: External Bus Interface Refresh Timer Register (REFTIM) The REFTIM register sets the refresh timing to SDRAM. Field Reserved NREF Attribute Initial value 00000000 Field REFC Attribute Initial value 0000000000110011 [bit31:25] Reserved: Reserved bits The read value is undefined. Set this bit to 0 when writing.
Page 825 CHAPTER 14: External Bus Interface [bit15:0]REFC: Refresh Count These bits set the interval of refresh operations. The refresh operation starts when the specified cycle count (MSDCLK) elapses. When the writing is executed during accessing, the executing access is aborted and the first refresh operation is implemented to reflect the setting immediately.
Page 826: Power Down Count Register (Pwrdwn)
CHAPTER 14: External Bus Interface Power Down Count Register (PWRDWN) The PWRDWN register set the count value required for SDRAM to transfer to power down mode.. Field Reserved Attribute Initial Value Field Attribute Initial Value 0000000000000000 [bit31:16] Reserved: Reserved bits The read value is undefined.
Page 827: Sdram Timing Register (Sdtim)
CHAPTER 14: External Bus Interface SDRAM Timing Register (SDTIM) The SDTIM register set the automatic wait time at SDRAM access. Field BOFF Reserved TDPL TREFC TRAS Attribute Initial Value 0100 0010 Field TRCD Reserved Attribute Initial Value 0001 0001 0100 [bit31] BOFF: Buffer readout bit This bit sets buffer for SDRAM during read.
Page 828 CHAPTER 14: External Bus Interface [bit19:16] TRAS: RAS active time These bits set the minimum active time of ROW. Description 0000 1 cycle 0010 3 cycles [Initial Value] 0111 8 cycles 1000 Setting is prohibited. 1111 Setting is prohibited. [bit15:12] TRCD: RAS-CAS Delay These bits set the latency from RAS to CAS.
Page 829 CHAPTER 14: External Bus Interface [bit3:2] Reserved: Reserved bits The read value is undefined. Set this bit to 0 when writing. [bit1:0] CL: CAS Latency These bits set CAS latency. Description 1 cycle 2 cycles [Initial Value] 3 cycles Setting is prohibited. FM4 Peripheral Manual, Doc.
Page 830: Sdram Command Register (Sdcmd)
CHAPTER 14: External Bus Interface SDRAM Command Register (SDCMD) The SDCMD register outputs the set value to the external pin for controlling SDRAM. Field PEND Reserved Attribute Initial Value Field Reserved SDCKE SDCS SDRAS SDCAS SDWE Attribute Initial Value Field SDAD[15:8] Attribute Initial Value...
Page 831 CHAPTER 14: External Bus Interface [bit20]SDCKE: SDRAM CKE On detecting the writing to this register, outputs the value set in this bit to MADCKE. [bit19] SDCS: SDRAM Chip Select On detecting the writing to this register, outputs the value set in this bit to MCSX[8]. [bit18] SDRAS: SDRAM RAS On detecting the writing to this register, outputs the value set in this bit to MRASX.
Page 832: Memory Controller Register (Memcerr)
CHAPTER 14: External Bus Interface 6.10 Memory Controller Register (MEMCERR) The MEMCERR register enables SDRAM/Flash memory/SDRAM error interrupt. Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved SDION SFION SDER SFER Attribute Initial Value [bit31:4] Reserved: Reserved bits The read value is undefined.
Page 833 CHAPTER 14: External Bus Interface [bit0] SFER: SRAM/Flash Error This bit is used to indicate that the access is executed to an area not mapped in SRAM/Flash memory area access. At this time, the controller returns an error response to the internal bus and sets this register at the same time.
Page 834: Division Clock Register (Dclkr)
CHAPTER 14: External Bus Interface 6.11 Division Clock Register (DCLKR) The following shows the configuration of DCLKR. Field Reserved Attribute Initial value Field Reserved MCLKON MDIV Attribute Initial value 1111 [bit31:5] Reserved: Reserved bits The read value is undefined. Set this bit to 0 when writing. [bit4] MCLKON: MCLKOUT ON This bit is used to set the output of clock for SRAM/Flash memory (MCLKOUT) enable.
Page 835 CHAPTER 14: External Bus Interface − When you want to output the division clock, clock output setup is required with the use of GPIO. See a separate chapter I/O Port for the details of the setups. To output the MCLKOUT set MCLKON=1. To output MSDCLK, set SDRAM mode register (SDMODE) to MSDCLKOFF=0.
Page 836: Error Status Register (Est)
CHAPTER 14: External Bus Interface 6.12 Error Status Register (EST) The following shows the configuration of EST. Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved WERR Attribute Initial Value [bit31:1] Reserved: Reserved bits The read value is undefined.
Page 837: Write Error Address Register (Wead)
CHAPTER 14: External Bus Interface 6.13 Write Error Address Register (WEAD) The WEAD register enables/disables the preceding read and continuous write access. Field ADDR[31:16] Attribute Initial Value 0x0000 Field ADDR[15:0] Attribute Initial Value 0x0000 [bit31:0] ADDR These bits are used to hold the AHB address at the reception of an error response on write access when the continuous write access of Access Mode Register (AMODE) is enabled (WAEN=1).
Page 838: Error Status Clear Register (Esclr)
CHAPTER 14: External Bus Interface 6.14 Error Status Clear Register (ESCLR) The ESCLR register initializes the error status register (EST) and write error address register (WEAD). Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved WERRCLR...
Page 839: Access Mode Register (Amode)
CHAPTER 14: External Bus Interface 6.15 Access Mode Register (AMODE) The AMODE register enables/disables the preceding read and continuous write access.. Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved Attribute Initial Value Field Reserved WERRCLR Attribute Initial [bit31:1]Reserved: Reserved bits The read value is undefined.
Page 840: Usage Precautions
CHAPTER 14: External Bus Interface Usage Precautions This section explains the usage precautions for the external bus interface.  AC Specifications See the data sheets for the AC specifications in each operating mode.  External Bus Pin and GPIO Setup For using the GPIO as an external bus pin, it is required to set the GPIO to the external bus pin setup with the EPFR register.
Page 841: Chapter 15: Sd Card Interface
CHAPTER 15: SD Card Interface This chapter explains details of the SD card interface. 1. Overview of SD Card Interface 2. Registers 3. MMC Boot Operation 4. MMC Wait IRQ 2. Registers is created based on SD Specifications Part A2 SD Host Controller Simplified Specification Version 3.00 (to be called SD Specifications Part A2 later in this document).
Page 842: Overview Of Sd Card Interface
CHAPTER 15: SD Card Interface Overview of SD Card Interface This section provides an overview of the SD card interface. SD Card Specifications An SD card compliant with the following specifications can be used with the SD card interface.  Part 1 Physical Layer Specification Version 3.01 ...
Page 843: Registers
CHAPTER 15: SD Card Interface Registers This section explains details of registers of the SD card interface. List of Registers of SD Card Interface Table 2-1 List of Registers of SD Card Interface Register Name Reference SDMA System Address / Argument 2 Register Block Size Register Block Size Register Argument 1 Register...
Page 844 CHAPTER 15: SD Card Interface Register Name Reference Power Switching Interrupt Status Enable Register 2.40 Power Switching Interrupt Signal Enable Register 2.41 MMC/eSD Control Register 2.42 MMC Wait IRQ Control Register 2.43 MMC Wait IRQ Control Register 2.44 MMC Response Check Bit Register 2.45 Card Detect Setting Register 2.46...
Page 845: Sdma System Address / Argument 2 Register
CHAPTER 15: SD Card Interface SDMA System Address / Argument 2 Register This register contains the physical system memory address used for DMA transfers or the second argument for the Auto CMD23. SDMA System Address / Argument 2 For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc.
Page 846: Block Size Register
CHAPTER 15: SD Card Interface Block Size Register This register is used to configure the number of bytes in a data block. Transfer Block Size *: The write access to Host SDMA Buffer Boundary is enabled only when the SDMA Support bit in the Capabilities Register is 1.
Page 847: Block Count Register
CHAPTER 15: SD Card Interface Block Count Register This register is used to configure the number of data blocks. Blocks Count For Current Transfer (*) *: This register is divided into two registers, one for writing and another for reading. The register for writing keeps the current value until the next access is made to this register, or a hardware reset is generated or a software reset is generated.
Page 848: Argument 1 Register
CHAPTER 15: SD Card Interface Argument 1 Register This register contains the SD Command Argument. Command Argument For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 849: Transfer Mode Register
CHAPTER 15: SD Card Interface Transfer Mode Register This register is used to control the operation of data transfers. D03 D02 Rsvd For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 850: Command Register
CHAPTER 15: SD Card Interface Command Register The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit (CMD) bit in the Present State Register before writing to this register. Writing to the upper byte of this register triggers SD command generation.
Page 851: Response Register
CHAPTER 15: SD Card Interface Response Register This register is used to store responses from SD cards. Command Response 0 - 31 Command Response 32 - 63 Command Response 64 - 95 Command Response 96 - 127 For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc.
Page 852: Buffer Data Port Register
CHAPTER 15: SD Card Interface Buffer Data Port Register This is a 32-bit data port register for accessing the internal buffer. Buffer Data For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 853: Present State Register
CHAPTER 15: SD Card Interface Present State Register The Host Driver can get status of the Host Controller from this 32-bit read-only register. Rsvd DAT[3:0] Line Signal Level Rsvd Rsvd For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc.
Page 854: Host Control 1 Register
CHAPTER 15: SD Card Interface Host Control 1 Register 2.10 This register is used to control the Host Controller. D04 D03 *1: Only when the ADMA2 Support bit in the Capabilities Register is 1 can 0b10 be written to the DMA Select bits.
Page 855: Power Control Register
CHAPTER 15: SD Card Interface Power Control Register 2.11 This register is used to control the SD Bus voltage. SD Bus Voltage Rsvd Select *: This product enters the power on state it one of the following conditions is met. "0b111"...
Page 856: Block Gap Control Register
CHAPTER 15: SD Card Interface Block Gap Control Register 2.12 This register is used to control the block gap. Rsvd For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 857: Wakeup Control Register
CHAPTER 15: SD Card Interface Wakeup Control Register 2.13 This register is mandatory for the Host Controller, but wakeup functionality depends on the Host Controller system hardware and software. The Host Driver shall maintain voltage on the SD Bus, by setting the SD Bus Power bit to 1 in the Power Control Register, when a wakeup event via a Card Interrupt is desired.
Page 858: Clock Control Register
CHAPTER 15: SD Card Interface Clock Control Register 2.14 At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select bits according to the setting of the Capabilities Register. D07 D06 D04 D03 SDCLK Frequency Select Attribute Description SD Clock Enable...
Page 859: Timeout Control Register
CHAPTER 15: SD Card Interface Timeout Control Register 2.15 At the initialization of the Host Controller, the Host Driver shall set the Data Timeout Counter Value bits according to the setting of the Capabilities Register. Rsvd Data Timeout Counter Value For details of this register, refer to SD Specifications Part A2.
Page 860: Software Reset Register
CHAPTER 15: SD Card Interface Software Reset Register 2.16 A reset pulse is generated when 1 is written to one of the three bits, D02 to D00, in this register. Rsvd *: This bit can be set to 1 only when the Internal Clock Enable bit in the Clock Control Register is 1. For other details of this register, refer to SD Specifications Part A2.
Page 861: Normal Interrupt Status Register
CHAPTER 15: SD Card Interface Normal Interrupt Status Register 2.17 The Normal Interrupt Status Enable Register affects the read access to this register, but the Normal Interrupt Signal Enable Register does not. An interrupt is generated when its interrupt signal is enabled by its corresponding bit in the Normal Interrupt Signal Enable Register and its corresponding interrupt status bit in this register is set to 1.
Page 862: Error Interrupt Status Register
CHAPTER 15: SD Card Interface Error Interrupt Status Register 2.18 Signals defined in this register can be enabled by the Error Interrupt Status Enable Register, but not by the Error Interrupt Signal Enable Register. An interrupt is generated when its interrupt signal is enabled by its corresponding bit in the Error Interrupt Signal Enable Register and its corresponding bit in the Error Interrupt Status Enable Register is set to 1.
Page 863 CHAPTER 15: SD Card Interface Attribute Description Auto CMD19 Error In Re-Tuning Mode 3, this bit indicates that in the execution of Auto CMD19 automatically issued by this SD card interface, a timeout or a bus conflict error has occurred, or re-tuning has failed.
Page 864: Normal Interrupt Status Enable Register
CHAPTER 15: SD Card Interface Normal Interrupt Status Enable Register 2.19 Setting a status enable bit in this register to 1 enables the interrupt status corresponding to that bit. For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc.
Page 865: Error Interrupt Status Enable Register
CHAPTER 15: SD Card Interface Error Interrupt Status Enable Register 2.20 Setting a status enable bit in this register to 1 enables the interrupt status corresponding to that bit. Attribute Description Rsvd There is no Vendor Specific Error Status Enable bit. AHB Master Error Status Enable This bit enables the detection of the AHB master error by the AHB Master Error bit in the Error Interrupt Status Register.
Page 866: Normal Interrupt Signal Enable Register
CHAPTER 15: SD Card Interface Normal Interrupt Signal Enable Register 2.21 This register is used to select which interrupt status is indicate to the Host System as the interrupt. For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc.
Page 867: Error Interrupt Signal Enable Register
CHAPTER 15: SD Card Interface Error Interrupt Signal Enable Register 2.22 This register is used to select which interrupt status is notified to the Host System as the interrupt. Attribute Description Rsvd There is no Vendor Specific Error Signal Enable bit. AHB Master Error Signal Enable This bit enables the output of the interrupt for the AHB master error detected by the AHB Master Error bit in the Error Interrupt Status Register.
Page 868: Auto Cmd Error Status Register
CHAPTER 15: SD Card Interface Auto CMD Error Status Register 2.23 This register is used to indicate the CMD12 response error of Auto CMD12 and the CMD23 response error of Auto CMD23. D06 D05 Rsvd For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc.
Page 869: Host Control 2 Register
CHAPTER 15: SD Card Interface Host Control 2 Register 2.24 This register is used to control the Host Controller. D05 D04 Rsvd *1: Regardless of the setting of this bit, the SD card interface handles all interrupts of interrupt periods except the interrupt period at the data block gap as asynchronous interrupts.
Page 870: Capabilities Register
CHAPTER 15: SD Card Interface Capabilities Register 2.25 This register provides the Host Driver with information specific to the Host Controller implementation. Rsvd Clock Multiplier D47 D46 Timer Count for Re-Tuning D31 D30 D17 D16 Base Clock Frequency For SD Clock Timeout Clock Frequency FM4 Peripheral Manual, Doc.
Page 871 CHAPTER 15: SD Card Interface Attribute Description 63-56 Rsvd Reserved Clock Multiplier This field indicates the multiplier to be used by the clock generator in Programmable Clock Mode. *: This Family does not use this field. Bit value Clock multiplier 55-48 HwInit 0x00...
Page 872 CHAPTER 15: SD Card Interface Attribute Description Driver Type D Support This bit indicates whether Driver Type D is supported in UHS-I. HwInit 1: Driver Type D is supported. 0: Driver Type D is not supported. Driver Type C Support This bit indicates whether Driver Type C is supported in UHS-I.
Page 873 CHAPTER 15: SD Card Interface Attribute Description Voltage Support 3.3V HwInit 1: 3.3 V power supply is supported. 0: 3.3 V power supply is not supported. Suspend/Resume Support HwInit The value of this bit is fixed at 1. The Suspend/Resume function is supported. SDMA Support HwInit 1: SDMA is supported.
Page 874: Maximum Current Capabilities Register
CHAPTER 15: SD Card Interface Maximum Current Capabilities Register 2.26 This register indicates the maximum current capability for each voltage. Rsvd Rsvd Maximum Current for 1.8 V Maximum Current for 3.0 V Maximum Current for 3.3 V Attribute Description 63-32 Rsvd Reserved 31-24...
Page 875: Force Event Register For Auto Cmd Error Status
CHAPTER 15: SD Card Interface Force Event Register for Auto CMD Error Status 2.27 The Force Event Register for Auto CMD Error Status is not a physically implemented register, but is an address to which the settings of the Auto CMD Error Status Register can be written. D06 D05 Rsvd Rsvd...
Page 876: Force Event Register For Error Interrupt Status
CHAPTER 15: SD Card Interface Force Event Register for Error Interrupt Status 2.28 The Force Event Register for Error Interrupt Status is not a physically implemented register, but is an address to which the settings of the Error Interrupt Status Register can be written. Attribute Description Rsvd...
Page 877 CHAPTER 15: SD Card Interface Attribute Description Force Event for Boot Acknowledge Error This bit selects whether the Boot Acknowledge Error bit in the Error Interrupt Status Register is forced to become 1. 1: An interrupt is generated. 0: No interrupt is generated. Set/Reset Condition 1 Write...
Page 878: Adma Error Status Register
CHAPTER 15: SD Card Interface ADMA Error Status Register 2.29 If an ADMA Error Interrupt occurs, the ADMA Error States field in this register holds the ADMA state and the ADMA System Address Register holds the address around the error descriptor. D01 D00 Rsvd For details of this register, refer to SD Specifications Part A2.
Page 879: Adma System Address Register
CHAPTER 15: SD Card Interface ADMA System Address Register 2.30 This register contains the physical Descriptor address used for ADMA data transfer. ADMA System Address For details of this register, refer to SD Specifications Part A2. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 880: Preset Value Registers
CHAPTER 15: SD Card Interface Preset Value Registers 2.31 The Preset Value Registers consist of the following registers for different speed modes as shown below. Offset Preset Value Register Signal Voltage 0x060 Preset Value for Initialization 3.3 V or 1.8 V 0x062 Preset Value for Default Speed 3.3 V...
Page 881: Shared Bus Control Register
CHAPTER 15: SD Card Interface Shared Bus Control Register 2.32 The devices on a shared bus are not intended to be controlled by the Standard Host Driver. D30 D24 D22 D20 D18 D16 D14 D08 D07 D06 D05 D04 D02 D00 Attribute Description Rsvd...
Page 882 CHAPTER 15: SD Card Interface Attribute Description Clock Pin Select This field selects a clock pin output. Settings: 0b000: Clock pins are disabled. 0b001: CLK[1](SD_CLK) is selected. 0b010: CLK[2](SD_CLK) is selected. 18-16 ...: ... "0b111": CLK[7](SD_CLK) is selected. Set/Reset Condition 1 Write System reset Reset (0)
Page 883: Slot Interrupt Status Register
CHAPTER 15: SD Card Interface Slot Interrupt Status Register 2.33 This register indicates the logical OR of the interrupt signal and wakeup signal for each slot. Rsvd Interrupt Signal For Each Slot *: Since this Family does not support multiple slots, it does not have this register. FM4 Peripheral Manual, Doc.
Page 884: Host Controller Version Register
CHAPTER 15: SD Card Interface Host Controller Version Register 2.34 This register indicates the vendor version number and the specification version number. Vendor Version Number Specification Version Number Attribute Description Vendor Version Number This field indicates the vendor version number. 15-08 HwInit The value of this field is fixed at 0x01.
Page 885: Ahb Config Register
CHAPTER 15: SD Card Interface AHB Config Register 2.35 This register controls the configuration of the AHB bus. Rsvd Rsvd INCRSEL Attribute Description 31-07 Rsvd Reserved Big/Little Endian Select This bit selects the endianness from big endian and little endian. 0: Selects little endian.
Page 886 CHAPTER 15: SD Card Interface Attribute Description BSLOCK This bit is for using the bus lock function. 0: Disables the bus lock function. 1: Enables the bus lock function. If this bit is set to 1, the operation of the bus lock selected in the BSLOCKSEL bit in this register is to be executed.
Page 887 CHAPTER 15: SD Card Interface Attribute Description INCRSEL This field selects the AHB fixed length burst type (INCR4/8/16) to be used in the DMA transfer. 0b000: INCR4, INCR8 and INCR16 are not used. 0b001: INCR4 is used. 0b010: INCR8 is used. 0b011: INCR8 and INCR8 are used.
Page 888 CHAPTER 15: SD Card Interface Example 4) If SINEN is 1 and INCRSEL[2:0] are 0b111, if the address in the AHB fixed length burst is on one of the boundaries, the DMA controller uses one of INCR4, INCR8 and INCR16. If the AHB fixed length burst boundaries of INCR4, INCR8 and INCR16 are the same, depending on the transfer size, the DMA controller automatically chooses a burst type according to the following priority order from top to bottom: INCR16, INCR8, INCR4, and executes a DMA transfer.
Page 889: Power Switching Register
CHAPTER 15: SD Card Interface Power Switching Register 2.36 This register controls power switching of the SD card interface. Rsvd Rsvd Attribute Description 31-02 Rsvd Reserved I/O Register Selecting In the case of controlling power switching by software, this bit selects the register used in controlling power switching by software.
Page 890: Tuning Setting Register
CHAPTER 15: SD Card Interface Tuning Setting Register 2.37 This register controls the settings for tuning. Data Timeout Counter Value Rsvd Rsvd For Auto Re-Tuning D12 D11 Rsvd Tuning Point Select *: This Family does not support tuning or re-tuning. Attribute Description 31-28...
Page 891 CHAPTER 15: SD Card Interface Attribute Description CMD Conflict Check Disable This bit enables or disables the CMD bus conflict check. *: For this Family, set this bit to 1. 0: Enables the CMD bus conflict check. 1: Disables the CMD bus conflict check. Set/Reset Condition 1 Write...
Page 892 CHAPTER 15: SD Card Interface Attribute Description Re-Tuning Tap Select This bit selects the number of phases to be processed in re-tuning. 0: 8 phases is processed in re-tuning. 1: 3 phases (current phase and two adjacent phases) is processed in re-tuning. This bit can be set to 1 only when 3 or more bits of the 8 Phase Tuning/Re-Tuning Result bits in the Tuning Status Register are 1.
Page 893 CHAPTER 15: SD Card Interface Attribute Description Tuning Phase Select Enable This bit reselects the phase for tuning/re-tuning through software. 0: Disables reselecting the phase through software. 1: Enables reselecting the phase through software. In the case of determining the phase through software, after tuning/re-tuning has been completed, when there is no communication, set this bit to 1 and select the desired phase in the Tuning Point Select bit simultaneously.
Page 894: Tuning Status Register
CHAPTER 15: SD Card Interface Tuning Status Register 2.38 This register indicates the reference phase selected and re-tuning results. Rsvd Present Tuning point 3 Phase Re-Tuning Rsvd 8 Phase Tuning/Re-Tuning Result Result *: This Family does not support tuning or re-tuning. Attribute Description 31-24...
Page 895 CHAPTER 15: SD Card Interface Attribute Description 3 Phase Re-Tuning Result These bits indicate the result of re-tuning for 3 phases. Bit 10 indicates the result of re-tuning in the phase after the current phase. Bit 09 indicates the result in the phase currently selected. Bit 08 indicates the result of re-tuning in the phase before the current phase.
Page 896: Power Switching Interrupt Status Register
CHAPTER 15: SD Card Interface Power Switching Interrupt Status Register 2.39 This register indicates the respective statuses of 1ms wait interrupt and 5ms wait interrupt. Rsvd Rsvd *: This Family does not support power switching. Attribute Description 31-02 Rsvd Reserved 1ms Wait Interrupt This bit (*1) is used when power switching is controlled through hardware (Auto Power Switching Enable bit in the Power Switching Register = 1).
Page 897: Power Switching Interrupt Status Enable Register
CHAPTER 15: SD Card Interface Power Switching Interrupt Status Enable Register 2.40 This register enables the generation of interrupts caused by the1ms Wait Interrupt bit and the 5ms Wait Interrupt bit in the Power Switching Interrupt Status Register. Rsvd Rsvd *: This Family does not support power switching.
Page 898: Power Switching Interrupt Signal Enable Register
CHAPTER 15: SD Card Interface Power Switching Interrupt Signal Enable Register 2.41 This register enables the generation of interrupts caused by the1ms Wait Interrupt bit and the 5ms Wait Interrupt bit in the Power Switching Interrupt Status Register. Rsvd Rsvd *: This Family does not support power switching.
Page 899: Mmc/Esd Control Register
CHAPTER 15: SD Card Interface MMC/eSD Control Register 2.42 This register controls the operations of the MMC/eSD. Rsvd Rsvd Rsvd Attribute Description 31-19 Rsvd Reserved Boot Mode Enable for MMC This bit enables the boot mode of the MMC. The execution of the boot operation in boot mode is triggered by this bit being 1 and a write access to the Command Register.
Page 900 CHAPTER 15: SD Card Interface Attribute Description Boot Auto Abort Enable for MMC This bit controls whether the SD card interface automatically executes the boot abort of the boot operation of the MMC. If this bit is 1, the SD card interface automatically executes boot abort of the boot operation and alternative boot operation.
Page 901 CHAPTER 15: SD Card Interface Attribute Description MMC DDR Select This bit determines whether the SD card interface executes the DDR transfer on the MMC. To execute a data transfer other than the DDR transfer on the MMC, set this bit to 0. Before setting this bit to 1, set the SD Clock Enable bit in the Clock Control Register and stop SD_CLK.
Page 902 CHAPTER 15: SD Card Interface Attribute Description RST_n Control for MMC This bit sets the value of RSTN for the MMC. The value of this bit becomes the value of RSTN. 0: Selects 0 as the value of RSTN. 1: Selects 1 as the value of RSTN. Set/Reset Condition 1 Write...
Page 903: Mmc Wait Irq Control Register
CHAPTER 15: SD Card Interface MMC Wait IRQ Control Register 2.43 This register controls the operations of the MMC/eSD. Wait IRQ Cancel Response Rsvd Attribute Description Wait IRQ Cancel Response These bits define the content of R5 that cancels the Wait IRQ. They define [15:0] in R5 (48 bits).
Page 904 CHAPTER 15: SD Card Interface Attribute Description Wait IRQ Enable This bit enables or disables the Wait IRQ. With this bit set to 1, if a CMD is issued, the SD card interface generates the Wait IRQ. 0: Disables the Wait IRQ. 1: Enables the Wait IRQ.
Page 905: Mmc Wait Irq Control Register
CHAPTER 15: SD Card Interface MMC Wait IRQ Control Register 2.44 This register defines the content of R5 that cancels the Wait IRQ. Wait IRQ Cancel Response Wait IRQ Cancel Response Attribute Description Wait IRQ Cancel Response These bits define the content of R5 that cancels the Wait IRQ. They define [47:16] in R5 (48 bits).
Page 906: Mmc Response Check Bit Register
CHAPTER 15: SD Card Interface MMC Response Check Bit Register 2.45 This register keeps the respective check bits for response R2 and response R3. Rsvd Rsvd Check Bit 2 Check Bit 1 Attribute Description 31-13 Rsvd Reserved Check Bit 2 These bits keep the check bits for response R2 or response R3 when the MMC is used.
Page 907: Card Detect Setting Register
CHAPTER 15: SD Card Interface Card Detect Setting Register 2.46 This register sets the debounce period in card detection. Rsvd Card Detect Debounce Timer Rsvd Rsvd Counter Value Attribute Description 31-12 Rsvd Reserved Card Detect Debounce Timer Counter Value These bits set the debounce period in card detection. The debounce period is measured according to the division of SDCLK.
Page 908: Mmc Boot Operation
CHAPTER 15: SD Card Interface MMC Boot Operation This section explains details of the MMC boot operation. Example of Controlling Boot Mode (Using ADMA) Figure 3-1 Boot Mode Operation Start Create Descriptor table Set ADMA System Address Register Set MMC/eSD Control Register Set Timeout Control Register Set Host Control 1 Register Set Transfer Mode Register...
Page 909 CHAPTER 15: SD Card Interface (1) Prepare the ADMA descriptor table in the system memory. (2) Set the descriptor address of the ADMA in the ADMA System Address Register. (3) Set the Boot Mode Enable for MMC bit in the MMC/eSD Control Register to 1. In addition, to enable boot acknowledge reception, set the Boot Ack Enable for MMC bit to 1;...
Page 910: Example Of Controlling Alternative Boot Mode (Using Adma)
CHAPTER 15: SD Card Interface Example of Controlling Alternative Boot Mode (Using ADMA) Figure 3-2 Alternative Boot Mode Operation Start Set Command Register Create Descriptor table Wait for Set ADMA System Address Register Command Complete Interrupt (10) Set MMC/eSD Control Register Clear Command Complete Interrupt Status Set Timeout Control Register...
Page 911 CHAPTER 15: SD Card Interface (1) Prepare the ADMA descriptor table in the system memory. (2) Set the descriptor address of the ADMA in the ADMA System Address Register. (3) Set the Boot Mode Enable for MMC bit in the MMC/eSD Control Register to 0. In addition, to enable boot acknowledge reception, set the Boot Ack Enable for MMC bit to 1;...
Page 912: Mmc Wait Irq
CHAPTER 15: SD Card Interface MMC Wait IRQ This section explains details of the MMC Wait IRQ. Example of Controlling Wait IRQ Figure 4-1 MMC Wait Control Start Set MMC Wait IRQ Control Register Set Argument 1 Register Set Command Register Wait for Command Complete Wait IRQ Cancel Interrupt or Wait IRQ Cancel...
Page 913 CHAPTER 15: SD Card Interface (1) Set the Wait IRQ Enable bit in the MMC Wait IRQ Control Register to 1 (Enable). (2) Set the argument of CMD40 (Wait IRQ). (3) Set the Response Type Select bits to 0b10 (Response Length 48). Set the Command CRC Check Enable bit to 1 (Enable).
Page 914: Sdclk
CHAPTER 15: SD Card Interface SDCLK Base Clock frequency that generates SDCLK differs by products. For TYPE1-M4 product, Figure 5-1 shows. Base Clock frequency is same as HCLK frequency. For TYPE3-M4, TYPE5-M4, TYPE6-M4 products, Figure 5-2 shows. Base Clock frequency is HCLK frequency divided by four.
Page 915: Chapter 16: Debug Interface
CHAPTER 16: Debug Interface This chapter explains the function and operation of the debug interface. 1. Overview 2. Pin Description FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 916: Overview And Configuration
CHAPTER 16: Debug Interface Overview and Configuration This family contains a Serial Wire JTAG Debug Port (SWJ-DP). Connecting an ICE to the SWJ-DP allows system debugging. This series also contains an Embedded Trace Macro Cell (ETM) for tracing instructions and a Trace Port Interface Unit (TPIU) that controls trace data.
Page 917: Pin Description
CHAPTER 16: Debug Interface Pin Description This section explains pins. 2.1. Pins for Debug Purposes 2.2. Trace Pins 2.3. Functions Initially Assigned to Pins 2.4. Internal Pull-Ups of JTAG Pins FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 918: Pins For Debug Purposes
CHAPTER 16: Debug Interface Pins for Debug Purposes Five pins (TRSTX, TCK, TMS, TDI, and TDO) are assigned to the JTAG and two pins (SWCLK and SWDIO) are assigned to the serial wire. In addition, a Serial Wire Viewer signal (SWO) that outputs trace data is assigned.
Page 919: Trace Pins
CHAPTER 16: Debug Interface Trace Pins Four trace outputs (TRACED0, TRACED1, TRACED2, and TRACED3) and one clock (TRACECLK) are assigned for TYPE1-M4, TYPE2-M4, TYPE4-M4, TYPE6-M4 products. Table 2-2 shows a list of pin functions in each debug mode. Table 2-2 TYPE1-M4, TYPE2-M4, TYPE4-M4, TYPE6-M4 Products: Trace Pin Functions in Debug Mode Trace TRACED0 Synchronous Trace Data Output signal...
Page 920: Functions Initially Assigned To Pins
CHAPTER 16: Debug Interface Functions Initially Assigned to Pins SWJ-DP/SW-DP/ETM/HTM/Trace pins are also as GPIO. SWJ-DP/SW-DP/Trace pins are initially dedicated to debug function, whereas ETM/HTM pins are not initially dedicated to that. When using this series, please configure these ETM pins to provide the debug function. Note: −...
Page 921: Internal Pull-Ups Of Jtag Pins
CHAPTER 16: Debug Interface Internal Pull-Ups of JTAG Pins As specified by the IEEE Standard, this family provides the JTAG pins that have internal pull-ups. The user can control pull-ups by setting the appropriate registers in the GPIO. Table 2-5 Enabled or Disabled State of Internal Pull-ups of JTAG Pins Pin Name Pull-up with JTAG Pins Enabled *1 TCK/SWCLK...
Page 922 CHAPTER 16: Debug Interface FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 923: Chapter 17: Flash Memory
CHAPTER 17: Flash Memory For the flash memory, refer to the Flash Programming Manual of the product to be used. FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 924 CHAPTER 17: Flash Memory FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 925: Chapter 18: Unique Id Register
CHAPTER 18: Unique ID Register Functions and operations of Unique ID Register are explained as follows. 1. Overview 2. Registers FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 926: Overview
CHAPTER 18: Unique ID Register Overview Overview of this function is explained as follows. 41 bits of preset device unique values have been set to the Unique ID Register. These values are different from each other in all of the devices which allow using these bits for various purposes such as security enhancement and product serial number.
Page 927: Registers
CHAPTER 18: Unique ID Register Registers Configuration and functions of registers are explained as follows. Registers List Abbreviated Name Register Name Reference UIDR0 Unique ID Register 0 UIDR1 Unique ID Register 1 FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 928: Unique Id Register 0 (Uidr0: Unique Id Register 0)
CHAPTER 18: Unique ID Register Unique ID Register 0 (UIDR0: Unique ID Register 0) Unique ID Register 0 is explained as follows. Field UID[27:20] Attribute Field UID[19:12] Attribute Field UID[11:4] Attribute Field UID[3:0] Reserved Attribute [bit31:4] UID[27:0] : Unique ID 27 through 0 Bit 27 through 0 of the unique ID.
Page 929: Unique Id Register 1 (Uidr1: Unique Id Register 1)
CHAPTER 18: Unique ID Register Unique ID Register 1 (UIDR1: Unique ID Register 1) Unique ID Register 1 is explained as follows. Field Reserved Attribute Field Reserved Attribute Field Reserved UID[40:36] Attribute Field UID[35:28] Attribute [bit31:13] Reserved : Reserved bits Reserved bits.
Page 930 CHAPTER 18: Unique ID Register FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 931: Chapter 19: Programmable Crc
CHAPTER 19: Programmable CRC This chapter explains the programmable CRC (Cyclic Redundancy Check). 1. Overview of the Programmable CRC 2. Configuration and Operation of the Programmable CRC 3. Methods for Controlling the Programmable CRC 4. Registers of the Programmable CRC 5.
Page 932: Overview Of The Programmable Crc
CHAPTER 19: Programmable CRC Overview of the Programmable CRC This section explains the overview of the programmable CRC. Overview The programmable CRC is the functional block which can compute CRC values of the input data. − CRC generator polynomial can be selected arbitrarily. (CRC values length up to 32-bit) −...
Page 933: Configuration And Operation Of The Programmable Crc
CHAPTER 19: Programmable CRC Configuration and Operation of the Programmable CRC Configuration of the Programmable CRC Figure 2-1shows the block diagram of the programmable CRC. Figure 2-1 Block Diagram of the Programmable CRC Write input data from CPU PRGCRC_WR[31:0] reg. Input data PRGCRC_CFG.
Page 934: Operation Of The Programmable Crc
CHAPTER 19: Programmable CRC Operation of the Programmable CRC This section explains the functions of the programmable CRC and computing operation based on the block diagram in Figure 2-1. CRC computing is performed in the LFSR (Linear Feedback Shift Register) block in the block diagram. Specify the generator polynomial value of CRC computing to the PRGCRC_POLY register before computing starts.
Page 935 CHAPTER 19: Programmable CRC performed at first, the value specified with the PRGCRC_FXOR register is operated with bitwise XOR, and then the value is stored in the PRGCRC_RD register. Table2-4 shows operation example of output format conversion of 16-bit data. Table2-4 Operation Example of Output Data Format Conversion Output Data from LFSR PRGCRC_RD...
Page 936: Methods For Controlling The Programmable Crc
CHAPTER 19: Programmable CRC Methods for Controlling the Programmable CRC This section explains an example of methods for controlling the programmable CRC. Control Flow for the Programmable CRC (during Input Data Transfer from CPU) Figure 3-1 shows a flowchart of the control method when transferring input data from CPU to acquire the CRC computing result.
Page 937 CHAPTER 19: Programmable CRC #7 and #8 Wait for the completion of computing. Check that LOCK of the PRGCRC_CFG register is "0" and go to the next step. #9 If you need to input other data, go to step #10. If not, go to step #11. #10 If input/output format change is required for the next input/output data, go to step #5.
Page 938: Control Flow For The Programmable Crc (During Input Data Dma Transfer With Dstc)
CHAPTER 19: Programmable CRC Control Flow for the Programmable CRC (during Input Data DMA Transfer with DSTC) Figure 3-2 shows a flowchart of the control method when transferring input data with HW startup DMA transfer of DSTC to acquire the CRC computing result. The numbers shown in the figure correspond the numbers of the following descriptions.
Page 939 CHAPTER 19: Programmable CRC Each time CRC computing is completed, a transfer request is issued and transfer operations are repeatedly performed until transfer of all input data completes. When transfer of the last input data completes, DSTC resets the DRQMSK[n] register and masks the following transfer requests from the programmable CRC.
Page 940: Registers Of The Programmable Crc
CHAPTER 19: Programmable CRC Registers of the Programmable CRC This section explains the register functions of the programmable CRC. Control Register List Table 4-1 shows the list of the programmable CRC control registers. Table 4-1 List of Programmable CRC Control Registers Abbreviated Offset Address Register Name...
Page 941: Crc Computing Generator Polynomial Register
CHAPTER 19: Programmable CRC CRC Computing Generator Polynomial Register CRC computing generator polynomial register (PRGCRC_POLY) specifies the generator polynomial for CRC computing. Register configuration Address: +0x00 Field PRGCRC_POLY[31:0] Attribute Initial value 0x 04C1 1DB7 Register functions [bit31:0] PRGCRC_POLY (Generator Polynomial) Access Application Sets generator polynomial for CRC computing.
Page 942 CHAPTER 19: Programmable CRC  Specify the values from the term of largest degree -1 by left justified, padding with "0" for the right unused section. 0101 1100 0110 0000 0000 0000 0000 0000 (binary) / 0x 5C60 0000 (hexadecimal) The value of the PRGCRC_POLY register is not influenced by the format conversion specifications (PRGCRC_CFG.
Page 943: Crc Computing Initial Value Register
CHAPTER 19: Programmable CRC CRC Computing Initial Value Register CRC computing initial value register (PRGCRC_SEED) specifies the initial values for CRC computing. Register configuration Address: +0x04 Field PRGCRC_SEED[31:0] Attribute Initial value 0x FFFF FFFF Register functions [bit31:0] PRGCRC_SEED (CRC Seed value) Access Application Set the initial values for new CRC computing.
Page 944: Crc Computing Result Xor Value Register
CHAPTER 19: Programmable CRC CRC Computing Result XOR Value Register The CRC computing result XOR value register (PRGCRC_FXOR) specifies the value of XOR (exclusive OR) for final results of CRC computing. Register configuration Address: +0x08 Field PRGCRC_FXOR[31:0] Attribute Initial value 0x FFFF FFFF Register functions [bit31:0] PRGCRC_FXOR (CRC Final XOR value)
Page 945: Crc Computing Configuration Register
CHAPTER 19: Programmable CRC CRC Computing Configuration Register The CRC computing configuration register (PRGCRC_CFG) sets the operation functions of programmable CRC and reads the state. Register configuration Address: +0x0C Field Reserved Reserved Reserved LOCK Reserved CDEN CIEN CIRQ Attribute Initial value Field SZ[1:0] TEST [5:0]...
Page 946 CHAPTER 19: Programmable CRC [bit9:8] FO[1:0](CRC Output data Format) Access Application MSB-first / Big endian is selected for output format conversion. Write 00 MSB-first / Little endian is selected for output format conversion. Write 01 LSB-first / Big endian is selected for output format conversion. Write 10 LSB-first / Little endian is selected for output format conversion.
Page 947 CHAPTER 19: Programmable CRC [bit23:22] SZ[1:0] (Input data size) Access Application 8-bit input data size is selected. Write 00 16-bit input data size is selected. Write 01 24-bit input data size is selected. Write 10 32-bit input data size is selected. Write 11 Read Reads the register setting value.
Page 948 CHAPTER 19: Programmable CRC Access Application Prohibits the transfer request of input data for DMA. Write 0 In case that a transfer has been already requested, the transfer request will be canceled. Write 1 Allows the transfer request of input data for DMA. Read Reads the register setting value.
Page 949: Crc Computing Input Data Register
CHAPTER 19: Programmable CRC CRC Computing Input Data Register The CRC computing input data register (PRGCRC_WR) specifies the input data of CRC computing. Register configuration Address: +0x10 Field PRGCRC_WR[31:0] Attribute Initial value 0x 0000 0000 Register functions [bit31:0] PRGCRC_WR (CRC input write data) Access Application Sets the input data of CRC computing and starts CRC computing.
Page 950: Crc Computing Output Data Register
CHAPTER 19: Programmable CRC CRC Computing Output Data Register The CRC computing output data register (PRGCRC_RD) reads the output data of CRC computing. Register configuration Address: +0x14 Field PRGCRC_RD[31:0] Attribute Initial value 0x 0000 0000 Register functions [bit31:0] PRGCRC_RD (CRC output read data) Access Application Can write values from CPU for test purposes.
Page 951: Example Of The Programmable Crc Computing
CHAPTER 19: Programmable CRC Example of the Programmable CRC Computing This section explains an example to perform CRC computing using CRC computing function of this function block. Computing Example 1 This example1 shows computing which generates CRC code when data is transferred to the following 48-bit serial bit sequence.
Page 952 CHAPTER 19: Programmable CRC 1. Set the value of generator polynomial for the PRGCRC_POLY register. Set 0x1021 0000 according with generator polynomial. (value common to format A, B, C and D) 2. Set the CRC initial value for the PRGCRC_SEED register. Since the CRC initial value is 0xFFFF, set 0xFFFF 0000.
Page 953: Example Of Computing 2
CHAPTER 19: Programmable CRC Example of Computing 2 This example2 shows computing which checks the CRC code when data is received to the following 64-bit serial bit sequence. This was transmitted in the computing example 1. This example is explained based on the following conditions.
Page 954 CHAPTER 19: Programmable CRC 4. Set the computing input/output format for the PRGCRC_CFG register. The size of the input data is 32-bit. Select and set (SZ="11") and the computing input/output data format (FI, FO) respectively according to the memory storage format of the input/output data. 5.
Page 955: Appendixes
Appendixes This chapter shows the register map, the list of notes and the major changes. A. Register Map B. List of Notes C. Major Changes FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 956: Register Map
A. Register Map This chapter shows the register map. 1. Register Map 1.1 FLASH_IF 1.2 Unique ID 1.3 ECC Capture Address 1.4 Clock/Reset 1.5 HW WDT 1.6 SW WDT 1.7 Dual_Timer 1.8 MFT 1.9 PPG 1.10 Base Timer 1.11 IO Selector for Base Timer 1.12 QPRC 1.13 QPRC NF 1.14 A/DC...
Page 957 A. Register Map 1.37 DMAC 1.38 DSTC 1.39 CAN 1.40 Ethernet-MAC 1.41 Ethernet-Control 1.42 I2S 1.43 SD-Card 1.44 CAN FD 1.45 Programmable-CRC 1.46 WorkFlash_IF 1.47 High-Speed Quad SPI Controller 1.48 HyperBus Interface 1.49 GDC Sub System Controller 1.50 GDC Sub System SDRAM Controller FM4 Peripheral Manual, Doc.
Page 958: Register Map
A. Register Map Register Map Register map is shown on the table every module/function. [How to read the each table] Module/function name and its base address Clock/Reset Base_Address : 0x4001_0000 Base_Address Register + Address SCM_CTL[B,H,W] 0x000 00000-0- SCM_STR[B,H,W] 0x004 00000-0- STB_CTL[B,H,W] 0x008 00000000 00000000 -------- ---0--00...
Page 959: Flash_If
A. Register Map FLASH_IF TYPE1-M4, TYPE2-M4 Products 1.1.1 FLASH_IF Base_Address : 0x4000_0000 Base_Address Register + Address 0x000 FASZR[B,H,W] 0x004 FRWTR[B,H,W] 0x008 FSTR[B,H,W] 0x00C 0x010 FSYNDN[B,H,W] 0x014 FBFCR[B,H,W] 0x018 - 0x01C 0x020 FICR[B,H,W] 0x024 FISR[B,H,W] 0x028 FICLR[B,H,W] 0x02C - 0x0FC 0x100 CRTRMM[B,H,W] 0x104 - 0x1FC Note:...
Page 960: Type3-M4 Product
A. Register Map TYPE3-M4 Product 1.1.2 FLASH_IF Base_Address : 0x4000_0000 Register Base_Address + Address 0x000 FASZR[B,H,W] 0x004 FRWTR[B,H,W] 0x008 FSTR[B,H,W] 0x00C 0x010 FSYNDN[B,H,W] 0x014 FBFCR[B,H,W] 0x018 - 0x01C 0x020 FICR[B,H,W] 0x024 FISR[B,H,W] 0x028 FICLR[B,H,W] 0x02C 0x030 DFCTRLR[W] 0x034 - 0x0FC 0x100 CRTRMM[B,H,W] 0x104 - 0x10C...
Page 961: Type4-M4, Type5-M4, Type6-M4 Products
A. Register Map TYPE4-M4, TYPE5-M4, TYPE6-M4 Products 1.1.3 FLASH_IF Base_Address : 0x4000_0000 Register Base_Address + Address 0x000 FASZR[B,H,W] 0x004 FRWTR[B,H,W] 0x008 FSTR[B,H,W] 0x00C 0x010 FSYNDN[B,H,W] 0x014 FBFCR[B,H,W] 0x018 - 0x01C 0x020 FICR[B,H,W] 0x024 FISR[B,H,W] 0x028 FICLR[B,H,W] 0x02C - 0x0FC 0x100 CRTRMM[B,H,W] 0x104 - 0x10C 0x110...
Page 962: Unique Id
A. Register Map Unique ID Unique ID Base_Address : 0x4000_0200 Register Base_Address + Address UIDR0[W] 0x000 XXXXXXXX XXXXXXXX XXXXXXXX XXXX---- UIDR1[W] 0x004 -------- -------- ---XXXXX XXXXXXXX 0x008 - 0xDFC ECC Capture Address ECC Capture Address Base_Address : 0x4000_0300 Register Base_Address + Address FERRAD[W] 0x000...
Page 963: Clock/Reset
A. Register Map Clock/Reset TYPE1-M4, TYPE2-M4 Products 1.4.1 Clock/Reset Base_Address : 0x4001_0000 Register Base_Address + Address SCM_CTL[W] 0x000 00000-0- SCM_STR[W] 0x004 00000-0- STB_CTL[W] 0x008 00000000 00000000 -------- ---0-000 RST_STR[W] 0x00C -------0 0000--01 BSC_PSR[W] 0x010 -----000 APBC0_PSR[W] 0x014 ------00 APBC1_PSR[W] 0x018 1--0--00 APBC2_PSR[W] 0x01C...
Page 964 A. Register Map Base_Address Register + Address FCSWD_CTL[W] 0x050 00000000 00000000 DBWDT_CTL[W] 0x054 0-0----- 0x058 0x05C - 0x05F INT_ENR[W] 0x060 --0--000 INT_STR[W] 0x064 --0–000 INT_CLR[W] 0x068 --0--000 0x06C – 0xFFC FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 965: Type3-M4, Type4-M4, Type5-M4, Type6-M4 Products
A. Register Map TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products 1.4.2 Clock/Reset Base_Address : 0x4001_0000 Register Base_Address + Address SCM_CTL[W] 0x000 00000-0- SCM_STR[W] 0x004 00000-0- STB_CTL[W] 0x008 00000000 00000000 -------- ---0-000 RST_STR[W] 0x00C -------0 0000--01 BSC_PSR[W] 0x010 -----000 APBC0_PSR[W] 0x014 ------00 APBC1_PSR[W] 0x018 1--0--00 APBC2_PSR[W]...
Page 966 A. Register Map Base_Address Register + Address FCSWD_CTL[W] 0x050 00000000 00000000 DBWDT_CTL[W] 0x054 0-0----- 0x058 0x05C - 0x05F INT_ENR[W] 0x060 --0--000 INT_STR[W] 0x064 --0–000 INT_CLR[W] 0x068 --0--000 0x06C – 0x070 PLLCG_CTL[W] 0x074 -------- 11111111 00000000 00----00 0x078 – 0xFFC FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 967: Hw Wdt
A. Register Map HW WDT HW WDT Base_Address : 0x4001_1000 Register Base_Address + Address WDG_LDR[W] 0x000 00000000 00000000 11111111 11111111 WDG_VLR[W] 0x004 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WDG_CTL[W] 0x008 ------11 WDG_ICL[W] 0x00C XXXXXXXX WDG_RIS[W] 0x010 -------0 0x014 0x018 – 0xBFC WDG_LCK[W] 0xC00 00000000 00000000 00000000 00000001 0xC04 –...
Page 968: Dual_Timer
A. Register Map Dual_Timer Dual_Timer Base_Address : 0x4001_5000 Register Base_Address + Address Timer1Load[W] 0x000 00000000 00000000 00000000 00000000 Timer1Value[W] 0x004 11111111 11111111 11111111 11111111 Timer1Control[W] 0x008 -------- -------- -------- 00100000 Timer1IntClr[W] 0x00C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Timer1RIS[W] 0x010 -------- -------- -------- -------0 Timer1MIS[W] 0x014 -------- -------- -------- -------0...
Page 969: Mft
A. Register Map TYPE1-M4, TYPE2-M4 Products 1.8.1 MFT unit0 Base_Address : 0x4002_0000 MFT unit1 Base_Address : 0x4002_1000 MFT unit2 Base_Address : 0x4002_2000 Register Base_Address + Address OCCP0[H,W] 0x100 00000000 00000000 OCCP1[H,W] 0x104 00000000 00000000 OCCP2[H,W] 0x108 00000000 00000000 OCCP3[H,W] 0x10C 00000000 00000000 OCCP4[H,W] 0x110...
Page 970 A. Register Map Base_Address Register + Address TCCP1[H,W] 0x14C 11111111 11111111 TCDT1[H,W] 0x150 00000000 00000000 TCSC1[H,W] TCSA1[B,H,W] 0x154 00000000 00000000 00000000 01000000 TCCP2[H,W] 0x158 11111111 11111111 TCDT2[H,W] 0x15C 00000000 00000000 TCSC2[H,W] TCSA2[B,H,W] 0x160 00000000 00000000 00000000 01000000 TCAL[W] 00000000 00000000 11111111 11111111 *1 0x164 - *2 *1 MFT unit0...
Page 971 A. Register Map Base_Address Register + Address WFTF54[H,W] 0x19C 00000000 00000000 WFTB54[H,W] WFTA54[H,W] 0x1A0 00000000 00000000 00000000 00000000 WFSA10[B,H,W] 0x1A4 --000000 000000 WFSA32[B,H,W] 0x1A8 --000000 000000 WFSA54[B,H,W] 0x1AC --000000 000000 WFIR[H,W] 0x1B0 00000000 00000000 NZCL[H,W] 0x1B4 00000000 00000000 ACMP0[H,W] 0x1B8 00000000 00000000 ACMP1[H,W] 0x1BC...
Page 972: Type3-M4, Type4-M4, Type5-M4, Type6-M4 Products
A. Register Map TYPE3-M4, TYPE4-M4, TYPE5-M4, TYPE6-M4 Products 1.8.2 MFT unit0 Base_Address : 0x4002_0000 MFT unit1 Base_Address : 0x4002_1000 MFT unit2 Base_Address : 0x4002_2000 Base_Address Register + Address OCCP0[H,W] 0x100 00000000 00000000 OCCP1[H,W] 0x104 00000000 00000000 OCCP2[H,W] 0x108 00000000 00000000 OCCP3[H,W] 0x10C 00000000 00000000...
Page 973 A. Register Map Base_Address Register + Address TCDT1[H,W] 0x150 00000000 00000000 TCSC1[H,W] TCSA1[B,H,W] 0x154 00000000 00000000 00000000 01000000 TCCP2[H,W] 0x158 11111111 11111111 TCDT2[H,W] 0x15C 00000000 00000000 TCSC2[H,W] TCSA2[B,H,W] 0x160 00000000 00000000 00000000 01000000 TCAL[W] 00000000 00000000 11111111 11111111 *1 0x164 - *2 *1 MFT unit0 *2 MFT unit1,unit2...
Page 974 A. Register Map Base_Address Register + Address WFTB54[H,W] WFTA54[H,W] 0x1A0 00000000 00000000 00000000 00000000 WFSA10[B,H,W] 0x1A4 --000000 000000 WFSA32[B,H,W] 0x1A8 --000000 000000 WFSA54[B,H,W] 0x1AC --000000 000000 WFIR[H,W] 0x1B0 00000000 00000000 NZCL[H,W] 0x1B4 00000000 00000000 ACMP0[H,W] 0x1B8 00000000 00000000 ACMP1[H,W] 0x1BC 00000000 00000000 ACMP2[H,W] 0x1C0...
Page 975: Ppg
A. Register Map Base_Address : 0x4002_4000 Base_Address Register + Address TTCR0 [B,H,W] 0x000 11110000 0x004 COMP0 [B,H,W] 0x008 00000000 COMP2 [B,H,W] 0x00C 00000000 COMP4 [B,H,W] 0x010 00000000 COMP6 [B,H,W] 0x014 00000000 0x018 - 0x01C TTCR1 [B,H,W] 0x020 11110000 0x024 COMP1 [B,H,W] 0x028 00000000 COMP3 [B,H,W]...
Page 976 A. Register Map Register Base_Address + Address PPGC0 [B,H,W] PPGC1 [B,H,W] 0x200 00000000 00000000 PPGC2 [B,H,W] PPGC3 [B,H,W] 0x204 00000000 00000000 PRLH0 [B,H,W] PRLL0 [B,H,W] 0x208 XXXXXXXX XXXXXXXX PRLH1 [B,H,W] PRLL1 [B,H,W] 0x20C XXXXXXXX XXXXXXXX PRLH2 [B,H,W] PRLL2 [B,H,W] 0x210 XXXXXXXX XXXXXXXX PRLH3 [B,H,W]...
Page 977 A. Register Map Register Base_Address + Address PPGC14 [B,H,W] PPGC15 [B,H,W] 0x2C4 00000000 00000000 PRLH12 [B,H,W] PRLL12 [B,H,W] 0x2C8 XXXXXXXX XXXXXXXX PRLH13 [B,H,W] PRLL13 [B,H,W] 0x2CC XXXXXXXX XXXXXXXX PRLH14 [B,H,W] PRLL14 [B,H,W] 0x2D0 XXXXXXXX XXXXXXXX PRLH15 [B,H,W] PRLL15 [B,H,W] 0x2D4 XXXXXXXX XXXXXXXX GATEC12 [B,H,W]...
Page 978: Base Timer
A. Register Map Base Timer 1.10 Base Timer ch.0 Base Address : 0x4002_5000 Base Timer ch.1 Base Address : 0x4002_5040 Base Timer ch.2 Base Address : 0x4002_5080 Base Timer ch.3 Base Address : 0x4002_50C0 Base Timer ch.4 Base Address : 0x4002_5200 Base Timer ch.5 Base Address : 0x4002_5240 Base Timer ch.6...
Page 979: Io Selector For Base Timer
A. Register Map IO Selector for Base Timer 1.11 IO Selector for ch.0-ch.3 (Base Timer) Base Address : 0x4002_5100 Register Base_Address + Address BTSEL0123 [B,H,W] 0x000 00000000 0x004 - 0x0FC IO Selector for ch.4-ch.7(Base Timer) Base Address : 0x4002_5300 Register Base_Address + Address BTSEL4567 [B,H,W]...
Page 980: Qprc
A. Register Map QPRC 1.12 TYPE1-M4, TYPE2-M4, TYPE6-M4 Products 1.12.1 QPRC ch.0 Base Address : 0x4002_6000 QPRC ch.1 Base Address : 0x4002_6040 QPRC ch.2 Base Address : 0x4002_6080 QPRC ch.3 Base Address : 0x4002_60C0 Base_Address Register + Address QPCR [H,W] 0x0000 00000000 00000000 QRCR [H,W]...
Page 981: Type3-M4, Type4-M4, Type5-M4 Products
A. Register Map TYPE3-M4, TYPE4-M4, TYPE5-M4 Products 1.12.2 QPRC ch.0 Base Address : 0x4002_6000 QPRC ch.1 Base Address : 0x4002_6040 QPRC ch.2 Base Address : 0x4002_6080 QPRC ch.3 Base Address : 0x4002_60C0 Base_Address Register + Address QPCR [H,W] 0x0000 00000000 00000000 QRCR [H,W] 0x0004 00000000 00000000...
Page 982: Qprc Nf
A. Register Map QPRC NF 1.13 QPRC ch.0 NF Base Address : 0x4002_6100 QPRC ch.1 NF Base Address : 0x4002_6110 QPRC ch.2 NF Base Address : 0x4002_6120 QPRC ch.3 NF Base Address : 0x4002_6130 Base_Address Register + Address NFCTLA[B,H,W] 0x0000 --00-000 NFCTLB[B,H,W] 0x0004...
Page 983: A/Dc
A. Register Map A/DC 1.14 12bit A/DC unit0 Base_Address : 0x4002_7000 12bit A/DC unit1 Base_Address : 0x4002_7100 12bit A/DC unit2 Base_Address : 0x4002_7200 Register Base_Address + Address ADCR[B,H,W] ADSR[B,H,W] 0x000 000-0000 00---000 0x004 SCCR[B,H,W] SFNS[B,H,W] 0x008 1000-000 ----0000 SCFD[B,H,W] 0x00C XXXXXXXX XXXX---- ---1--XX ---XXXXX SCIS3[B,H,W] SCIS2[B,H,W]...
Page 984: Cr Trim
A. Register Map CR Trim 1.15 CR Trim Base_Address : 0x4002_E000 Register Base_Address + Address MCR_PSR[B,H,W] 0x000 -----001 MCR_FTRM[B,H,W] 0x004 ------01 11101111 MCR_TTRM[B,H,W] 0x008 ---10000 MCR_RLR[W] 0x00C 00000000 00000000 00000000 00000001 0x010 - 0x0FC FM4 Peripheral Manual, Doc. No. 002-04856 Rev. *E...
Page 985: Exti
A. Register Map EXTI 1.16 TYPE1-M4, TYPE2-M4, TYPE3-M4, TYPE4-M4 Products 1.16.1 EXTI Base_Address : 0x4003_0000 Base_Address Register + Address ENIR[B,H,W] 0x000 00000000 00000000 00000000 00000000 EIRR[B,H,W] 0x004 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EICL[B,H,W] 0x008 11111111 11111111 11111111 11111111 ELVR[B,H,W] 0x00C 00000000 00000000 00000000 00000000 ELVR1[B,H,W] 0x010 00000000 00000000 00000000 00000000...
Page 986: Int-Req. Read
A. Register Map INT-Req. READ 1.17 TYPE1-M4, TYPE2-M4, TYPE6-M4 Products 1.17.1 INT-Req. READ Base_Address : 0x4003_1000 Base_Address Register + Address DRQSEL[B,H,W] 0x000 00000000 00000000 00000000 00000000 0x004 – 0x00C ODDPKS[B] 0x010 ---00000 0x014 0x018 0x01C – 0x10C IRQ003SEL[B,H,W] 0x110 -------- 00000000 -------- 00000000 IRQ004SEL[B,H,W] 0x114 -------- 00000000 -------- 00000000...
Page 987 A. Register Map Register Base_Address + Address IRQ006MON[B,H,W] 0x21C -------- -------- -------- 00000000 IRQ007MON[B,H,W] 0x220 -------- -------- -------- 00000000 IRQ008MON[B,H,W] 0x224 -------- -------- -------- 00000000 IRQ009MON[B,H,W] 0x228 -------- -------- -------- 00000000 IRQ010MON[B,H,W] 0x22C -------- -------- -------- 00000000 IRQ011MON[B,H,W] 0x230 -------- -------- -------- -------0 IRQ012MON[B,H,W] 0x234 -------- -------- -------- -------0...
Page 988 A. Register Map Register Base_Address + Address IRQ030MON[B,H,W] 0x27C -------- -------- -------- ----0000 IRQ031MON[B,H,W] 0x280 -------- -------- -------- --000000 IRQ032MON[B,H,W] 0x284 -------- -------- -------- -----000 IRQ033MON[B,H,W] 0x288 -------- -------- -------- -----000 IRQ034MON[B,H,W] 0x28C -------- -------- -------- ---00000 IRQ035MON[B,H,W] 0x290 -------- -------- -------- --000000 IRQ036MON[B,H,W] 0x294 -------- -------- -------- -----000...
Page 989 A. Register Map Register Base_Address + Address IRQ054MON[B,H,W] 0x2DC -------- -------- -------- -------0 IRQ055MON[B,H,W] 0x2E0 -------- -------- -------- -------0 IRQ056MON[B,H,W] 0x2E4 -------- -------- -------- -------0 IRQ057MON[B,H,W] 0x2E8 -------- -------- -------- -------0 IRQ058MON[B,H,W] 0x2EC -------- -------- -------- -------0 IRQ059MON[B,H,W] 0x2F0 -------- -------- -------- ----0000 IRQ060MON[B,H,W] 0x2F4 -------- -------- -------- -------0...
Page 990 A. Register Map Register Base_Address + Address IRQ078MON[B,H,W] 0x33C -------- -------- -------- ---00000 IRQ079MON[B,H,W] 0x340 -------- -------- -------- --000000 IRQ080MON[B,H,W] 0x344 -------- -------- -------- -------0 IRQ081MON[B,H,W] 0x348 -------- -------- -------- -------0 IRQ082MON[B,H,W] 0x34C -------- -------- -------- -----000 IRQ083MON[B,H,W] 0x350 -------- -------- -------- -------0 IRQ084MON[B,H,W] 0x354 -------- -------- -------- -------0...
Page 991 A. Register Map Register Base_Address + Address IRQ102MON[B,H,W] 0x39C -------- -------- -------- ------00 IRQ103MON[B,H,W] 0x3A0 -------- -------- -------- -------0 IRQ104MON[B,H,W] 0x3A4 -------- -------- -------- ------00 IRQ105MON[B,H,W] 0x3A8 -------- -------- -------- -------0 IRQ106MON[B,H,W] 0x3AC -------- -------- -------- ------00 IRQ107MON[B,H,W] 0x3B0 -------- -------- -------- -------0 IRQ108MON[B,H,W] 0x3B4 -------- -------- -------- ------00...
Page 992: Type3-M4, Type5-M4 Product
A. Register Map TYPE3-M4, TYPE5-M4 Products 1.17.2 INT-Req. READ Base_Address : 0x4003_1000 Register Base_Address + Address DRQSEL[B,H,W] 0x000 00000000 00000000 00000000 00000000 0x004 – 0x00C ODDPKS[B] 0x010 ---00000 ODDPKS1[B] 0x014 --00000 0x018 0x01C – 0x10C IRQ003SEL[B,H,W] 0x110 -------- 00000000 -------- 00000000 IRQ004SEL[B,H,W] 0x114 -------- 00000000 -------- 00000000...
Page 993 A. Register Map Base_Address Register + Address IRQ006MON[B,H,W] 0x21C -------- -------- -------- 00000000 IRQ007MON[B,H,W] 0x220 -------- -------- -------- 00000000 IRQ008MON[B,H,W] 0x224 -------- -------- -------- 00000000 IRQ009MON[B,H,W] 0x228 -------- -------- -------- 00000000 IRQ010MON[B,H,W] 0x22C -------- -------- -------- 00000000 IRQ011MON[B,H,W] 0x230 -------- -------- -------- -------0 IRQ012MON[B,H,W] 0x234 -------- -------- -------- -------0...
Page 994 A. Register Map Base_Address Register + Address IRQ027MON[B,H,W] 0x270 -------- -------- -------- --000000 IRQ028MON[B,H,W] 0x274 -------- -------- -------- -----000 IRQ029MON[B,H,W] 0x278 -------- -------- -------- -----000 IRQ030MON[B,H,W] 0x27C -------- -------- -------- ----0000 IRQ031MON[B,H,W] 0x280 -------- -------- -------- --000000 IRQ032MON[B,H,W] 0x284 -------- -------- -------- -----000 IRQ033MON[B,H,W] 0x288 -------- -------- -------- -----000...
Page 995 A. Register Map Base_Address Register + Address IRQ048MON[B,H,W] 0x2C4 -------- -------- -------- -------0 IRQ049MON[B,H,W] 0x2C8 -------- -------- -------- -------0 IRQ050MON[B,H,W] 0x2CC -------- -------- -------- -------0 IRQ051MON[B,H,W] 0x2D0 -------- -------- -------- -------0 IRQ052MON[B,H,W] 0x2D4 -------- -------- -------- -------0 IRQ053MON[B,H,W] 0x2D8 -------- -------- -------- -------0 IRQ054MON[B,H,W] 0x2DC -------- -------- -------- -------0...
Page 996 A. Register Map Base_Address Register + Address IRQ069MON[B,H,W] 0x318 -------- -------- -------- ------00 IRQ070MON[B,H,W] 0x31C -------- -------- -------- -------0 IRQ071MON[B,H,W] 0x320 -------- -------- -------- ------00 IRQ072MON[B,H,W] 0x324 -------- -------- -------- -------0 IRQ073MON[B,H,W] 0x328 -------- -------- -------- ------00 IRQ074MON[B,H,W] 0x32C -------- -------- -------- -------0 IRQ075MON[B,H,W] 0x330 -------- -------- -------- ------00...
Page 997 A. Register Map Base_Address Register + Address IRQ090MON[B,H,W] 0x36C -------- -------- -------- -------0 IRQ091MON[B,H,W] 0x370 -------- -------- -------- ------00 IRQ092MON[B,H,W] 0x374 -------- -------- -------- ----0000 IRQ093MON[B,H,W] 0x378 -------- -------- -------- ----0000 IRQ094MON[B,H,W] 0x37C -------- -------- -------- ----0000 IRQ095MON[B,H,W] 0x380 -------- -------- -------- ----0000 IRQ096MON[B,H,W] 0x384 -------- -------- -------- --000000...
Page 998 A. Register Map Base_Address Register + Address IRQ111MON[B,H,W] 0x3C0 -------- -------- -------- ---00000 IRQ112MON[B,H,W] 0x3C4 -------- -------- -------- --000000 IRQ113MON[B,H,W] 0x3C8 -------- -------- -------- --000000 IRQ114MON[B,H,W] 0x3CC -------- -------- -------- -0000000 IRQ115MON[B,H,W] 0x3D0 -------- -------- -------- -----000 IRQ116MON[B,H,W] 0x3D4 -------- -------- -------- -------- IRQ117MON[B,H,W] 0x3D8 -------- -------- -------- ------00...
Page 999: Type4-M4 Product
A. Register Map TYPE4-M4 Product 1.17.3 INT-Req. READ Base_Address : 0x4003_1000 Register Base_Address + Address DRQSEL[B,H,W] 0x000 00000000 00000000 00000000 00000000 0x004 – 0x00C ODDPKS[B] 0x010 ---00000 ODDPKS1[B] 0x014 --00000 0x018 0x01C – 0x10C IRQ003SEL[B,H,W] 0x110 00000000 00000000 -------- 00000000 IRQ004SEL[B,H,W] 0x114 00000000 00000000 -------- 00000000...
Page 1000 A. Register Map Base_Address Register + Address IRQ006MON[B,H,W] 0x21C -------- -------- -------- 00000000 IRQ007MON[B,H,W] 0x220 -------- -------- -------- 00000000 IRQ008MON[B,H,W] 0x224 -------- -------- -------- 00000000 IRQ009MON[B,H,W] 0x228 -------- -------- -------- 00000000 IRQ010MON[B,H,W] 0x22C -------- -------- -------- 00000000 IRQ011MON[B,H,W] 0x230 -------- -------- -------- -------0 IRQ012MON[B,H,W] 0x234 -------- -------- -------- -------0...