Specify Base Addresses And Interrupt Request Priorities - Altera Nios II Hardware Development Manual

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7. Connect the clk_reset port of the clk_0 clock source to the reset port of the PIO.
8. Connect the data_master port of the Nios II processor to the s1 port of the PIO.
9. In the external_connection row, click Click to export in the Export column to
export the PIO ports.
f
For more information about the PIO, refer to the PIO Core chapter in the
Peripherals IP User

Specify Base Addresses and Interrupt Request Priorities

At this point, you have added all the necessary hardware components to the system.
Now you must specify how the components interact to form a system. In this section,
you assign base addresses for each slave component, and assign interrupt request
(IRQ) priorities for the JTAG UART and the interval timer.
Qsys provides the Assign Base Addresses command which makes assigning
component base addresses easy. For many systems, including this design example,
Assign Base Addresses is adequate. However, you can adjust the base addresses to
suit your needs. Below are some guidelines for assigning base addresses:
■ Nios II processor cores can address a 31-bit address span. You must assign base
address between 0x00000000 and 0x7FFFFFFF.
■ Nios II programs use symbolic constants to refer to addresses. Do not worry about
choosing address values that are easy to remember.
Address values that differentiate components with only a one-bit address
■
difference produce more efficient hardware. Do not worry about compacting all
base addresses into the smallest possible address range, because this can create
less efficient hardware.
■ Qsys does not attempt to align separate memory components in a contiguous
memory range. For example, if you want an on-chip RAM and an off-chip RAM to
be addressable as one contiguous memory range, you must explicitly assign base
addresses.
Qsys also provides an Assign Interrupt Numbers command which connects IRQ
signals to produce valid hardware results. However, assigning IRQs effectively
requires an understanding of how software responds to them. Because Qsys does not
know the software behavior, Qsys cannot make educated guesses about the best IRQ
assignment.
The Nios II HAL interprets low IRQ values as higher priority. The timer component
must have the highest IRQ priority to maintain the accuracy of the system clock tick.
To assign appropriate base addresses and IRQs, perform the following steps:
1. On the System menu, click Assign Base Addresses to make Qsys assign functional
base addresses to each component in the system. Values in the Base and End
columns might change, reflecting the addresses that Qsys reassigned.
2. In the IRQ column, connect the Nios II processor to the JTAG UART and interval
timer.
3. Click the IRQ value for the jtag_uart component to select it.
4. Type 16 and press Enter to assign a new IRQ value.
Nios II Hardware Development Tutorial
Guide.
Chapter 1: Nios II Hardware Development
Creating the Design Example
Embedded
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