Compile The Quartus Ii Project And Verify Timing - Altera Nios II Hardware Development Manual

Chapter 1: Nios II Hardware Development
Creating the Design Example
Figure 1–17
Figure 1–17. The Unused Pins Page of the Device and Pin Options Dialog Box
14. In the Reserve all unused pins list, select As input tri-stated with weak pull-up.
With this setting, all unused I/O pins on the FPGA enter a high-impedance state
after power-up.
c
Unused pins are set as input tri-stated with weak pull-up to remove contention which
might damage the board. Depending on the board, you might have to make more
assignments for the project to function correctly. You can damage the board if you fail
to account for the board design. Consult with the maker of the board for specific
contention information.
15. Click OK to close the Device and Pin Options dialog box.
16. Click OK to close the Device dialog box.
f
For more information about making assignments in the Quartus II software, refer to
the Volume 2: Design Implementation and Optimization

Compile the Quartus II Project and Verify Timing

At this point you are ready to compile the Quartus II project and verify that the
resulting design meets timing requirements.
You must compile the hardware design to create a .sof that you can download to the
board. After the compilation completes, you must analyze the timing performance of
the FPGA design to verify that the design will work in hardware.
May 2011 Altera Corporation
shows the Unused Pins page of the Device and Pin Options dialog box.
of the Quartus II Handbook.
Nios II Hardware Development Tutorial
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