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3.3 Connectors description
3.3.1 LVDS + backlight connector
Embedded into NXP i.MX6 processor there is an LVDS Display Bridge, connected to the Image Processing Unit (IPU), that makes externally available two LVDS
channels, each one consisting of 1 clock pair and four data pairs.
LVDS connector - J1
Pin
Signal
Pin
Signal
1
V
2
V
IN
IN
3
+3.3V
4
+5V
LCD
5
+3.3V
6
+5V
LCD
7
LVDS1_TX0-
8
LVDS0_TX0-
9
LVDS1_TX0+
10
LVDS0_TX0+
11
LVDS1_TX1-
12
LVDS0_TX1-
13
LVDS1_TX1+
14
LVDS0_TX1+
15
LVDS1_TX2-
16
LVDS0_TX2-
17
LVDS1_TX2+
18
LVDS0_TX2+
19
LVDS1_TX3-
20
LVDS0_TX3-
21
LVDS1_TX3+
22
LVDS0_TX3+
23
GND
24
GND
25
LVDS1_CLK-
26
LVDS0_CLK-
27
LVDS1_CLK+
28
LVDS0_CLK+
29
LVDS_BLT_EN
30
LVDS_BLT_CTRL
31
GND
32
GND
LVDS0_TX2+/LVDS0_TX2-: LVDS Channel #0 differential data pair #2.
LVDS0_TX3+/LVDS0_TX3-: LVDS Channel #0 differential data pair #3.
LVDS0_CLK+/LVDS0_CLK-: LVDS Channel #0 differential Clock.
SBC-984
SBC-984 User Manual - Rev. First Edition: 1.0 - Last Edition: 4.0 - Author: S.B. - Reviewed by N.P. Copyright © 2016 SECO S.r.l.
It is possible to configure LVDS output so that it can be used as:
One single channel (18 or 24 bit) output, max resolution supported 1366 x 768 @ 60fps
One dual channel (18 or 24 bit) output, max resolution supported 1920 x 1200 @ 60fps
Two identical single channel outputs, max resolution supported 1366 x 768 @ 60fps
LCD
Two independent single channel outputs, max resolution supported 1366 x 768 @ 60fps on each
LCD
channel
All of these possibilities come by opportunely configuring the O.S. installed on the
module.
For the connection, a connector type HR A1014WVA-S-2x16P or equivalent (2 x
16p, male, straight, P1, low profile, polarized) is provided, with the pin-out shown in
the table on the left.
Mating connector: HR A1014H-2X16P with HR A1014-T female crimp terminals.
On the same connectors, are also implemented signals for direct driving of display's backlight: voltages (V
directly coming from external PSU, +5V
LVDS_BKLT_EN, and Backlight Brightness Control signal, LVDS_BLT_CTRL).
When building a cable for connection of LVDS displays, please take care of twist as tight as possible
differential pairs' signal wires, in order to reduce EMI interferences. Shielded cables are also recommended.
Here following the signals related to LVDS management:
LVDS0_TX0+/LVDS0_TX0-: LVDS Channel #0 differential data pair #0.
LVDS0_TX1+/LVDS0_TX1-: LVDS Channel #0 differential data pair #1.
and +3.3V
) and control signals (Backlight enable signal,
LCD
LCD
,
IN
23
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