Digilent Eclypse Z7 Hardware Reference Manual page 6

There are many aspects of the Zynq APSoC architecture that are beyond the scope of
this document. For a complete and thorough description, refer to the
Reference manual.
The tables in the dropdowns below depict the external components connected to the
MIO pins of the Eclypse Z7. The Vivado board files found on the
Center can be used to properly configure the PS to work with these peripherals. It is
also possible to use the example projects found on the resource center as a starting
point for custom designs.
MIO 0-15 : Bank 500
MIO 500 3.3 V
Pin
0 (N/C)
1
2
3
4
5
6
7 (N/A)
8
Peripherals
GPIO SPI Flash ENET 0
CS
DQ0
DQ1
DQ2
DQ3
SCLK
SCLK FB
Zynq Technical
Eclypse Z7 Resource
SYZYGY UART 0