Digilent Eclypse Z7 Hardware Reference Manual page 24

Figure 7.1: UART Connections
8. Zmod Ports
The Eclypse Z7 features two Zmod ports, which use SYZYGY Standard interfaces to
communicate with installed SYZYGY pods. Both ports are compatible with version 1.1
of the SYZYGY specification from Opal Kelly.
SYZYGY SmartVIO functionality is implemented by the Eclypse's Platform MCU, as
discussed in the 1 Power Supplies section of this document. Each port's SYZYGY DNA
is connected to both the Platform MCU and the Zynq's I2C 0 peripheral (MIO12:13)
through a single I2C bus. Once the board is fully powered on, and the PMCU has
configured itself in I2C slave mode, SYZYGY DNA data can be read directly from the
pods, and the negotiated voltages and currents can be read from the PMCU over this
bus.
Warning: SYZYGY pods are NOT hot-swappable. Connecting or disconnecting a pod
from the Eclypse while the board is powered on may cause damage to the pod and/or
the board, and is to be avoided.
Each SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O
pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two
dedicated differential clocks - one for input and one for output. Each Zmod port has a
I/O bank of the Zynq dedicated to it, which is powered by a dedicated adjustable rail,
configured by the Platform MCU as the Eclypse is powered on. Template constraints for
each Zmod port can be found in the Eclypse Z7's Master XDC file, available through
Digilent's digilent-xdc repository on Github.
Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software
libraries to support each Digilent Zmod.
For more information on the SYZYGY standard, see syzygyfpga.io.