Dram Timing Settings - VIA Technologies VX800 Technical Manual

Mini-itx m/b for via c7/eden/nano processor
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3-6-1 DRAM Timing Settings

Auto Configuration
* DRAM CAS Latency (TCL)
* RAS Active Time (Tras)
* ROW Precharge Time (Trp)
*RAS to CAS Delay (Trcd)
DRAM Bank Interleaving
DDR Burst Length
DRAM Command Rate
DDR Y Table
ODT
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values
Auto Configuration
The default setting is By SPD. User can set it as Manual to enable 4 sub items below it:
*DRAM CAS Latency (TCL)
The optional settings are 2T, 3T, 4T, 5T, 6T and SPD.
*RAS Active Time (Tras)
The optional settings are from 5T to 20T.
*Row Precharge Time(Trp)
The optional settings are 2T, 3T, 4T, 5T and 6T.
*RAS to CAS Delay(Trcd)
The optional settings are 2T, 3T, 4T, 5T and 6T.
DRAM Bank Interleaving
User can activate DRAM Bank Interleaving by set the item as Enabled. The optional settings
are: Enabled; Disabled.
DDR Burst Length
User can set it as 4,8 or SPD. The optional setting is SPD.
DRAM Command Rate
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
F6:Optimized Defaults
By SPD
SPD
17T
5T
Menu Level >>
5T
Enabled
SPD
2T
Optimize
Disabled
F7:Standard Defaults
24
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