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VIA Technologies VX800 Series Programming Manual

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Download this manual See also: Technical Manual
System
Programming
Manual
VX800 / VX820
Series
Preliminary Revision 0.95
June 20, 2008
VIA TECHNOLOGIES, INC.

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Summary of Contents for VIA Technologies VX800 Series

  • Page 1 System Programming Manual VX800 / VX820 Series Preliminary Revision 0.95 June 20, 2008 VIA TECHNOLOGIES, INC.
  • Page 2 However, VIA Technologies assumes no responsibility for any errors in this document. Furthermore, VIA Technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document.

  • Page 3: Table Of Contents

    VX800 / VX820 Series System Programming Manual ABLE OF ONTENTS TABLE OF CONTENTS..................................I LIST OF TABLES ...................................VI LIST OF FIGURES ..................................VI REGISTERS OVERVIEW ................................1 ............................1 EGISTER OCUMENT NTRODUCTION ..........................2 ODULE AND EGISTER COPE EFINITIONS Module Name Abbreviations ..............................2 Register Scope Map Within Modules............................

  • Page 4: Table Of Contents

    VX800 / VX820 Series System Programming Manual DDR2 – I/O Pad Termination and Driving Control (D0–DFh) ..................66 DRAM Driving Control (E0–EBh)............................73 DRAM CKG Control (EC–EFh) ............................75 DQ / DQS CKG Output Delay Control (F0–F9h)......................76 DDR2 – DQ De-Skew Control (FA–FFh) ........................... 77 4 (D0F4): P ..................
  • Page 5 VX800 / VX820 Series System Programming Manual PCI Express Electrical PHY Registers (E0-EFh)......................185 PCI Express Electrical PHY Test Registers (F0-FFh)..................... 186 0 (D3F0) – PCI E ..............188 EVICE UNCTION XPRESS XTENDED PACE Advanced Error Reporting Capability (100-13Fh)......................188 Virtual Channel Capability (140-14Fh) ..........................
  • Page 6 VX800 / VX820 Series System Programming Manual 12 F 0 (D12F0) - SDIO H ....................264 EVICE UNCTION ONTROLLER PCI Configuration Space Header (00-3Fh) ........................264 PCI Device Specific Registers (40-FFh) ..........................266 SDIO H (00-FF ) ......................... 271 TANDARD EGISTERS DA H I/O S...
  • Page 7 VX800 / VX820 Series System Programming Manual IO Trap Registers (PMIO 54-69h) ............................ 425 Watchdog Timer Memory Base (PM-MMIO 00-07h)..................... 430 System Management Bus I/O Space Registers (SMIO 00-0Fh)..................431 SPI C ..................................437 ONTROLLER 17 F 7 (D17F7): S ..............
  • Page 8 VX800 / VX820 Series System Programming Manual IST OF ABLES TABLE 1. VX800 / VX820 SERIES FEATURE COMPARISON TABLE.................. 1 TABLE 2. DYNAMIC DEFER SNOOP STALL TABLE......................19 TABLE 3. CPU WRITE REQUEST POLICY..........................22 TABLE 4. HOST / DRAM BANDWIDTH POLICY........................23 TABLE 5.

  • Page 9: Registers Overview

    VX800 / VX820 Series System Programming Manual EGISTERS VERVIEW Register Document Introduction This document includes the registers for VIA VX800 and VX820 Series. Please refer to Table 1 for the specification differences of these products. This chip integrates functional modules of the traditional North Bridge and South Bridge chips, plus 3D/2D and Video Processors, Video Decoding Accelerator and controller for external display interface.

  • Page 10: Module And Register Scope Definitions

    VX800 / VX820 Series System Programming Manual Module and Register Scope Definitions Module Name Abbreviations NM: North Module. It contains functional modules of the traditional North Bridge chip. SM: South Module. It contains functional modules of the traditional South Bridge chip. NSMIC: North-South Module Interface Control SNMIC: South-North Module Interface Control PM: Power Management...
  • Page 11 VX800 / VX820 Series System Programming Manual Abbreviation of Register Space Function Register Space / Module Name South Module D12F0 PCI Device 12, Function 0 SDIO Host Controller SDIO-MMIO Memory Space SDIO Memory Mapped I/O Space Registers D13F0 PCI Device 13, Function 0 Security Digital Controller Memory Space Security Digital Controller Memory Mapped I/O Space...

  • Page 12: Register Table Format

    VX800 / VX820 Series System Programming Manual Register Table Format Column Definitions In the register descriptions, column “Default” indicates the power-on default value of register bit(s), while column “Attribute” indicates access type of register bit. Attribute Definitions: Read / Write Attributes: read / write attributes may be used together to specify combined attributes Read Only.

  • Page 13: Pci Arbiter Control

    VX800 / VX820 Series System Programming Manual PCI Arbiter Control I/O Port Address: 22h PCI Arbiter Disable Default Value: 00h Attribute Default Description Reserved PCI2 Arbiter Control 0: Enable PCI2 Bus Arbiter 1: Disable PCI2 Bus Arbiter PCI1 Arbiter Control 0: Enable PCI1 Bus Arbiter (arbiter will respond to REQ# assertion) 1: Disable PCI1 Bus Arbiter (arbiter will not respond to PCI-1 REQ# and PREQ# assertion) PCI Configuration Space I/O...

  • Page 14: North Module Register Descriptions

    CF8 / CFC with bus number 0, device number 0 and function number 0. Header Registers (00-3Fh) Offset Address: 01-00h (D0F0) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technologies ID Code Offset Address: 03-02h (D0F0) Device ID Default Value: 0353h Attribute Default Description 15:0 0353h Device ID Code...
  • Page 15 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D0F0) PCI Status Default Value: 0210h Attribute Default Description RW1C Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) RW1C Received Master-Abort (except special cycle) 0: No abort received...
  • Page 16 VX800 / VX820 Series System Programming Manual Offset Address: 0Eh (D0F0) Header Type Default Value: 00 or 80h Attribute Default Description 00 or 80h Header Type Could be 80 when Rx4F[0] = 1 Offset Address: 0Fh (D0F0) Built In Self Test (BIST) Default Value: 00h Attribute Default...

  • Page 17: Multiple Function And Legacy Space Access Control (4F-C6H)

    VX800 / VX820 Series System Programming Manual Multiple Function and Legacy Space Access Control (4F-C6h) Offset Address: 4Fh (D0F0) Multiple Function Control Default Value: 00h Attribute Default Description Reserved Multi-Function Support 0: Disable. Registers of functions 1-7 cannot be accessed, and the value returned will be 0FFFFFFFFh when accessed.

  • Page 18: Control Registers For Integrated Graphics / Video Processor (C7-Ffh)

    VX800 / VX820 Series System Programming Manual Control Registers for Integrated Graphics / Video Processor (C7-FFh) Offset Address: C7h (D0F0) – Reserved The integrated Graphics / Video processor uses up to two memory spaces; they are S.L. (System memory Local frame buffer) and MMIO.
  • Page 19 VX800 / VX820 Series System Programming Manual Offset Address: CB-C8h (D0F0) GFX Shadow Memory Base 0 - S.L. Default Value: FFF0 0000h Attribute Default Description 31:4 FFF0 000h GFX’s Memory Base 0 Address[31:4] for S.L. GFX’s Memory Base 0 Address[3:0] for S.L. Offset Address: CF-CCh (D0F0) GFX Shadow Memory Base 1 - MMIO Default Value: FFF0 0000h...

  • Page 20: Device 0 Function 1 (D0F1): Error Reporting

    Device 0 Function 1 (D0F1): Error Reporting Header Registers (00-3Fh) Offset Address: 01-00h (D0F1) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technologies ID Code Offset Address: 03-02h (D0F1) Device ID Default Value: 1353h Attribute Default Description 15:0 1353h Device ID Code...
  • Page 21 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D0F1) PCI Status Default Value: 0200h Attribute Default Description Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) Received Master-Abort (except special cycle) 0: No abort received 1: Transaction aborted by the Master...
  • Page 22 VX800 / VX820 Series System Programming Manual Offset Address: 0Eh (D0F1) Header Type Default Value: 00 or 80h Attribute Default Description 00 or 80h Header Type Could be 80 when D0F0 Rx4F[0] = 1 Offset Address: 0Fh (D0F1) Built In Self Test (BIST) Default Value: 00h Attribute Default...

  • Page 23: Host Bus Error Report (60-6Fh)

    VX800 / VX820 Series System Programming Manual Host Bus Error Report (60-6Fh) Offset Address: 60h (D0F1) Host Parity Status Default Value: 00h Attribute Default Description RW1C Host Address Parity Error Detected 0: Not detected 1: Detected RW1C Host Data Parity Error Detected 0: Not detected 1: Detected RW1C...

  • Page 24: Device 0 Function 2 (D0F2): Host Bus Control

    Device 0 Function 2 (D0F2): Host Bus Control Header Registers (00-3Fh) Offset Address: 01-00h (D0F2) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technologies ID Code Offset Address: 03-02h (D0F2) Device ID Default Value: 2353h Attribute Default Description 15:0 2353h Device ID Code...
  • Page 25 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D0F2) PCI Status Default Value: 0200h Attribute Default Description RW1C Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) RW1C Received Master-Abort (except special cycle) 0: No abort received...
  • Page 26 VX800 / VX820 Series System Programming Manual Offset Address: 0Fh (D0F2) Built In Self Test (BIST) Default Value: 00h Attribute Default Description BIST Support Hardwired to 0 (Not supported) Reserved Offset Address: 10-2Bh (D0F2) – Reserved Offset Address: 2D-2Ch (D0F2) Subsystem Vendor ID Default Value: 0000h Attribute...

  • Page 27: Host Cpu Control (50-5Fh)

    VX800 / VX820 Series System Programming Manual Host CPU Control (50-5Fh) Offset Address: 50h (D0F2) Request Phase Control Default Value: n0h Attribute Default Description IOQ (In-Order Queue) Depth 0: 1 level 1: 12 levels (or 8 levels. Please refer to Rx55[7] for details.) Default sets from the inverse of the SYSIDLE signal during system initialization.
  • Page 28 VX800 / VX820 Series System Programming Manual Offset Address: 52h (D0F2) CPU Interface Control – Advanced Option Default Value: 00h Attribute Default Description CPU 0WS Read / Write DRAM for Back-to-Back Pipeline Access 0: Disable 1: Enable HREQ (Host Continuous DRAM Ownership) / HPRI (Host High Priority DRAM Request) Assertion to DRAM Controller 0: Disable 1: Enable assertion of HREQ / HPRI to DRAM controller for efficient memory utilization / faster memory data...
  • Page 29 VX800 / VX820 Series System Programming Manual Offset Address: 55h (D0F2) Miscellaneous Control 2 Default Value: 20h Attribute Default Description Host Interface IOQ Size Rx50[7] Rx55[7] Host IF IOQ Size Reserved Reserved (Do not program) Early Read DRDY Assertion for Host Interface DRDY Table 0: 2T early 1: 3T early Reserved...

  • Page 30: Table 3. Cpu Write Request Policy

    VX800 / VX820 Series System Programming Manual Offset Address: 59h (D0F2) CPU Miscellaneous Control 1 Default Value: 08h Attribute Default Description Reserved Enable 8QW SDRAM Access for Direct Frame Buffer 0: 8QW access for direct frame buffer is disabled 1: 8QW access for direct frame buffer is enabled Warm CPU Reset (CPURST#) Duration Control 00: 475ns 01: 1050ns...

  • Page 31: Table 4. Host / Dram Bandwidth Policy

    VX800 / VX820 Series System Programming Manual Offset Address: 5Eh (D0F2) Bandwidth Timers Default Value: 00h Attribute Default Description Host Bandwidth Timer DRAM Bandwidth Timer Offset Address: 5Fh (D0F2) CPU Miscellaneous Control 3 Default Value: 00h Attribute Default Description Reserved Enable Reorder Retry Queue 0: Retried CPU transaction always complete in order 1: Allow second entry of retried (IOW/MEMW) transaction to complete before first queued entry...

  • Page 32: Host Interface Drdy Timing Control (60-6Fh)

    VX800 / VX820 Series System Programming Manual Host Interface DRDY Timing Control (60-6Fh) Offset Address: 60h (D0F2) DRDY Timing Control 1 for Read Line Access Default Value: 00h Attribute Default Description Read Line Phase 4 Wait State The number of wait states should be added into this phase. (n wait states mean nT delay) Read Line Phase 3 Wait State See the bit descriptions above.
  • Page 33 VX800 / VX820 Series System Programming Manual Offset Address: 64h (D0F2) DRDY Timing Control 2 for Read Quad-Word Access Default Value: 00h Attribute Default Description Read QW Phase 8 Wait State Refer to Rx60[7:6] bit descriptions for details. Read QW Phase 7 Wait State Refer to Rx60[7:6] bit descriptions for details.
  • Page 34 VX800 / VX820 Series System Programming Manual Offset Address: 68h (D0F2) APIC CPU Priority 0 Default Value: 00h Attribute Default Description Priority of CPU ID#0 Offset Address: 69h (D0F2) APIC CPU Priority 1 Default Value: 00h Attribute Default Description Priority of CPU ID#1 Offset Address: 6Ah (D0F2) APIC CPU Priority 2 Default Value: 00h...

  • Page 35: Host Agtl+ I/O Circuit (70-8Fh)

    VX800 / VX820 Series System Programming Manual Host AGTL+ I/O Circuit (70–8Fh) Offset Address: 70h (D0F2) Host Address Pad Pullup Driving Default Value: 00h Attribute Default Description Reserved Address Strobe Pad Pullup Driving – (HADSTB1#, HADSTB0#) Reserved Address Pad Pullup Driving – (HA[30, 16:03]#, HREQ[2:0]#) Offset Address: 71h (D0F2) Host Address Pad Pulldown Driving Default Value: 00h...
  • Page 36 VX800 / VX820 Series System Programming Manual Offset Address: 75h (D0F2) AGTL+ I/O Configuration 1 Default Value: 00h Attribute Default Description Reserved AGTL+ Slew Rate 0: Disable 1: Enable Reserved Behavior Control of AGTL+ Pull-up Termination for STROBE Signal 0: Pull-up termination of AGTL+ output buffer will be open-drained when driving STROBE signal of GTL bus from high to low.
  • Page 37 VX800 / VX820 Series System Programming Manual Offset Address: 76h (D0F2) AGTL+ I/O Configuration 2 Default Value: 0Ch Attribute Default Description Reserved Power Down Input Comparators of AGTL+ IO Buffers When Entering S3 State (Suspend to DRAM State) 0: Disable 1: Enable Reserved (Do not program) Disable DBI Function...
  • Page 38 VX800 / VX820 Series System Programming Manual Offset Address: 7Bh (D0F2) Input Host Address / Host Strobe Delay Control for HA Group Default Value: 18h HA lower address group definitions: HA30# HA[16:03]# HREQ[2:0]# Attribute Default Description Reserved 001b Host Address Input Delay Relative to Host Address Strobe for HA Lower Address Group 000: delay(data) = delay(strobe) –...
  • Page 39 VX800 / VX820 Series System Programming Manual Offset Address: 7Eh (D0F2) Host Address CKG Rising / Falling Time Control Default Value: 00h Attribute Default Description Falling Time Output Delay of HA Lower Address Group Signals* Delay the output at the physical macro before driven into the host bus. 00: Typical, falling edge transition time <...
  • Page 40 VX800 / VX820 Series System Programming Manual Offset Address: 81h (D0F2) Host Data / Strobe Input Delay Control 2 Default Value: 33h Attribute Default Description Reserved 011b Host Data Input Delay Relative to Host Data Strobe for HD/HDBI Group 3 000: delay(data) = delay(strobe) –...
  • Page 41 VX800 / VX820 Series System Programming Manual Offset Address: 84h (D0F2) Host Data / Strobe CKG Control (Group 0) Default Value: 00h Attribute Default Description Falling Time Output Delay of HDSTB0N# Signal 00: Typical, falling edge transition time < 50 ps 01: Falling edge transition time: 100 ps 10: Falling edge transition time: 200 ps 11: Falling edge transition time: 300 ps...
  • Page 42 VX800 / VX820 Series System Programming Manual Offset Address: 86h (D0F2) Host Data / Strobe CKG Control (Group 2) Default Value: 00h Attribute Default Description Falling Time Output Delay of HDSTB2N# Signal 00: Typical, falling edge transition time < 50 ps 01: Falling edge transition time: 100 ps 10: Falling edge transition time: 200 ps 11: Falling edge transition time: 300 ps...

  • Page 43: Miscellaneous Control (90-9Eh)

    VX800 / VX820 Series System Programming Manual Miscellaneous Control (90–9Eh) Offset Address: 90h (D0F2) Miscellaneous Control 3 Default Value: 08h Attribute Default Description Reserved Disable Continuous Data Pop to Host Bus 0: Enable continuous data pop to host bus 1: Disable continuous data pop to host bus Add One Pipe When Issuing Speculative Read 0: Disable 1: Enable...

  • Page 44: Device 0 Function 3 (D0F3): Dram Bus Control

    VX800 / VX820 Series System Programming Manual Device 0 Function 3 (D0F3): DRAM Bus Control There are three DDR2 DRAM controllers in this chip. Channel A: It can be 64 or 32 bits decided by Rx6C[5], and can also be used as the system memory. Channel C: It is dedicated to 16 bits, and can also store still display data in the snapshot mode.
  • Page 45 VX800 / VX820 Series System Programming Manual Offset Address: 05-04h (D0F3) PCI Command Default Value: 0006h Attribute Default Description 15:10 Reserved Fast Back-to-Back Cycle Enable Hardwired to 0 (Not supported) SERR# Enable Hardwired to 0 (Not supported) Address / Data Stepping Hardwired to 0 (Not supported) Parity Error Response 0: Ignore parity errors...
  • Page 46 VX800 / VX820 Series System Programming Manual Offset Address: 0B-09h (D0F3) Class Code Default Value: 06 0000h Attribute Default Description 23:0 060000h Class Code Offset Address: 0Ch (D0F3) – Reserved Offset Address: 0Dh (D0F3) Latency Timer Default Value: 00h Attribute Default Description Latency Timer...

  • Page 47: Dram Rank (Row) Ending / Beginning Address (40-4Fh)

    VX800 / VX820 Series System Programming Manual DRAM Rank (Row) Ending / Beginning Address (40–4Fh) Offset Address: 40h (D0F3) DRAM Rank 0 Ending Address Default Value: 01h Attribute Default Description Virtual Rank 0 Ending Address (Host Address Bits[33:26]) Offset Address: 41h (D0F3) DRAM Rank 1 Ending Address Default Value: 00h Attribute...
  • Page 48 VX800 / VX820 Series System Programming Manual Offset Address: 43h (D0F3) DRAM Rank 3 Ending Address Default Value: 00h Attribute Default Description Virtual Rank 3 Ending Address (Host Address Bits[33:26]) Offset Address: 44-47h (D0F3) – Reserved Offset Address: 48h (D0F3) DRAM Rank 0 Beginning Address Default Value: 00h Attribute...

  • Page 49: Ma Map / Command Rate (50-53H)

    VX800 / VX820 Series System Programming Manual MA Map / Command Rate (50–53h) Offset Address: 51-50h (D0F3) DRAM MA Map Type Default Value: 2022h Attribute Default Description 15:13 001b Rank 0 of Channel C MA Map Type (see the following table) Rank 0 of Channel C 1T Command Rate 0: Disable (2T command) 1: 1T command...

  • Page 50: Physical-To-Virtual Rank Mapping (54-57H)

    VX800 / VX820 Series System Programming Manual Table 7. DRAM Bank Address Table Rx53[6:4] for BA2 rsvd rsvd rsvd rsvd Rx52[2:0] for BA1 rsvd rsvd rsvd Rx52[6:4] for BA0 rsvd rsvd rsvd rsvd Table 8. Rank Interleave Address Table Rx53[3:2] for Rank Interleave Address Bit 1 Rx53[1:0] for Rank Interleave Address Bit 0 Notes.

  • Page 51: Virtual Rank Interleave Address Select / Enable (58-5Fh)

    VX800 / VX820 Series System Programming Manual Virtual Rank Interleave Address Select / Enable (58–5Fh) Offset Address: 58h (D0F3) Virtual Rank Interleave Address Select / Enable – Rank 0 Default Value: 00h Attribute Default Description Reserved Rank #0 Interleave Address Select (RINLV0AS[2:0]) This 3-bits field determines the Rank Interleave Address of Rank #0.

  • Page 52: Figure 1. Dimm / Channel Mapping Diagram

    VX800 / VX820 Series System Programming Manual Offset Address: 5Ch (D0F3) Virtual Rank Interleave Address Select / Enable – Rank 0 of Channel B Default Value: 00h Attribute Default Description Reserved Rank 0 of Channel B Interleave Address Select See the description on Rank 0 (Rx58). Reserved Rank 0 of Channel B Interleave Address Enable See the description on Rank 0 (Rx58).

  • Page 53: Dram Timing (60-64H)

    VX800 / VX820 Series System Programming Manual DRAM Timing (60–64h) Offset Address: 60h (D0F3) DRAM Pipeline Turn-Around Setting Default Value: 00h Attribute Default Description 0ws Back-to-Back Write to Different DDR Rank 0: Disable 1: Enable Fast Read-to-Read Turn Around 0: Disable 1: Enable (DQS post-amble overlap with preamble) Fast Read-to-Write Turn Around 0: Disable...
  • Page 54 VX800 / VX820 Series System Programming Manual Offset Address: 63h (D0F3) DRAM Timer for All Ranks 3 Default Value: 20h Attribute Default Description 001b Write Recovery Time (tWR) 000: 2T 001: 3T 010: 4T 011: 5T 100: 6T Others: reserved Reserved Read-to-Precharge Delay (tRTP) 0: 2T...

  • Page 55: Dram Queue / Arbitration (65-67H)

    VX800 / VX820 Series System Programming Manual DRAM Queue / Arbitration (65–67h) Offset Address: 65h (D0F3) DRAM Arbitration Timer Default Value: 00h Attribute Default Description AGP Timer (unit of 4 DCLKS) DRAMC time slot allocated for AGP device. Active when there is pending memory requests from other requesters.

  • Page 56: Dram Control (68-69H)

    VX800 / VX820 Series System Programming Manual DRAM Control (68–69h) Offset Address: 68h (D0F3) DDR2 Page Control 1 Default Value: 00h Attribute Default Description DRAM Expired Page Threshold Close expired pages with precharge-all command when the number of expired pages exceeds the value. Page Register Life Timer (in unit of 16 DCLKs) When timer expired, the expired page will be closed.

  • Page 57: Ddr Sdram Control (6C-6Fh)

    VX800 / VX820 Series System Programming Manual DDR SDRAM Control (6C–6Fh) Offset Address: 6Ch (D0F3) DRAM Type Default Value: C0h Attribute Default Description Reserved (Do not program) Memory Type Detected 0: DDR 1: DDR2 Enable 32-bit Memory Width Mode – Channel A 0: Disable 1: Enable Disable DQM Signals...
  • Page 58 VX800 / VX820 Series System Programming Manual Offset Address: 6Fh (D0F3) Miscellaneous Control Default Value: 42h Attribute Default Description Non-ONBD Protection for GART Table Fetching 0: Disable 1: Enable DRAM-Side-Input-Pointer Non-Return-Zero Mode 0: Disable 1: Enable Enable to avoid overwrite data Disallow the 2nd Cycle of a 2T Command Overlapped with Command of Different Type on a Different MA/SCMD Bus 0: Allow...

  • Page 59: Dram Signal Timing Control (70-7Fh)

    VX800 / VX820 Series System Programming Manual DRAM Signal Timing Control (70–7Fh) Offset Address: 70h (D0F3) DQS Output Delay - Channel A Default Value: 00h Attribute Default Description DQS Output Delay Offset Address: 71h (D0F3) MD Output Delay - Channel A Default Value: 00h Attribute Default...
  • Page 60 VX800 / VX820 Series System Programming Manual Offset Address: 76h (D0F3) Write Data Phase Control Default Value: 00h Attribute Default Description 1 More Pipeline Stage on Write Data Path Will provide safer timing margin. 1 More Pipeline Stage on Write Data Path for DDR2-667 and Above Will provide safer timing margin.
  • Page 61 VX800 / VX820 Series System Programming Manual Offset Address: 7Ah (D0F3) DQS Input Capture Range Control Default Value: 00h Attribute Default Description Reserved Select DQS Input Pin as Input Capture Range Detection Signal 0: DQSA0 1: DQSA4 DQS Input Capture Range Offset Value - Channel A 1/8T per step, 2’s complement Offset Address: 7Bh (D0F3) Read Data Phase Control...

  • Page 62: Read-Only Control (7C-7Fh)

    VX800 / VX820 Series System Programming Manual Read-Only Control (7C-7Fh) Offset Address: 7Ch (D0F3) DQS Input Delay Offset Control - Channel A Default Value: 00h Attribute Default Description Reserved DQS Input Delay Offset (In two’s complement) This is the offset values (in 2’s complement format) from the base delay value (Rx77[5:0]) for Channel A DIMM.

  • Page 63: Table 9. Cpu-To-Smram Cycle Flow

    VX800 / VX820 Series System Programming Manual Offset Address: 82h (D0F3) Page-E ROM Shadow Control Default Value: 00h Attribute Default Description EC000-EFFFFh Memory Space Access Control 00: Read from PCI. Write to PCI. 01: Read from PCI. Writer to DRAM. 10: Read from DRAM.

  • Page 64: Dram Above 4G Support (84-8Dh)

    VX800 / VX820 Series System Programming Manual DRAM Above 4G Support (84-8Dh) Offset Address: 84h (D0F3) Low Top Address - Low Default Value: 00h Attribute Default Description Low Top Address - A[23:20] Reserved Offset Address: 85h (D0F3) Low Top Address - High Default Value: FFh Attribute Default...
  • Page 65 VX800 / VX820 Series System Programming Manual Offset Address: 8Ch (D0F3) DQS Output Control Default Value: 00h Attribute Default Description Reserved MD/DQS Earlier Output Enable 0: Disable 1: Enable DQ Output Enable (MDOE) 1/2T earlier DQS Output Enable (DQSOE) 1/2T earlier if bit 0 =0 DQS Earlier Output Enable 0: Disable 1: Enable...

  • Page 66: Dram Clocking Control (90-9Fh)

    VX800 / VX820 Series System Programming Manual DRAM Clocking Control (90-9Fh) Offset Address: 90h (D0F3) DRAM Clock Operation Mode and Frequency Default Value: 00h Attribute Default Description DCLK Switch to Non-Feedback Mode 0: Feedback mode 1: Non-feedback mode (feed-forward mode). There is no need to feed DCLKO back through MCLKIN port.
  • Page 67 VX800 / VX820 Series System Programming Manual Offset Address: 95h (D0F3) By-Rank Self Refresh Related Registers - Channel A Default Value: 00h Attribute Default Description Check GFX Vertical Blank When Rank3 Enters By-Rank Self Refresh 0: Not check 1: Check Check Self-Refresh Request When Rank3 Enters By-Rank Self Refresh 0: Not check 1: Check...
  • Page 68 VX800 / VX820 Series System Programming Manual Offset Address: 98h (D0F3) DRAM Channel Pipeline Control Default Value: 00h Attribute Default Description Pipelining Stage on Request Page Decoding Improve DRAMC internal timing for DDR2-667 and above, but increase latency. 2T Page Close Command 2T Command Scheduling Improve DRAMC internal timing for DDR2-667 and above when Rx50 = 1, but may affect performance.
  • Page 69 VX800 / VX820 Series System Programming Manual Offset Address: 9Bh (D0F3) DRAM MD PADs ODTA[7:4] Pullup / Pulldown Control Default Value: 00h Attribute Default Description Reserved Enable DRAM MD Pad ODTA[7:4] 0: Disable ODT unless Rx9B[1] is not equal to 0 1: Enable ODT when reading data Reserved MD PAD ODTA[7:4] Pulldown/Pullup Enable –...

  • Page 70: Uma Registers (A0-Afh)

    VX800 / VX820 Series System Programming Manual UMA Registers (A0–AFh) Offset Address: A1-A0h (D0F3) CPU Direct Access Frame Buffer Control Default Value: 00h Attribute Default Description Integrated Graphics Enable 0: Disable 1: Enable 14:12 000b System Frame Buffer Size Selection – Channel A 000: none 001: 8M 010: 16M...
  • Page 71 VX800 / VX820 Series System Programming Manual Offset Address: A6h (D0F3) Page Register Life Timer 1 in CPU Power Saving States Default Value: 00h Attribute Default Description Reserved Enable Page Register Life Timer 1 in C4 State 0: Disable 1: Enable Enable Page Register Life Timer 1 in C3 State 0: Disable 1: Enable...

  • Page 72: Gmint And Agpcint Registers (B0-Bfh)

    VX800 / VX820 Series System Programming Manual GMINT and AGPCINT Registers (B0–BFh) Offset Address: B1-B0h (D0F3) GMINT Misc. 1 Default Value: 00h Attribute Default Description 15:12 GMINT Arbiter Timer for HighChannel-to-LowChannel Switching (unit of 16 DCLK) 11:8 GMINT Arbiter Timer for LowChannel-to-HighChannel Switching (unit of 16 DCLK) Bypass the MCLK Sync Logic for GFX-to-GMINT Signals 0: Sync the signals (1T) 1: Bypass the sync logic...
  • Page 73 VX800 / VX820 Series System Programming Manual Offset Address: B3h (D0F3) GMINT Misc. 2 Default Value: 9Eh Attribute Default Description 100b Flush Counter Used when RxB3[2] =1 & Write Queue Full For ex: if number =4, it will pop 4~5 write requests. Flush Counter Used when RxB3[1] =1 &...

  • Page 74: Ddr2 - I/O Pad Termination And Driving Control (D0-Dfh)

    VX800 / VX820 Series System Programming Manual DDR2 – I/O Pad Termination and Driving Control (D0–DFh) Offset Address: D0h (D0F3) DQ / DQS Termination Strength Manual Control Default Value: 00h Attribute Default Description DQ/DQS Pull-up Termination Strength Manual Setting DQ/DQS Pull-down Termination Strength Manual Setting Offset Address: D1h (D0F3) DQ / DQS Termination Strength Auto-Comp Status Default Value: 00h...

  • Page 75: Table 10. Md Pads Odt Control In Different Dram Mode

    VX800 / VX820 Series System Programming Manual Offset Address: D4h (D0F3) ODT Pullup / Pulldown Control Default Value: 00h Attribute Default Description Enable NM Pad ODT 0: Disable ODT unless RxD4[3:0] is not equal to 0 1: Enable ODT when reading data Enable DDR Pad Static Termination 0: Disable 1: Enable...
  • Page 76 VX800 / VX820 Series System Programming Manual Offset Address: D5h (D0F3) DQ / DQS Burst Function and ODT Range Select Default Value: 00h Attribute Default Description Enable DQ Burst Function – Channel A 0: Disable 1: Enable Enable DQ Burst Function – Channel C 0: Disable 1: Enable DQS Burst Function –...
  • Page 77 VX800 / VX820 Series System Programming Manual Offset Address: D7h (D0F3) SCMD/MA Burst Function Default Value: 00h Attribute Default Description SCMD/MAA Burst Function Enable 0: Disable 1: Enable Reserved Offset Address: D8h (D0F3) DCLKI Termination Strength Default Value: 00h Attribute Default Description DCLKI Pull-up Termination Strength...
  • Page 78 VX800 / VX820 Series System Programming Manual Command Type Command types will be triggered by bit RxDB[1] Type Ready/completion for Read/Write. This command must be triggered once before/after Read/Write command is issued. This command is only used by NM for preparing/terminating.
  • Page 79 VX800 / VX820 Series System Programming Manual Offset Address: DCh (D0F3) Timing Parameters Control – Channel C Default Value: 00h Attribute Default Description Read CAS Latency Normally, RxDC[7:6] = RxDF[7:6]. But if DRAM's DLL has been disabled, it might be set as (RxDF[7:6]-1) or (RxDF[7:6]+1) according to the actual read data timing.
  • Page 80 VX800 / VX820 Series System Programming Manual Offset Address: DEh (D0F3) GMINT’s Merge Function Default Value: 00h Attribute Default Description Reserved Disable GMINTA Merge Mode 0: Merge 2QW request 1: Disable 2QW merge Reserved Offset Address: DFh (D0F3) Write Cycle Timing Control – Channel C Default Value: 04h Attribute Default...

  • Page 81: Dram Driving Control (E0-Ebh)

    VX800 / VX820 Series System Programming Manual DRAM Driving Control (E0–EBh) Table 12. Physical Pin to Driving Group Mapping Table Physical Pins MCLK[A, B] CKE[A, B] CS[A, B] MA[A, B] DQ[A, B] DQS[A, B] DQM[A, B] Driving Group MCLK[A, B] CS[A, B] CS[A, B] MA[A, B]...
  • Page 82 VX800 / VX820 Series System Programming Manual Offset Address: E5h (D0F3) DRAM Driving – Group CSB (CS, DQM) Default Value: 00h Attribute Default Description CSB – PMOS Driving CSB – NMOS Driving Offset Address: E6h (D0F3) DRAM Driving – Group MCLKA Default Value: 00h Attribute Default...

  • Page 83: Dram Ckg Control (Ec-Efh)

    VX800 / VX820 Series System Programming Manual DRAM CKG Control (EC–EFh) Offset Address: ECh (D0F3) Channel-A DQS / DQ CKG Output Duty Cycle Control Default Value: 00h Attribute Default Description DQS CKG Falling Edge Control 00: Default 01: Falling edge delays 100 ps 10: Falling edge delays 200 ps 11: Falling edge delays 300 ps DQS CKG Rising Edge Control...

  • Page 84: Dq / Dqs Ckg Output Delay Control (F0-F9H)

    VX800 / VX820 Series System Programming Manual DQ / DQS CKG Output Delay Control (F0–F9h) Offset Address: F0-F3h (D0F3) DQ/DQS CKG Output Delay Control - Channel A Default Value: 0000 0000h Attribute Default Description Reserved 30:28 000b DQ/DQS Delay Control for Group A7 000: Default 001: Delay 60ps 010: Delay 120ps...

  • Page 85: Ddr2 - Dq De-Skew Control (Fa-Ffh)

    VX800 / VX820 Series System Programming Manual DDR2 – DQ De-Skew Control (FA–FFh) Offset Address: FAh (D0F3) DQ De-Skew Function Control Default Value: 40h Attribute Default Description Enable DQ Input De-Skew Circuit 0: Disable 1: Enable Manual DQ Output Delay Setting 0: Auto 1: Manual Manual DQ Input Delay Setting...
  • Page 86 VX800 / VX820 Series System Programming Manual Offset Address: FDh (D0F3) Power Management 1 Default Value: 00h Attribute Default Description Stop Page Timer’s Clock when DRAMCA’s Ranks All Enter Self Refresh 0: Free running 1: Enable dynamic Reserved Stop MCLKOA When All Ranks Enter Self Refresh 0: Free running 1: Enable dynamic Reserved...

  • Page 87: Table 13. Scmd And Ma Pins Power Saving Mode Setting

    VX800 / VX820 Series System Programming Manual DRAM Power Saving Mode Please refer to these following Power Saving Mode tables for the details of DRAM power management. Table 13. SCMD and MA Pins Power Saving Mode Setting Power Saving Mode Setting D0F4 RxA1[5] D0F3 RxFF[0] S1: Extra power saving mode...

  • Page 88: Device 0 Function 4 (D0F4): Power Management Control

    Device 0 Function 4 (D0F4): Power Management Control Header Registers (00-3Fh) Offset Address: 01-00h (D0F4) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technologies ID Code Offset Address: 03-02h (D0F4) Device ID Default Value: 4353h Attribute Default Description 15:0 4353h Device ID Code...
  • Page 89 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D0F4) PCI Status Default Value: 0200h Attribute Default Description RW1C Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) RW1C Received Master-Abort (except special cycle) 0: No abort received...

  • Page 90: Power Management Control (80-Efh)

    VX800 / VX820 Series System Programming Manual Offset Address: 0Fh (D0F4) Built In Self Test (BIST) Default Value: 00h Attribute Default Description BIST Support Hardwired to 0 (Not supported) Reserved Offset Address: 10-2Bh (D0F4) – Reserved Offset Address: 2D-2Ch (D0F4) Subsystem Vendor ID Default Value: 00h Attribute...
  • Page 91 VX800 / VX820 Series System Programming Manual Offset Address: 85h (D0F4) Central Traffic Controller Power Management Registers 2 Default Value: 00h Attribute Default Description Dynamic ECLK Control for Up-stream 0: Free-running clock 1: Dynamic clock Dynamic HCLK Control for PE0 Up-Stream Pop and Push 0: Free-running clock 1: Dynamic clock Dynamic HCLK Control for PE1 Up-Stream Pop and Push...
  • Page 92 VX800 / VX820 Series System Programming Manual Offset Address: 8Bh (D0F4) Data Path Module (DBX) Power Management Registers Default Value: 00h Attribute Default Description Power Management of C2M Read Cycle Data Bus of Channel-A (M2AI) 0: The pipeline of M2AI has free-running clocks 1: The pipeline of M2AI has dynamic clocks Power Management of C2M Read Cycle Data Bus of Channel-B (M2BI) 0: The pipeline of M2BI has free-running clocks...
  • Page 93 VX800 / VX820 Series System Programming Manual Offset Address: 8Eh (D0F4) PMU Related Registers 2 Default Value: 00h Attribute Default Description EPLL Gating Enable Option 0: Disable 1: Enable PLL_OK Source Selection from PLL or SM 0: Select PLL_OK from PLLs 1: Select PLL_OK from SM Suspend State PLL Always on Option 0: Suspend State will Reset/Turn_off PLLs...
  • Page 94 VX800 / VX820 Series System Programming Manual Offset Address: 91h (D0F4) P6IF Power Management Registers 2 Default Value: 00h Attribute Default Description Set as 1’b1 for the Case When BREQ0# Always Parks on the Host Bus. (e.g. VIA-Centaur CPU, CN Series) to Invoke Another Power –...
  • Page 95 VX800 / VX820 Series System Programming Manual Offset Address: A0h (D0F4) Power Management Mode Default Value: 00h Attribute Default Description Dynamic Power Management 0: Disable 1: Enable Power Management During HALT / SHUTDOWN 0: Disable 1: Enable Power Management During STPCLK 0: Disable 1: Enable Power Management During Suspend State...
  • Page 96 VX800 / VX820 Series System Programming Manual Offset Address: A5h (D0F4) Miscellaneous Control Default Value: 00h Attribute Default Description Dynamically Gates Phase Signals on Pseudo Synchronous Conversion Circuit Between Host/DRAM Interface 0: Disable 1: Enable Reserved Enable Dynamic Clock STOP for PE1 Port for PHY 0: Disable 1: Enable Offset Address: A6-A7h (D0F4) –...
  • Page 97 VX800 / VX820 Series System Programming Manual Offset Address: AAh (D0F4) PCIe Power Management Registers 2 Default Value: 00h Attribute Default Description Reserved L1 State PCIe Dynamic Clock Stop Control - PEG0 0: Disable dynamic clock 1: Enable dynamic clock L1 State PCIe Dynamic Clock Stop Control - PE0 0: Disable dynamic clock 1: Enable dynamic clock...
  • Page 98 VX800 / VX820 Series System Programming Manual Offset Address: AEh (D0F4) PCIe Power Management Registers 6 Default Value: 00h Attribute Default Description Reserved PEG0 250MHz ECLK Gated 0: This bit has no effect on ECLK 1: ECLK is gated by this bit from Clock Group Center PE0 250MHz ECLK Gated 0: This bit has no effect on ECLK 1: ECLK is gated by this bit from Clock Group Center...

  • Page 99: Device 0 Function 5 (D0F5): Apic And Central Traffic Control

    Header Registers (00–3Fh) Offset Address: 01-00h (D0F5) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technologies ID Code Offset Address: 03-02h (D0F5) Device ID Default Value: 5353h Attribute Default Description 15:0 5353h Device ID – For Power Management Control...
  • Page 100 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D0F5) PCI Status Default Value: 0000h Attribute Default Description RW1C Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) RW1C Received Master-Abort (except special cycle) 0: No abort received...

  • Page 101: Legacy Apic Base I/O Registers (40-5Fh)

    VX800 / VX820 Series System Programming Manual Offset Address: 0Fh (D0F5) Build In Self Test (BIST) Default Value: 00h Attribute Default Description Build In Self Test (BIST) Offset Address: 10-2Bh (D0F5) – Reserved Offset Address: 2D-2Ch (D0F5) Subsystem Vendor ID Default Value: 0000h Attribute Default...
  • Page 102 VX800 / VX820 Series System Programming Manual Offset Address: 41h (D0F5) APIC Legacy Address Range – y / z Default Value: 00h Attribute Default Description APIC Legacy Address Range – y Value can be programmed from 0h~Fh APIC Legacy Address Range – z Value can be programmed from 0h~Fh Offset Address: 42h (D0F5) APIC Interrupt Control...

  • Page 103: Central Traffic - Downstream Control (60-7Fh)

    VX800 / VX820 Series System Programming Manual Central Traffic - Downstream Control (60–7Fh) Offset Address: 60h (D0F5) Extended CFG Address Support Default Value: 28h Attribute Default Description Reserved Convert Device-2 CF8 Cycles to Device-1 while Passing it to the SM (in PCIe Mode) 0: CF8 access cycles are passed to the SM normally 1: CF8 with data[15:11]=00010 will be changed to data[15:11]=00001 CF8 Byte Write Enable...
  • Page 104 VX800 / VX820 Series System Programming Manual Offset Address: 64h (D0F5) Miscellaneous 1 Default Value: F2h Attribute Default Description Block P2P Request During Arbiter Disable 0: Non-block 1: Block Central Traffic Controller Split GFX 1/8QW Request Into DW Access 0: Disable 1: Enable Upstream MSI Cycles Forces Flush of the Queued P2C Write Data 0: Disable...

  • Page 105: Central Traffic - Upstream Control (80-85H)

    VX800 / VX820 Series System Programming Manual Central Traffic - Upstream Control (80-85h) Offset Address: 80h (D0F5) Central Traffic-Upstream Control 1 Default Value: 90h Attribute Default Description PCI Express (PEG0) Interface Selection 0: PCI Express (PEG0) interface is not supported 1: PCI Express (PEG0) interface is supported VC1 Upstream Path 0: VC1 requests are forwarded to the host side (snoop)
  • Page 106 VX800 / VX820 Series System Programming Manual Offset Address: 83h (D0F5) Downstream Arbitration Timeout Timer Control Default Value: 11h Attribute Default Description 0001b P2PW (PCI-to-PCI Write) Downstream Arbitration Timeout Timer (* 4 LCLK) 0000: Occupancy timer is off, i.e. the arbitration will be in a fairly RR scheme. 0001: 4 T 0010: 2 x 4 T …..

  • Page 107: Pcie Message Controller And Power Management (A0-Ffh)

    VX800 / VX820 Series System Programming Manual PCIe Message Controller and Power Management (A0–FFh) Offset Address: A0h (D0F5) PCIe PMU Control and Status Default Value: 00h Attribute Default Description PCI Express Wake Activation Control 0: Disable 1: Enable PCI Express PME SCI (System Control Interrupt to Indicate Power Management Event) Activation Control 0: Disable 1: Enable...
  • Page 108 VX800 / VX820 Series System Programming Manual Offset Address: A3h (D0F5) PMU Control 1 Default Value: 00h Attribute Default Description Downstream Address Bit [7] This bit is used for monitoring S3/S4/S5 downstream command. Refers to RxA2 for address [15:8]. Reserved Monitor S3/S4/S5 Command 0: Disable 1: Enable...
  • Page 109 VX800 / VX820 Series System Programming Manual Offset Address: F1h (D0F5) Device 1 / 2 Configuration Control 1 Default Value: 02h Attribute Default Description Reserved Device 1 Exist or Not 0: Absent 1: Exist Device 2 Function 1 Exist or Not 0: Absent 1: Exist Offset Address: F2h (D0F5) –...

  • Page 110: Device 0 Function 6 (D0F6): Scratch Registers

    Device 0 Function 6 (D0F6): Scratch Registers Header Registers (00-3Fh) Offset Address: 01-00h (D0F6) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technologies ID Code Offset Address: 03-02h (D0F6) Device ID Default Value: 6353h Attribute Default Description 15:0 6353h Device ID Code...
  • Page 111 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D0F6) PCI Status Default Value: 0000h Attribute Default Description RW1C Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) RW1C Received Master-Abort (except special cycle) 0: No abort received...

  • Page 112: Scratch Registers (40-7F)

    VX800 / VX820 Series System Programming Manual Offset Address: 0Eh (D0F6) Header Type Default Value: 00 or 80h Attribute Default Description 00 or 80h Header Type Could be 80 when D0F0 Rx4F[0] = 1 Offset Address: 0Fh (D0F6) Built In Self Test (BIST) Default Value: 00h Attribute Default...

  • Page 113: Hash Data Control Registers (C0-Ffh)

    VX800 / VX820 Series System Programming Manual Offset Address: 6F-60h (D0F6) BIOS Scratch Register 3 Default Value: 0 Attribute Default Description 127:0 BIOS Scratch Register Offset Address: 7F-70h (D0F6) BIOS Scratch Register 4 Default Value: 0 Attribute Default Description 127:0 BIOS Scratch Register Offset Address: 80-BFh (D0F6) –...
  • Page 114 VX800 / VX820 Series System Programming Manual Offset Address: CCh (D0F6) TPM (Trusted Platform Module) Function Support Default Value: 00h Attribute Default Description Forward CPU Cycle to Protected TPM Reserved Range 00: The host controller will forward the CPU cycle which hits TPM reserved range to the SM. Others: The host controller will accept the CPU cycle which hits TPM reserved range, but will not do anything further.
  • Page 115 VX800 / VX820 Series System Programming Manual Offset Address: E3-E0h (D0F6) Hash Data Base Address Low Default Value: 0000 0000h Attribute Default Description 31:2 Hash Data Base Address[31:2] Reserved Offset Address: E5-E4h (D0F6) Hash Data Base Address High Default Value: 0000h Attribute Default Description...

  • Page 116: Device 0 Function 7 (D0F7): North-South Module Interface Control

    Header Registers (00-3Fh) Offset Address: 01-00h (D0F7) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technologies ID Code Offset Address: 03-02h (D0F7) Device ID Default Value: 7353h Attribute Default Description 15:0 7353h Device ID – North-South Module Interface...
  • Page 117 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D0F7) PCI Status Default Value: 0200h Attribute Default Description RW1C Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) RW1C Received Master-Abort (except special cycle) 0: No abort received...
  • Page 118 VX800 / VX820 Series System Programming Manual Offset Address: 0Eh (D0F7) Header Type Default Value: 00h Attribute Default Description Header Type Offset Address: 0Fh (D0F7) Built In Self Test (BIST) Default Value: 00h Attribute Default Description BIST Support Hardwired to 0 (Not supported) Reserved Offset Address: 10-2Bh (D0F7) –...

  • Page 119: North-South Module Interface Control (40-60H)

    VX800 / VX820 Series System Programming Manual North-South Module Interface Control (40–60h) Offset Address: 40h (D0F7) Miscellaneous Control Default Value: 00h Attribute Default Description Reserved Options of Combining Multiple STPGNT Cycles into NSMIC Command 00: Compatible mode: a NSMIC command per STPGNT cycle 01: Combines 2 STPGNT cycles into a NSMIC command 10: Combines 3 STPGNT cycles into a NSMIC command 11: Combines 4 STPGNT cycles into a NSMIC command...
  • Page 120 VX800 / VX820 Series System Programming Manual Offset Address: 62h (D0F7) Page-D ROM Shadow Control Default Value: 00h Attribute Default Description DC000-DFFFF 00: Read/Write disable 01: Write enable 10: Read enable 11: Read/Write enable D8000-DBFFF D4000-D7FFF D0000-D3FFF Offset Address: 63h (D0F7) Page-E ROM Shadow Control Default Value: 00h Attribute...

  • Page 121: Host-Pci Bridge Control (70-Ffh)

    VX800 / VX820 Series System Programming Manual Host-PCI Bridge Control (70-FFh) Offset Address: 70h (D0F7) – Reserved Offset Address: 71h (D0F7) CPU to PCI Flow Control Default Value: 00h Attribute Default Description Reserved Compatible TYPE#1 Configuration Cycle AD31 0: Fixed AD31 1: AD31 will be 1’b0.

  • Page 122: Device 2 Function 0 (D2F0) - Pci Express Root Port G0 (Pci-To-Pci Virtual Bridge)

    VX800 / VX820 Series System Programming Manual Device 2 Function 0 (D2F0) – PCI Express Root Port G0 (PCI-to-PCI Virtual Bridge) Device 2 Function 0, a 4-Lane PCI Express Root Port, is connected to the PCI bus through AD14 as the IDSEL. All registers are located in PCI configuration space and should be programmed using PCI configuration mechanism 1 through I/O registers CF8 / CFC with Bus Number 0, Device Number 2 and Function Number 0.

  • Page 123: Header Registers (00-3Fh)

    VX800 / VX820 Series System Programming Manual Header Registers (00-3Fh) Offset Address: 01-00h (D2F0) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h Vendor ID Offset Address: 03-02h (D2F0) Device ID Default Value: C353h Attribute Default Description 15:0 C353h Device ID Offset Address: 05-04h (D2F0) PCI Command...
  • Page 124 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D2F0) PCI Status Default Value: 0010h Attribute Default Description RW1C Detected Parity Error This bit is set whenever a poisoned TLP is received, regardless the state of Parity Error Enabled (Rx4[6]). RW1C Signaled System Error This bit is set when:...
  • Page 125 VX800 / VX820 Series System Programming Manual Offset Address: 0Dh (D2F0) Master Latency Timer Default Value: 00h Attribute Default Description Master Latency Timer Reserved Offset Address: 0Eh (D2F0) Header Type Default Value: 01h Attribute Default Description Header Type Offset Address: 0Fh (D2F0) Built In Self Test (BIST) Default Value: 00h Attribute...
  • Page 126 VX800 / VX820 Series System Programming Manual Offset Address: 1Ch (D2F0) I/O Base Default Value: F0h Attribute Default Description I/O Base (AD[15:12] - Inclusive) This bridge will forward the cycles from primary side to PCI if the I/O address AD[15:12] is between I/O base and I/O limit.
  • Page 127 VX800 / VX820 Series System Programming Manual Offset Address: 25-24h (D2F0) Prefetchable Memory Base Default Value: FFF1h Attribute Default Description 15:4 FFFh Prefetchable Memory Base AD[31:20] Reserved Report Support Prefetchable 64 Bits Memory Addressing 0: Not supported 1: Supported Offset Address: 27-26h (D2F0) Prefetchable Memory Limit Default Value: 0001h Attribute...
  • Page 128 VX800 / VX820 Series System Programming Manual Offset Address: 34h (D2F0) Capability Pointer Default Value: 40h Attribute Default Description Capability Pointer This register contains the offset address from the start of the configuration space. Always reads 40h. Capability Pointer link list: Rx34 Rx40 Rx68 Rx70...
  • Page 129 VX800 / VX820 Series System Programming Manual Offset Address: 35-3Bh (D2F0) – Reserved Offset Address: 3Ch (D2F0) Interrupt Line Default Value: 00h Attribute Default Description INT Line (For Software Use Only) Offset Address: 3Dh (D2F0) Interrupt Pin Default Value: 01h Attribute Default Description...

  • Page 130: Pci Express Capability Registers (40-67H)

    VX800 / VX820 Series System Programming Manual PCI Express Capability Registers (40-67h) Offset Address: 41-40h (D2F0) PCI Express List Default Value: 6810h Attribute Default Description 15:8 Next Pointer Capability ID 10h indicates a PCI Express Capability Structure. Offset Address: 43-42h (D2F0) PCI Express Capabilities Default Value: 0141h Attribute...
  • Page 131 VX800 / VX820 Series System Programming Manual Offset Address: 49-48h (D2F0) Device Control Default Value: 0000h Attribute Default Description Reserved 14:12 000b Max Read Request Size 000b: 128 bytes This field sets the maximum Read Request size for the device as a Requestor. Enable No Snoop 0: Disable 1: Enable...
  • Page 132 VX800 / VX820 Series System Programming Manual Offset Address: 4F-4Ch (D2F0) Link Capabilities Default Value: 0118 3C41h Attribute Default Description 31:24 Port Number This field indicates the PCI Express Port number for the given PCI Express Link. 23:21 Reserved Data Link Layer Link Active Reporting Capable 0: Not supported 1: Supported Surprise Down Error Reporting Capable...
  • Page 133 VX800 / VX820 Series System Programming Manual Offset Address: 53-52h (D2F0) Link Status Default Value: 1nn1h Attribute Default Description 15:14 Reserved Data Link Layer Link Active 0: Inactive 1: Active Slot Clock Configuration 0: Use an independent clock irrespective of the presence of a reference on the connector. 1: Use the same physical reference clock that the platform provides on the connector.
  • Page 134 VX800 / VX820 Series System Programming Manual Offset Address: 59-58h (D2F0) Slot Control Default Value: 0000h Attribute Default Description 15:13 Reserved Enable Data Link Layer State Change Report 0: Disable 1: Enable Electromechanical Interlock Control 0: Disable 1: Enable Power Controller Control Reserved Power Indicator Control Reserved...
  • Page 135 VX800 / VX820 Series System Programming Manual Offset Address: 5D-5Ch (D2F0) Root Control Default Value: 0000h Attribute Default Description 15:5 Reserved CRS Software Visibility Enable 0: Disable 1: Enable the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software. PME Interrupt Enable 0: Disable 1: Enable interrupt generation upon receipt of a PME message as reflected in the PME status register bit.

  • Page 136: Pci Power Management Capability Structure Registers (68-6Fh)

    VX800 / VX820 Series System Programming Manual PCI Power Management Capability Structure Registers (68-6Fh) Offset Address: 6B-68h (D2F0) Power Management Capabilities Default Value: C822 7001h Attribute Default Description 31:27 PME Support 0: Not supported 1: Supported Bit 31, 30 and 27 are set to 1b (PME Message will be forwarded). D2 Support 0: Not supported 1: Supported...

  • Page 137: Pci Message Signal Interrupt (Msi) Capability Structure Registers (70-87H)

    VX800 / VX820 Series System Programming Manual PCI Message Signal Interrupt (MSI) Capability Structure Registers (70-87h) Offset Address: 73-70h (D2F0) MSI Capability Support Default Value: 0180 9805h Attribute Default Description 31:25 Reserved Supports Pre-vector Masking Capability 0: Not supported 1: Supported Supports 64 Bit Message Address Only 0: Not supported 1: Supported...

  • Page 138: Message Signal Interrupt (Msi) Capability Registers (88-97H)

    VX800 / VX820 Series System Programming Manual Offset Address: 83-80h (D2F0) Message Mask Control Default Value: 0000 0000h Attribute Default Description 31:1 Reserved Mask Bit for Message 0 0: Not masked 1: Mask message 0 Offset Address: 87-84h (D2F0) Message Pending Status Default Value: 0000 0000h Attribute Default...

  • Page 139: Pci Express Transaction Layer Registers (A0-Afh)

    VX800 / VX820 Series System Programming Manual PCI Express Transaction Layer Registers (A0-AFh) Offset Address: A0h (D2F0) Downstream Control 1 Default Value: 11h Attribute Default Description Downstream Cycles Have Traffic Class TC1 0: Disable 1: Enable Downstream Cycles Have Attribute “No Snoop” Set 0: Disable 1: Enable Downstream Cycles Have Attribute “Relaxed Ordering”...
  • Page 140 VX800 / VX820 Series System Programming Manual Offset Address: A2h (D2F0) Downstream Control 3 Default Value: 30h Attribute Default Description Downstream Ordering Queue Timing O ption 0: 1T setup time 1: 2T setup time 011b Waiting Time for GNT Timer in Priority Arbitration Mode 000: 4 ns 001: 16 ns 010: 32 ns...
  • Page 141 VX800 / VX820 Series System Programming Manual Offset Address: A4h (D2F0) Upstream Control Default Value: 1Dh Attribute Default Description Force Upstream Address A35~A31 to 0 0: Disable 1: Enable for system testing or loop back mode test. The upcoming data may be checked in the system memory. Reserved Upstream Check Malformed TLP through “Byte Enable Rule”...
  • Page 142 VX800 / VX820 Series System Programming Manual Offset Address: A6h (D2F0) Credit Advertisement Control 2 Default Value: 7Fh Attribute Default Description Upstream Non-Posted Header Credit Infinite Mode Control 0: The non-posted header credit is finite and has to update NPH credits. 1: The non-posted header credit is infinite and not necessary to update NPH credits.

  • Page 143: Pci Express Data Link Layer Registers (B0-Bfh)

    VX800 / VX820 Series System Programming Manual Offset Address: A9h (D2F0) CRS Retry Control Default Value: 00h Attribute Default Description Reserved Enable CRS Retry Mechanism 0: No retry cycle for CRS regardless of Rx5C[4] setting and return ‘hffffffff for read cycles. 1: Follow Rx5C[4] setting.
  • Page 144 VX800 / VX820 Series System Programming Manual Offset Address: B3h (D2F0) Replay Timer Control Default Value: 81h Attribute Default Description Replay Timer Control While Rewinding (resend those DLLPs which do not have corresponded ACK / NAK received) 00: Hold Replay Timer during rewinding. 01: During rewinding, if ACK / NAK comes in, reset and hold the Replay Timer.
  • Page 145 VX800 / VX820 Series System Programming Manual Offset Address: B5h (D2F0) FCU Control Default Value: 00h Attribute Default Description Reserved FCU Timer Control 0: Update flow control credit when either Transaction Layer requested packets being sent or when FCU timer expired.
  • Page 146 VX800 / VX820 Series System Programming Manual Offset Address: B8h (D2F0) Data Link Layer Header Position Default Value: 00h Attribute Default Description Reserved Data Link Layer Header Position 0: SDP (Start DLLP) can be in Lane 0 / 4 / 8 / 12. 1: SDP (Start DLLP) always at Lane 0.
  • Page 147 VX800 / VX820 Series System Programming Manual Offset Address: BDh (D2F0) Replay Timer Limit 1 Default Value: 12h Attribute Default Description Replay_timer_limit in Large LSNLW Setting This timer is used for Replay_timer when LSNLW is x16. 00h: 8 x 1 Clocks (Clock = 250Mhz) 01h: 8 x 2 Clocks 02h: 8 x 3 Clocks …….

  • Page 148: Pci Express Physical Layer Registers (C0-Cfh)

    VX800 / VX820 Series System Programming Manual PCI Express Physical Layer Registers (C0-CFh) Offset Address: C0h (D2F0) PHY General Control Default Value: 03h Attribute Default Description Quick Timeout Counter Setting When set to 1, PHY timeout period will be shorter as below: 2 ms 4 us 12 ms...
  • Page 149 VX800 / VX820 Series System Programming Manual Offset Address: C1h (D2F0) PHYLS General Control Default Value: 00h Attribute Default Description Reserved Enable Aggressive Power Management When No Device Plug 0: Disable 1: Enable Enable Aggressive Power Management in Rx Path to Data Link Layer Module 0: Disable 1: Enable 00000b...

  • Page 150: Table 16. Mapping Table For D2F0 Rxc3

    VX800 / VX820 Series System Programming Manual Offset Address: C3h (D2F0) PHYLS LTSSM State Default Value: 00h Attribute Default Description PHYLS LTSSM State See the table below. Table 16. Mapping Table for D2F0 RxC3 LTSSM States Binary Coding Hexadecimal Coding DETECT_QUIET 8'B0000_0000 8’H00...
  • Page 151 VX800 / VX820 Series System Programming Manual Offset Address: C4h (D2F0) Elastic Buffer Base Registers for Lane 0 to 1 Default Value: 04h Attribute Default Description Reserved Elastic Buffer Base Register for Lane 0 0, 1, 7: Illegal values. Others: Delay numbers of T for elastic buffer operations. Offset Address: C5-CCh (D2F0) –...

  • Page 152: Pci Express Power Management Module Registers (D0-D3H)

    VX800 / VX820 Series System Programming Manual PCI Express Power Management Module Registers (D0-D3h) Offset Address: D0h (D2F0) Power Management Controller PHYLS Control Default Value: 50h Attribute Default Description Reserved 101b Timeout Period This timer is used when waiting for ACK from a device after issued PME_TURNOFF message to notify the device to move to power down mode.

  • Page 153: Pci Express Message Controller Related Registers (D8-Dfh)

    VX800 / VX820 Series System Programming Manual Offset Address: D3h (D2F0) PMU L1 Idle Timeout Default Value: 00h Attribute Default Description Idle Period to Enter ASL1 Minimum time period is 128 ns. 00h: 128 ns 01h: 2x128 ns 02h: 3x128 ns …...
  • Page 154 VX800 / VX820 Series System Programming Manual Offset Address: E2h (D2F0) 6 Lanes PHYES Module Control – Rx/Tx 1 Default Value: 00h Attribute Default Description Reserved Mobile Swing 0: Disable 1: Enable PHYES Clock Buffer Power Down on Lane 0-5 0: All enable 1: Power down Lane Clock Buffer Power Down...

  • Page 155: Pci Express Electrical Phy Test Registers (F0-Ffh)

    VX800 / VX820 Series System Programming Manual PCI Express Electrical PHY Test Registers (F0-FFh) Offset Address: F0h (D2F0) – Reserved Offset Address: F1h (D2F0) Repeated Count of the Test Pattern Default Value: 00h Attribute Default Description Repeated Count of the Test Pattern (as selected in RxF2[7:4]) When using loopback mode to test electrical PHY, the following should be satisfied: RxF1 x 8 >...
  • Page 156 VX800 / VX820 Series System Programming Manual Offset Address: F5-F4h (D2F0) BIST Status 1 Default Value: 0000h Attribute Default Description 15:10 Reserved Received Symbol (When RxF3[7] is set to 1) 00: When RxF3[7] is 0. Offset Address: F7-F6h (D2F0) BIST Status 2 Default Value: 0000h Attribute Default...

  • Page 157: Device 2 Function 0 (D2F0) - Pci Express Root Port G0 Extended Space

    VX800 / VX820 Series System Programming Manual Device 2 Function 0 (D2F0) – PCI Express Root Port G0 Extended Space Registers defined in the Extended Space can be accessed through PCI Express Enhanced Configuration Access Mechanism, which utilizes a flat memory-mapped address space to access the configuration registers. Please check PCI Express Specification for the detailed information.
  • Page 158 VX800 / VX820 Series System Programming Manual Offset Address: 10F-10Ch (D2F0) Uncorrectable Error Severity Default Value: 0006 2031h Attribute Default Description 31:21 Reserved Unsupported Request Error Severity (TL) ECRC Error Severity (TL) Malformed TLP Severity (TL) Receiver Overflow Error Severity (TL) Unexpected Completion Error Severity (TL) Completed Abort Error Severity (TL) Completion Timeout Error Severity (TL)
  • Page 159 VX800 / VX820 Series System Programming Manual Offset Address: 11F-11Ch (D2F0) Header Log (TL) Register 1st DW Default Value: 0000 0000h Attribute Default Description 31:0 Header Log Register 1st DW Offset Address: 123-120h (D2F0) Header Log (TL) Register 2nd DW Default Value: 0000 0000h Attribute Default...

  • Page 160: Virtual Channel Capability (140-14Fh)

    VX800 / VX820 Series System Programming Manual Virtual Channel Capability (140-14Fh) Virtual Channel Capability is defined for Egress direction of the device. For Root Port, since only VC0 is defined. VC0 mapping: TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 No VC arbitration table No port arbitration table Offset Address: 143-140h (D2F0)

  • Page 161: Vc0 Resource (150-15Bh)

    VX800 / VX820 Series System Programming Manual VC0 Resource (150-15Bh) Offset Address: 153-150h (D2F0) VC Resource Capability (VC0) Default Value: 0000 0000h Attribute Default Description 31:24 Port Arbitration Table Offset (VC0) Reserved for Root Port. Reserved 22:16 Maximum Time Slots (TL) Reject Snoop Transactions Advanced Packet Switching Reserved...

  • Page 162: Vc1 Resource (15C-19Fh)

    VX800 / VX820 Series System Programming Manual VC1 Resource (15C-19Fh) Offset Address: 15C-17Fh (D2F0) – Reserved Offset Address: 183-180h (D2F0) Root Complex Link Declaration Capabilities Header Default Value: 0001 0005h Attribute Default Description 31:20 Next Capability 19:16 Capability Version 15:0 0005h Capability ID Bit[15:0]=0005 indicates the Extended Capability ID for the Root Complex Link Declaration Capability.

  • Page 163: Device 3 Function 0 (D3F0) - Pci Express Root Port 0 (Pci-To-Pci Virtual Bridge)

    VX800 / VX820 Series System Programming Manual Device 3 Function 0 (D3F0) – PCI Express Root Port 0 (PCI-to-PCI Virtual Bridge) Device 3 Function 0, a 1-Lane PCI Express Root Port, is connected to the PCI bus through AD14 as the IDSEL. All registers are located in PCI configuration space and should be programmed using PCI configuration mechanism 1 through I/O registers CF8 / CFC with Bus Number 0, Device Number 3 and Function Number 0.
  • Page 164 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D3F0) PCI Status Default Value: 0010h Attribute Default Description RW1C Detected Parity Error This bit is set whenever a poisoned TLP is received, regardless the state of Parity Error Enabled (Rx4[6]). RW1C Signaled System Error This bit is set when:...
  • Page 165 VX800 / VX820 Series System Programming Manual Offset Address: 0Eh (D3F0) Header Type Default Value: 81h Attribute Default Description Header Type Offset Address: 0Fh (D3F0) Built In Self Test (BIST) Default Value: 00h Attribute Default Description BIST Support Offset Address: 17-10h (D3F0) Base Address Register Default Value: 0000 0000 0000 0000h Attribute...
  • Page 166 VX800 / VX820 Series System Programming Manual Offset Address: 1Dh (D3F0) I/O Limit Default Value: 00h Attribute Default Description I/O Limit (AD[15:12] - Inclusive) This bridge will forward the cycles from primary side to PCI if the I/O address is between I/O base (Rx1C) and I/O limit.
  • Page 167 VX800 / VX820 Series System Programming Manual Offset Address: 27-26h (D3F0) Prefetchable Memory Limit Default Value: 0001h Attribute Default Description 15:4 Prefetchable Memory Limit AD[31:20] Reserved Report Support Prefetchable 64 Bits Memory Addressing 0: Not supported 1: Supported Offset Address: 2B-28h (D3F0) Prefetchable Memory Upper Base Default Value: 0000 0000h Attribute...
  • Page 168 VX800 / VX820 Series System Programming Manual Cap. PTR = 40h Capabilities Pointer Rx34 PCI Express Capabilities Register Next Cap = 68h Cap. ID=10h … Rx40 PCI Power Management Capabilities Structur Next Cap = 70h Cap. ID=01h … Registers Rx68 PCI MSI Capability Next Cap = 98h Cap.
  • Page 169 VX800 / VX820 Series System Programming Manual Offset Address: 3Dh (D3F0) Interrupt Pin Default Value: 01h Attribute Default Description INT Pin = INTA# Offset Address: 3F-3Eh (D3F0) Bridge Control Default Value: 0000h Attribute Default Description 15:7 Reserved Secondary Bus Reset 0: No reset.

  • Page 170: Pci Express Capability Registers (40-67H)

    VX800 / VX820 Series System Programming Manual PCI Express Capability Registers (40-67h) Offset Address: 41-40h (D3F0) PCI Express List Default Value: 6810h Attribute Default Description 15:8 Next Pointer Capability ID 10h indicates a PCI Express Capability Structure. Offset Address: 43-42h (D3F0) PCI Express Capabilities Default Value: 0141h Attribute...
  • Page 171 VX800 / VX820 Series System Programming Manual Offset Address: 49-48h (D3F0) Device Control Default Value: 0000h Attribute Default Description Reserved 14:12 000b Max Read Request Size 000b: 128 bytes This field sets the maximum Read Request size for the device as a Requestor. Enable No Snoop 0: Disable 1: Enable...
  • Page 172 VX800 / VX820 Series System Programming Manual Offset Address: 4F-4Ch (D3F0) Link Capabilities Default Value: 0218 3C11h Attribute Default Description 31:24 Port Number This field indicates the PCI Express Port number for the given PCI Express Link. 23:21 Reserved Data Link Layer Link Active Reporting Capable 0: Not supported 1: Supported Surprise Down Error Reporting Capable...
  • Page 173 VX800 / VX820 Series System Programming Manual Offset Address: 53-52h (D3F0) Link Status Default Value: 1nn1h Attribute Default Description 15:14 Reserved Data Link Layer Link Active 0: Inactive 1: Active Slot Clock Configuration 0: Use an independent clock irrespective of the presence of a reference on the connector. 1: Use the same physical reference clock that the platform provides on the connector.
  • Page 174 VX800 / VX820 Series System Programming Manual Offset Address: 59-58h (D3F0) Slot Control Default Value: 0000h Attribute Default Description 15:13 Reserved Enable Data Link Layer State Change Report 0: Disable 1: Enable Electromechanical Interlock Control 0: Disable 1: Enable Power Controller Control Reserved Power Indicator Control Reserved...
  • Page 175 VX800 / VX820 Series System Programming Manual Offset Address: 5D-5Ch (D3F0) Root Control Default Value: 0000h Attribute Default Description 15:5 Reserved CRS Software Visibility Enable 0: Disable 1: Enable the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software. PME Interrupt Enable 0: Disable 1: Enable interrupt generation upon receipt of a PME message as reflected in the PME status register bit.

  • Page 176: Pci Power Management Capability Structure Registers (68-6Fh)

    VX800 / VX820 Series System Programming Manual PCI Power Management Capability Structure Registers (68-6Fh) Offset Address: 6B-68h (D3F0) Power Management Capabilities Default Value: C822 7001h Attribute Default Description 31:27 PME Support 0: Not supported 1: Supported Bit 31, 30 and 27 are set to 1b (PME Message will be forwarded). D2 Support 0: Not supported 1: Supported...

  • Page 177: Pci Message Signal Interrupt (Msi) Capability Structure Registers (70-87H)

    VX800 / VX820 Series System Programming Manual PCI Message Signal Interrupt (MSI) Capability Structure Registers (70-87h) Offset Address: 73-70h (D3F0) MSI Capability Support Default Value: 0180 9805h Attribute Default Description 31:25 Reserved Supports Pre-vector Masking Capability 0: Not supported 1: Supported Supports 64 Bit Message Address Only 0: Not supported 1: Supported...

  • Page 178: Message Signal Interrupt (Msi) Capability Registers (88-97H)

    VX800 / VX820 Series System Programming Manual Offset Address: 83-80h (D3F0) Message Mask Control Default Value: 0000 0000h Attribute Default Description 31:1 Reserved Mask Bit for Message 0 0: Not masked 1: Mask message 0 Offset Address: 87-84h (D3F0) Message Pending Status Default Value: 0000 0000h Attribute Default...

  • Page 179: Pci Express Transaction Layer Registers (A0-Afh)

    VX800 / VX820 Series System Programming Manual PCI Express Transaction Layer Registers (A0-AFh) Offset Address: A0h (D3F0) Downstream Control 1 Default Value: 11h Attribute Default Description Downstream Cycles Have Traffic Class TC1 0: Disable 1: Enable Downstream Cycles Have Attribute “No Snoop” Set 0: Disable 1: Enable Downstream Cycles Have Attribute “Relaxed Ordering”...
  • Page 180 VX800 / VX820 Series System Programming Manual Offset Address: A2h (D3F0) Downstream Control 3 Default Value: 30h Attribute Default Description Downstream Ordering Queue Timing Option 0: 1T setup time 1: 2T setup time 011b Waiting Time for GNT Timer in Priority Arbitration Mode 000: 4 ns 001: 16 ns 010: 32 ns...
  • Page 181 VX800 / VX820 Series System Programming Manual Offset Address: A4h (D3F0) Upstream Control Default Value: 1Dh Attribute Default Description Force Upstream Address A35~A31 to 0 0: Disable 1: Enabled for system testing or loop back mode test. The upcoming data may be checked in the system memory. Reserved Upstream Check Malformed TLP through “Byte Enable Rule”...
  • Page 182 VX800 / VX820 Series System Programming Manual Offset Address: A6h (D3F0) Credit Advertisement Control 2 Default Value: 7Fh Attribute Default Description Upstream Non-Posted Header Credit Infinite Mode Control 0: The non-posted header credit is finite and has to update NPH credits. 1: The non-posted header credit is infinite and not necessary to update NPH credits.

  • Page 183: Pci Express Data Link Layer Registers (B0-Bfh)

    VX800 / VX820 Series System Programming Manual Offset Address: A9h (D3F0) CRS Retry Control Default Value: 00h Attribute Default Description Reserved Enable of CRS Retry Mechanism 0: No retry cycle for CRS, regardless of Rx5C[4] setting and return ‘hffffffff for read cycles. 1: Follow Rx5C[4] setting.
  • Page 184 VX800 / VX820 Series System Programming Manual Offset Address: B3h (D3F0) Replay Timer Control Default Value: 81h Attribute Default Description Replay Timer Control While Rewinding (resend those DLLPs which do not have corresponded ACK / NAK received) 00: Hold Replay Timer during rewinding. 01: During rewinding, if ACK / NAK comes in, reset and hold the Replay Timer.
  • Page 185 VX800 / VX820 Series System Programming Manual Offset Address: B5h (D3F0) FCU Control Default Value: 00h Attribute Default Description Reserved FCU Timer Control 0: Update flow control credit when either Transaction Layer requested packets being sent or when FCU timer expired.
  • Page 186 VX800 / VX820 Series System Programming Manual Offset Address: B8h (D3F0) Data Link Layer Header Position Default Value: 00h Attribute Default Description Reserved Data Link Layer Header Position 0: SDP (Start DLLP) can be in Lane 0 / 4 / 8 / 12. 1: SDP (Start DLLP) is always at Lane 0.
  • Page 187 VX800 / VX820 Series System Programming Manual Offset Address: BDh (D3F0) Replay Timer Limit 1 Default Value: 12h Attribute Default Description Replay_timer_limit in Large LSNLW Setting This timer is used for Replay_timer when LSNLW is x16. 00h: 8 x 1 Clocks (Clock = 250Mhz) 01h: 8 x 2 Clocks 02h: 8 x 3 Clocks …….

  • Page 188: Pci Express Physical Layer Registers (C0-Cfh)

    VX800 / VX820 Series System Programming Manual PCI Express Physical Layer Registers (C0-CFh) Offset Address: C0h (D3F0) PHY General Control Default Value: 03h Attribute Default Description Quick Timeout Counter Setting When set to 1, PHY timeout period will be shorter as below: 2 ms 4 us 12 ms...
  • Page 189 VX800 / VX820 Series System Programming Manual Offset Address: C1h (D3F0) PHYLS General Control Default Value: 00h Attribute Default Description Reserved Enable Aggressive Power Management When No Device Plug 0: Disable 1: Enable Enable Aggressive Power Management in Rx Path to Data Link Layer Module 0: Disable 1: Enable 00000b...

  • Page 190: Table 17. Mapping Table For D3F0 Rxc3

    VX800 / VX820 Series System Programming Manual Offset Address: C3h (D3F0) PHYLS LTSSM State Default Value: 00h Attribute Default Description PHYLS LTSSM State See the table below. Table 17. Mapping Table for D3F0 RxC3 LTSSM States Binary Coding (RxC3) Hexadecimal Coding DETECT_QUIET 8'B0000_0000 8’H00...
  • Page 191 VX800 / VX820 Series System Programming Manual Offset Address: C4h (D3F0) Elastic Buffer Base Registers for Lane 0 to 1 Default Value: 04h Attribute Default Description Reserved Elastic Buffer Base Register for Lane 0 0, 1, 7: Illegal values. Others: Delay numbers of T for elastic buffer operations. Offset Address: C5-CCh (D3F0) –...

  • Page 192: Pci Express Power Management Module Registers (D0-D3H)

    VX800 / VX820 Series System Programming Manual PCI Express Power Management Module Registers (D0-D3h) Offset Address: D0h (D3F0) Power Management Controller PHYLS Control Default Value: 50h Attribute Default Description Reserved 101b Timeout Period This timer is used when waiting for ACK from a device after issued PME_TURNOFF message to notify the device to move to power down mode.

  • Page 193: Pci Express Message Controller Related Registers (D8-Dfh)

    VX800 / VX820 Series System Programming Manual Offset Address: D3h (D3F0) PMU L1 Idle Timeout Default Value: 00h Attribute Default Description Idle Period to Enter ASL1 Minimum time period is 128 ns. 00h: 128 ns 01h: 2x128 ns 02h: 3x128 ns …...

  • Page 194: Pci Express Electrical Phy Test Registers (F0-Ffh)

    VX800 / VX820 Series System Programming Manual PCI Express Electrical PHY Test Registers (F0-FFh) Offset Address: F0h (D3F0) – Reserved Offset Address: F1h (D3F0) Repeated Count of the Test Pattern Default Value: 00h Attribute Default Description Repeated Count of the Test Pattern (as selected in RxF2[7:4]) When using loopback mode to test electrical PHY, the following should be satisfied: RxF1 x 8 >...
  • Page 195 VX800 / VX820 Series System Programming Manual Offset Address: F5-F4h (D3F0) BIST Status 1 Default Value: 0000h Attribute Default Description 15:10 Reserved Received Symbol (When RxF3[7] is set 1) 10b’0: When RxF3[7] is 0. Offset Address: F7-F6h (D3F0) BIST Status 2 Default Value: 0000h Attribute Default...

  • Page 196: Device 3 Function 0 (D3F0) - Pci Express Root Port 0 Extended Space

    VX800 / VX820 Series System Programming Manual Device 3 Function 0 (D3F0) – PCI Express Root Port 0 Extended Space Registers defined in the Extended Space can be accessed through PCI Express Enhanced Configuration Access Mechanism, which utilizes a flat memory-mapped address space to access the configuration registers. Please check PCI Express Specification for the detailed information.
  • Page 197 VX800 / VX820 Series System Programming Manual Offset Address: 10F-10Ch (D3F0) Uncorrectable Error Severity Default Value: 0006 2031h Attribute Default Description 31:21 Reserved Unsupported Request Error Severity (TL) ECRC Error Severity (TL) Malformed TLP Severity (TL) Receiver Overflow Error Severity (TL) Unexpected Completion Error Severity (TL) Completed Abort Error Severity (TL) Completion Timeout Error Severity (TL)
  • Page 198 VX800 / VX820 Series System Programming Manual Offset Address: 11F-11Ch (D3F0) Header Log (TL) Register 1st DW Default Value: 0000 0000h Attribute Default Description 31:0 Header Log Register 1st DW Offset Address: 123-120h (D3F0) Header Log (TL) Register 2nd DW Default Value: 0000 0000h Attribute Default...

  • Page 199: Virtual Channel Capability (140-14Fh)

    VX800 / VX820 Series System Programming Manual Virtual Channel Capability (140-14Fh) Virtual Channel Capability is defined for Egress direction of the device. For Root Port, since only VC0 is defined. VC0 mapping: TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 No VC arbitration table No port arbitration table Offset Address: 143-140h (D3F0)

  • Page 200: Vc0 Resource (150-15Bh)

    VX800 / VX820 Series System Programming Manual VC0 Resource (150-15Bh) Offset Address: 153-150h (D3F0) VC Resource Capability (VC0) Default Value: 0000 0000h Attribute Default Description 31:24 Port Arbitration Table Offset (VC0) Reserved for Root Port. Reserved 22:16 Maximum Time Slots (TL) Reject Snoop Transactions Advanced Packet Switching Reserved...

  • Page 201: Vc1 Resource (15C-19Fh)

    VX800 / VX820 Series System Programming Manual VC1 Resource (15C-19Fh) Offset Address: 15C-17Fh (D3F0) – Reserved Offset Address: 183-180h (D3F0) Root Complex Link Declaration Capabilities Header Default Value: 0001 0005h Attribute Default Description 31:20 Next Capability 19:16 Capability Version 15:0 0005h Capability ID Offset Address: 187-184h (D3F0)

  • Page 202: Device 3 Function 1 (D3F1) - Pci Express Root Port 1 (Pci-To-Pci Virtual Bridge)

    VX800 / VX820 Series System Programming Manual Device 3 Function 1 (D3F1) – PCI Express Root Port 1 (PCI-to-PCI Virtual Bridge) Device 3 Function 1, a 1-Lane PCI Express Root Port, is connected to the PCI bus through AD14 as the IDSEL. All registers are located in PCI configuration space and should be programmed using PCI configuration mechanism 1 through I/O registers CF8 / CFC with Bus Number 0, Device Number 3 and Function Number 1.
  • Page 203 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D3F1) PCI Status Default Value: 0010h Attribute Default Description RW1C Detected Parity Error This bit is set whenever a poisoned TLP is received, regardless the state of Parity Error Enabled (Rx4[6]). RW1C Signaled System Error This bit is set when:...
  • Page 204 VX800 / VX820 Series System Programming Manual Offset Address: 0Eh (D3F1) Header Type Default Value: 81h Attribute Default Description Header Type Offset Address: 0Fh (D3F1) Built In Self Test (BIST) Default Value: 00h Attribute Default Description BIST Support Offset Address: 17-10h (D3F1) Base Address Register Default Value: 0000 0000 0000 0000h Attribute...
  • Page 205 VX800 / VX820 Series System Programming Manual Offset Address: 1Dh (D3F1) I/O Limit Default Value: 00h Attribute Default Description I/O Limit (AD[15:12] - Inclusive) This bridge will forward the cycles from primary side to PCI if the I/O address is between I/O base (Rx1C) and I/O limit.
  • Page 206 VX800 / VX820 Series System Programming Manual Offset Address: 27-26h (D3F1) Prefetchable Memory Limit Default Value: 0001h Attribute Default Description 15:4 Prefetchable Memory Limit AD[31:20] Reserved Report Support Prefetchable 64 Bits Memory Addressing 0: Not supported 1: Supported Offset Address: 2B-28h (D3F1) Prefetchable Memory Upper Base Default Value: 0000 0000h Attribute...
  • Page 207 VX800 / VX820 Series System Programming Manual Cap. PTR = 40h Capabilities Pointer Rx34 PCI Express Capabilities Register Next Cap = 68h Cap. ID=10h … Rx40 PCI Power Management Capabilities Structur Next Cap = 70h Cap. ID=01h … Registers Rx68 PCI MSI Capability Next Cap = 98h Cap.
  • Page 208 VX800 / VX820 Series System Programming Manual Offset Address: 3F-3Eh (D3F1) Bridge Control Default Value: 0000h Attribute Default Description 15:7 Reserved Secondary Bus Reset 0: No reset. 1: Triggers a warm reset on the corresponding PCI Express Port. Reserved Base VGA 16 Bits Decode 0: All VGA alias range will be forwarded.

  • Page 209: Pci Express Capability Registers (40-67H)

    VX800 / VX820 Series System Programming Manual PCI Express Capability Registers (40-67h) Offset Address: 41-40h (D3F1) PCI Express List Default Value: 6810h Attribute Default Description 15:8 Next Pointer Capability ID 10h indicates a PCI Express Capability Structure. Offset Address: 43-42h (D3F1) PCI Express Capabilities Default Value: 0141h Attribute...
  • Page 210 VX800 / VX820 Series System Programming Manual Offset Address: 49-48h (D3F1) Device Control Default Value: 0000h Attribute Default Description Reserved 14:12 000b Max Read Request Size 000b: 128 bytes This field sets the maximum Read Request size for the device as a Requestor. Enable No Snoop 0: Disable 1: Enable...
  • Page 211 VX800 / VX820 Series System Programming Manual Offset Address: 4F-4Ch (D3F1) Link Capabilities Default Value: 0318 3C11h Attribute Default Description 31:24 Port Number This field indicates the PCI Express Port number for the given PCI Express Link. 23:21 Reserved Data Link Layer Link Active Reporting Capable 0: Not supported 1: Supported Surprise Down Error Reporting Capable...
  • Page 212 VX800 / VX820 Series System Programming Manual Offset Address: 53-52h (D3F1) Link Status Default Value: 1nn1h Attribute Default Description 15:14 Reserved Data Link Layer Link Active 0: Inactive 1: Active Slot Clock Configuration 0: Use an independent clock irrespective of the presence of a reference on the connector. 1: Use the same physical reference clock that the platform provides on the connector.
  • Page 213 VX800 / VX820 Series System Programming Manual Offset Address: 59-58h (D3F1) Slot Control Default Value: 0000h Attribute Default Description 15:13 Reserved Enable Data Link Layer State Change Report 0: Disable 1: Enable Electromechanical Interlock Control 0: Disable 1: Enable Power Controller Control Reserved Power Indicator Control Reserved...
  • Page 214 VX800 / VX820 Series System Programming Manual Offset Address: 5D-5Ch (D3F1) Root Control Default Value: 0000h Attribute Default Description 15:5 Reserved CRS Software Visibility Enable 0: Disable 1: Enable the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software. PME Interrupt Enable 0: Disable 1: Enable interrupt generation upon receipt of a PME message as reflected in the PME status register bit.

  • Page 215: Pci Power Management Capability Structure Registers (68-6Fh)

    VX800 / VX820 Series System Programming Manual PCI Power Management Capability Structure Registers (68-6Fh) Offset Address: 6B-68h (D3F1) Power Management Capabilities Default Value: C822 7001h Attribute Default Description 31:27 PME Support 0: Not supported 1: Supported Bit 31, 30 and 27 are set to 1b (PME Message will be forwarded). D2 Support 0: Not supported 1: Supported...

  • Page 216: Pci Message Signal Interrupt (Msi) Capability Structure Registers (70-87H)

    VX800 / VX820 Series System Programming Manual PCI Message Signal Interrupt (MSI) Capability Structure Registers (70-87h) Offset Address: 73-70h (D3F1) MSI Capability Support Default Value: 0180 9805h Attribute Default Description 31:25 Reserved Supports Pre-vector Masking Capability 0: Not supported 1: Supported Supports 64 Bit Message Address Only 0: Not supported 1: Supported...

  • Page 217: Message Signal Interrupt (Msi) Capability Registers (88-97H)

    VX800 / VX820 Series System Programming Manual Offset Address: 83-80h (D3F1) Message Mask Control Default Value: 0000 0000h Attribute Default Description 31:1 Reserved Mask Bit for Message 0 0: Not masked 1: Mask message 0 Offset Address: 87-84h (D3F1) Message Pending Status Default Value: 0000 0000h Attribute Default...

  • Page 218: Pci Express Transaction Layer Registers (A0-Afh)

    VX800 / VX820 Series System Programming Manual PCI Express Transaction Layer Registers (A0-AFh) Offset Address: A0h (D3F1) Downstream Control 1 Default Value: 11h Attribute Default Description Downstream Cycles Have Traffic Class TC1 0: Disable 1: Enable Downstream Cycles Have Attribute “No Snoop” Set 0: Disable 1: Enable Downstream Cycles Have Attribute “Relaxed Ordering”...
  • Page 219 VX800 / VX820 Series System Programming Manual Offset Address: A2h (D3F1) Downstream Control 3 Default Value: 30h Attribute Default Description Downstream Ordering Queue Timing Option 0: 1T setup time 1: 2T setup time 011b Waiting Time for GNT Timer in Priority Arbitration Mode 000: 4 ns 001: 16 ns 010: 32 ns...
  • Page 220 VX800 / VX820 Series System Programming Manual Offset Address: A4h (D3F1) Upstream Control Default Value: 1Dh Attribute Default Description Force Upstream Address A35~A31 to 0 0: Disable 1: Enabled for system testing or loop back mode test. The upcoming data may be checked in the system memory. Reserved Upstream Check Malformed TLP through “Byte Enable Rule”...
  • Page 221 VX800 / VX820 Series System Programming Manual Offset Address: A8-A7h (D3F1) Upstream Performance Control Default Value: 01C4h Attribute Default Description C2P Completion Timeout Method when PHY Retrains or Re-configures 0: Keep the timeout value 1: Reset the timeout value Reserved 13:12 Configuration request timeout timer 00: 100 ms...

  • Page 222: Pci Express Data Link Layer Registers (B0-Bfh)

    VX800 / VX820 Series System Programming Manual PCI Express Data Link Layer Registers (B0-BFh) Offset Address: B0h-B1h (D2F0) – Reserved Offset Address: B2h (D3F1) Flow Control Initialization / Flow Control Unit and Status Default Value: 40h Attribute Default Description RW1C FCI / FCU Timeout Status 0: No time out 1 The FCI / FCU timeout has occurred.
  • Page 223 VX800 / VX820 Series System Programming Manual Offset Address: B4h (D3F1) Arbitration Control Default Value: 05h Attribute Default Description Reserved TLP Flow Control Initialization for VC0 in Arbitration 0: TLP is not allowed to pass Flow Control Initialization 2 (FCI2) for VC0. 1: TLP is allowed to pass Flow Control Initialization 2 (FCI2) for VC0.
  • Page 224 VX800 / VX820 Series System Programming Manual Offset Address: B7h (D3F1) – Reserved Offset Address: B8h (D3F1) Data Link Layer Header Position Default Value: 00h Attribute Default Description Reserved Data Link Layer Header Position 0: SDP (Start DLLP) can be in Lane 0 / 4 / 8 / 12. 1: SDP (Start DLLP) is always at Lane 0.
  • Page 225 VX800 / VX820 Series System Programming Manual Offset Address: BDh (D3F1) Replay Timer Limit 1 Default Value: 12h Attribute Default Description Replay_timer_limit in Large LSNLW Setting This timer is used for Replay_timer when LSNLW is x16. 00h: 8 x 1 Clocks (Clock = 250Mhz) 01h: 8 x 2 Clocks 02h: 8 x 3 Clocks …….

  • Page 226: Pci Express Physical Layer Registers (C0-Cfh)

    VX800 / VX820 Series System Programming Manual PCI Express Physical Layer Registers (C0-CFh) Offset Address: C0h (D3F1) PHY General Control Default Value: 03h Attribute Default Description Quick Timeout Counter Setting When set to 1, PHY timeout period will be shorter as below: 2 ms 4 us 12 ms...
  • Page 227 VX800 / VX820 Series System Programming Manual Offset Address: C1h (D3F1) PHYLS General Control Default Value: 00h Attribute Default Description Reserved Enable Aggressive Power Management when No Device Plug 0: Disable 1: Enable Enable Aggressive Power Management in Rx Path to Data Link Layer Module 0: Disable 1: Enable 00000b...

  • Page 228: Table 18. Mapping Table For D3F1 Rxc3

    VX800 / VX820 Series System Programming Manual Offset Address: C3h (D3F1) PHYLS LTSSM State Default Value: 00h Attribute Default Description PHYLS LTSSM State See the table below Table 18. Mapping Table for D3F1 RxC3 LTSSM States Binary Coding (RxC3) Hexadecimal Coding DETECT_QUIET 8'B0000_0000 8’H00...
  • Page 229 VX800 / VX820 Series System Programming Manual Offset Address: C4h (D3F1) Elastic Buffer Base Registers for Lane 0 to 1 Default Value: 04h Attribute Default Description Reserved Elastic Buffer Base Register for Lane 0 0, 1, 7: Illegal values. Others: Delay numbers of T for elastic buffer operations. Offset Address: C5-CCh (D3F1) –...

  • Page 230: Pci Express Power Management Module Registers (D0-D3H)

    VX800 / VX820 Series System Programming Manual PCI Express Power Management Module Registers (D0-D3h) Offset Address: D0h (D3F1) Power Management Controller PHYLS Control Default Value: 50h Attribute Default Description Reserved 101b Timeout Period This timer is used when waiting for ACK from a device after issued PME_TURNOFF message to notify the device to move to power down mode.

  • Page 231: Pci Express Message Controller Related Registers (D8-Dfh)

    VX800 / VX820 Series System Programming Manual Offset Address: D3h (D3F1) PMU L1 Idle Timeout Default Value: 00h Attribute Default Description Idle Period to Enter ASL1 Minimum time period is 128 ns. 00h: 128 ns 01h: 2x128 ns 02h: 3x128 ns …...

  • Page 232: Pci Express Electrical Phy Registers (E0-Efh)

    VX800 / VX820 Series System Programming Manual PCI Express Electrical PHY Registers (E0-EFh) Offset Address: E0h (D3F1) – Reserved Offset Address: E1h (D3F1) 1 Lane Related Control of PHYES Module Default Value: 08h Attribute Default Description Reserved Receiving Polarity Change Control 0: Have the same polarity on the loop-back / received data.

  • Page 233: Pci Express Electrical Phy Test Registers (F0-Ffh)

    VX800 / VX820 Series System Programming Manual PCI Express Electrical PHY Test Registers (F0-FFh) Offset Address: F1h (D3F1) Repeated Count of the Test Pattern Default Value: 00h Attribute Default Description Repeated Count of the Test Pattern (as selected in RxF2[7:4]) When using loopback mode to test electrical PHY, the following should be satisfied: RxF1 x 8 >...
  • Page 234 VX800 / VX820 Series System Programming Manual Offset Address: F5-F4h (D3F1) BIST Status 1 Default Value: 00h Attribute Default Description 15:10 Reserved Received Symbol (When RxF3[7] is set 1) 10b’0: When RxF3[7] is 0. Offset Address: F7-F6h (D3F1) BIST Status 2 Default Value: 0000h Attribute Default...

  • Page 235: Device 3 Function 1 (D3F1) - Pci Express Root Port 1 Extended Space

    VX800 / VX820 Series System Programming Manual Device 3 Function 1 (D3F1) – PCI Express Root Port 1 Extended Space Registers defined in the Extended Space can be accessed through PCI Express Enhanced Configuration Access Mechanism, which utilizes a flat memory-mapped address space to access the configuration registers. Please check PCI Express Specification for the detail information.
  • Page 236 VX800 / VX820 Series System Programming Manual Offset Address: 10F-10Ch (D3F1) Uncorrectable Error Severity Default Value: 0006 2031h Attribute Default Description 31:21 Reserved Unsupported Request Error Severity (TL) ECRC Error Severity (TL) Malformed TLP Severity (TL) Receiver Overflow Error Severity (TL) Unexpected Completion Error Severity (TL) Completed Abort Error Severity (TL) Completion Timeout Error Severity (TL)
  • Page 237 VX800 / VX820 Series System Programming Manual Offset Address: 11F-11Ch (D3F1) Header Log (TL) Register 1st DW Default Value: 0000 0000h Attribute Default Description 31:0 Header Log Register 1st DW Offset Address: 123-120h (D3F1) Header Log (TL) Register 2nd DW Default Value: 0000 0000h Attribute Default...

  • Page 238: Virtual Channel Capability (140-14Fh)

    VX800 / VX820 Series System Programming Manual Virtual Channel Capability (140-14Fh) Virtual Channel Capability is defined for Egress direction of the device. For Root Port, since only VC0 is defined. VC0 mapping: TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 No VC arbitration table No port arbitration table Offset Address: 143-140h (D3F1)

  • Page 239: Vc0 Resource (150-15Bh)

    VX800 / VX820 Series System Programming Manual VC0 Resource (150-15Bh) Offset Address: 153-150h (D3F1) VC Resource Capability (VC0) Default Value: 0000 0000h Attribute Default Description 31:24 Port Arbitration Table Offset (VC0) Reserved for Root Port. Reserved 22:16 Maximum Time Slots (TL) Reject Snoop Transactions Advanced Packet Switching Reserved...

  • Page 240: Vc1 Resource (15C-19Fh)

    VX800 / VX820 Series System Programming Manual VC1 Resource (15C-19Fh) Offset Address: 15C-17Fh (D3F1) – Reserved Offset Address: 183-180h (D3F1) Root Complex Link Declaration Capabilities Header Default Value: 0001 0005h Attribute Default Description 31:20 Next Capability 19:16 Capability Version 15:0 0005h Capability ID Offset Address: 187-184h (D3F1)

  • Page 241: Pci Express Root Complex Register Block - Host

    VX800 / VX820 Series System Programming Manual PCI Express Root Complex Register Block – Host Virtual Channel Capability (000-00Fh) Offset Address: 003-000h (RCRB-H) Virtual Channel Enhanced Capability Header Default Value: 0401 0002h Attribute Default Description 31:20 040h Next Capability Offset 19:16 Capability Version 15:0...

  • Page 242: Vc0 Resource (010-01Bh)

    VX800 / VX820 Series System Programming Manual VC0 Resource (010-01Bh) Offset Address: 013-010h (RCRB-H) VC Resource Capability (VC0) Default Value: 0000 0001h Attribute Default Description 31:24 Port Arbitration Table (VC0) Reserved 22:16 Maximum Time Slots (TL) Reserved Reject Snoop Transactions Reserved Advanced Packet Switching Reserved...

  • Page 243: Root Complex Link Declaration Enhanced Capability (040-04Fh)

    VX800 / VX820 Series System Programming Manual Root Complex Link Declaration Enhanced Capability (040-04Fh) Offset Address: 043-040h (RCRB-H) Root Complex Link Declaration Capabilities Header Default Value: 0001 0005h Attribute Default Description 31:20 Next Capability 19:16 Capability Version 15:0 0005h PCI Express Extended Capability ID Offset Address: 047-044h (RCRB-H) Element Self Description Default Value: 0001 0401h...

  • Page 244: Link Entry For Pe0 (060-06Fh)

    VX800 / VX820 Series System Programming Manual Link Entry for PE0 (060-06Fh) Offset Address: 063-060h (RCRB-H) PE0 Link Description Default Value: 0201 0003h Attribute Default Description 31:24 Target Port Number 23:16 Target Component ID 15:2 Reserved Link Type Link points to PE0. Link Valid Offset Address: 064-067h (RCRB-H) –...

  • Page 245: Link Entry For Hdac (080-08Fh)

    VX800 / VX820 Series System Programming Manual Link Entry for HDAC (080-08Fh) Offset Address: 083-080h (RCRB-H) HDAC Link Description Default Value: 0401 0003h Attribute Default Description 31:24 Target Port Number 23:16 Target Component ID 15:2 Reserved Link Type Link points to HDAC. Link Valid Offset Address: 084-087h (RCRB-H) –...

  • Page 246: Vc Arbitration Timer (200-20Fh)

    VX800 / VX820 Series System Programming Manual VC Arbitration Timer (200-20Fh) The arbitration schemes of PCI Express and DRAM controller are the same. Occupancy Timer is used to guarantee the number of time slots so that one requester will be granted when there is no high priority requester. Promote Timer is used for a requester to upgrade its requests to high priority if it is not served after the Promote Timer times out.
  • Page 247 VX800 / VX820 Series System Programming Manual Offset Address: 212h (RCRB-H) PE0 Occupancy Timer Default Value: 00h Attribute Default Description Reserved 0000b Occupancy Timer (in unit of 125MHz) 0000: Timer is off 0nh: n x 4 T, where 1< n <= 15 Offset Address: 213h (RCRB-H) PE0 Promote Timer Default Value: 00h...

  • Page 248: Host Side Upstream Arbitration Timers (230-23Fh)

    VX800 / VX820 Series System Programming Manual Host Side Upstream Arbitration Timers (230-23Fh) A fair arbitration timer is designed for the upstream traffic, which provides a fair arbitration between PCI express devices and other devices like PCI2 master, IO APIC and North-South Module Interface Control. The arbitration scheme is also used by DRAM controller.
  • Page 249 VX800 / VX820 Series System Programming Manual Offset Address: 238h (RCRB-H) IGFX Arbitration Control Default Value: 00h Attribute Default Description Strict Priority to GADS from IGFX 0: Disable 1: Enable Reserved 0000b Occupancy Timer (in unit of host frequency) 0000: Timer is off 0nh: n x 4 T, where 1<...

  • Page 250: Pxptrf (Central Traffic Controller) P2P Arbitration Timer Of Pcie (250-253H)

    VX800 / VX820 Series System Programming Manual PXPTRF (Central Traffic Controller) P2P Arbitration Timer of PCIe (250-253h) Offset Address: 250-251h (RCRB-H) – Reserved Offset Address: 252h (RCRB-H) P2P Occupancy Timer Default Value: 00h Attribute Default Description Reserved 0000b Occupancy Timer (in unit of host frequency) 0000: Timer is off 0nh: n x 4 T, where 1<...

  • Page 251: South Module Register Descriptions

    VX800 / VX820 Series System Programming Manual OUTH ODULE EGISTER ESCRIPTIONS Legacy I/O Ports This group of registers includes the DMA Controllers, Interrupt Controllers, and Timer/Counters as well as a number of miscellaneous ports originally implemented by using discrete logic on original PC/AT motherboards. All the registers listed are integrated on-chip.
  • Page 252 VX800 / VX820 Series System Programming Manual I/O Port Address: 61h Miscellaneous Functions & Speaker Control Default Value: 00h Attribute Default Description SERR# Status 0: SERR# has not been asserted 1: SERR# was asserted by a PCI agent Note: This bit is set when the PCI bus SERR# signal is asserted. Once set, this bit may be cleared by setting bit-2 of this register.

  • Page 253: Keyboard Controller I/O Registers

    VX800 / VX820 Series System Programming Manual Keyboard Controller I/O Registers The keyboard controller handles the keyboard and mouse interfaces. Two ports are used: port 60 and port 64. Reads from port 64 return a status byte. Writes to port 64h are command codes (see command code list following the register descriptions). Input and output data is transferred via port 60h.
  • Page 254 VX800 / VX820 Series System Programming Manual I/O Port Address: 60h Keyboard Controller Input / Output Buffer Attribute Description When Write: Keyboard Controller Input Buffer Only write to port 60h if port 64h bit-1 = 0 (1=full). When Read: Keyboard Controller Output Buffer Only read from port 60h if port 64h bit-0 = 1 (0=empty).

  • Page 255: Table 19. Keyboard Controller Command Codes

    VX800 / VX820 Series System Programming Manual I/O Port Address: 64h (When Write) Keyboard / Mouse Command This port is used to send commands to the keyboard / mouse controller. The command codes recognized by this chip are listed in the table below. Table 19.
  • Page 256 VX800 / VX820 Series System Programming Manual KBC Control Register (R/W via Commands 20h/60h) Attribute Default Description Reserved PC Compatibility 0: Disable scan conversion 1: Convert scan codes to PC format; convert 2-byte break sequences to 1-byte PC-compatible break codes. Mouse Interface 0: Enable 1: Disable...

  • Page 257: Dma Controller I/O Registers

    VX800 / VX820 Series System Programming Manual DMA Controller I/O Registers I/O Ports Address: 00-0Fh Master DMA Controller Channels 0-3 of the Master DMA Controller control System DMA Channels 0-3. There are 16 Master DMA Controller registers: I/O Address Bits 15-0 Attribute Description 0000 0000 000x 0000...

  • Page 258: Dma Controller Shadow Registers

    VX800 / VX820 Series System Programming Manual I/O Ports Address: 80-8Fh DMA Page Registers There are eight DMA Page Registers, one for each DMA channel. These registers provide bits 16-23 of the 24-bit address for each DMA channel (address bits 0-15 are stored in registers in the Master and Slave DMA Controllers). They are located at the following I/O Port addresses: I/O Address Bits 15-0 Attribute...

  • Page 259: Interrupt Controller I/O Registers

    VX800 / VX820 Series System Programming Manual Interrupt Controller I/O Registers This chip integrates two Interrupt Controllers, Master and Slave Interrupt Controllers, either one is compatible with the Intel 8259 Interrupt Controller chip. Detailed descriptions of 8259 Interrupt Controller operations can be obtained from the Intel Peripheral Components Data Book and numerous other industry publications.

  • Page 260: Timer / Counter I/O Registers

    VX800 / VX820 Series System Programming Manual I/O Ports Address: 21h Master Interrupt Mask Shadow Attribute Default Description Reserved T7-T3 of Interrupt Vector Address ― I/O Ports Address: A1h Slave Interrupt Mask Shadow Attribute Default Description Reserved T7-T3 of Interrupt Vector Address ―...

  • Page 261: Table 20. Cmos Register Summary

    VX800 / VX820 Series System Programming Manual I/O Ports Address: 74h CMOS Address Attribute Default Description CMOS Address (256 bytes of the CMOS memory) I/O Ports Address: 75h CMOS Data Attribute Default Description CMOS Data (256 bytes of the CMOS memory) Ports 74-75 may be accessed only if D17F0 Rx4E[3] (Port 74/75 Access Enable) is set to one to enable port 74/75 access.
  • Page 262 VX800 / VX820 Series System Programming Manual Description Offset Register Function Bit Description Register A Update In Progress 6:4: DV2-0 Divide (010=Enable oscillator & keep time) 3:0: RS3-0 Rate Select for Periodic Interrupt Register B Inhibit Update Transfers Periodic Interrupt Enable Alarm Interrupt Enable Update Ended Interrupt Enable SQWE No function (read/write bit)

  • Page 263: Keyboard / Mouse Wakeup Index / Data Registers

    VX800 / VX820 Series System Programming Manual Keyboard / Mouse Wakeup Index / Data Registers The Keyboard / Mouse Wakeup registers are accessed by performing I/O operations to / from an index / data pair of registers in system I/O space at port addresses 2Eh and 2Fh. The registers accessed using this mechanism are used to initialize Keyboard / Mouse Wakeup functions at index values in the range of E0-EFh.

  • Page 264: Keyboard / Mouse Wakeup Registers

    VX800 / VX820 Series System Programming Manual Keyboard / Mouse Wakeup Registers These registers are accessed via the port 2E / 2F index / data register pair with D17F0 Rx51[1] = 1 using the indicated index values below. Index: E0h Keyboard / Mouse Wakeup Enable Default Value: 08h Attribute...
  • Page 265 VX800 / VX820 Series System Programming Manual Index: E6h Keyboard Wakeup Scan Code Set 5 Default Value: 00h Attribute Default Description Keyboard Wakeup Sixth Reference Scan Code Index: E7h Keyboard Wakeup Scan Code Set 6 Default Value: 00h Attribute Default Description Keyboard Wakeup Seventh Reference Scan Code Index: E8h...

  • Page 266: Memory Mapped I/O Apic Registers

    VX800 / VX820 Series System Programming Manual Memory Mapped I/O APIC Registers The IO APIC registers are accessed by an indirect addressing scheme using Index Registers and Data Registers that are mapped into memory space. Memory Address: FEC00000h APIC Index Default Value: 0000 0000h Attribute Default...

  • Page 267: Indexed I/O Apic Registers

    VX800 / VX820 Series System Programming Manual Indexed I/O APIC Registers For index registers setting, please refer to Memory Address FEC00000h (APIC Index) and FEC00010 (APIC Data). Index: 00h I/O APIC Identification Default Value: 0000 0000h Attribute Default Description 31:28 Reserved 27:24 I/O APIC Identification...

  • Page 268: Table 21. I/O Redirection Table

    VX800 / VX820 Series System Programming Manual There are 24 64-bit I/O Redirection Table entry registers. Each register is a dedicated entry for each interrupt input signal. Table 21. I/O Redirection Table Index Function Mnemonic 11-10h I/O APIC Redirection – APIC IRQ0 IOREDTBL0 13-12h I/O APIC Redirection –...
  • Page 269 VX800 / VX820 Series System Programming Manual I/O Redirection Entry Default Value: nnn1 nnnn nnnn nnnnh Attribute Default Description 63:56 Destination Field In Physical Mode (bit-11=0), bits [59:56] contain an APIC ID. In Logical Mode (bit-11=1), bits [63:56] of the Destination Field specify the logical destination address. Destination Mode IOREDTBLx[11] Logical Destination Address 0: Physical Mode...

  • Page 270: Indexed I/O Uart Dma Control Registers

    VX800 / VX820 Series System Programming Manual Indexed I/O UART DMA Control Registers The base address is located at D17F0 RxB8[15:0] and through D17F0 RxB7[3] to enable or disable access. Index: 00h UART Port1 DMA Control Register 1 Default Value: 00h Attribute Default Description...
  • Page 271 VX800 / VX820 Series System Programming Manual Index: 02h UART Port2 DMA Control Register 1 Default Value: 00h Attribute Default Description Reserved Always reads 0. COM2 Transmit Using High Performance Way with DMA 0: Disable 1: Enable COM2 Receive Using High Performance Way with DMA 0: Disable 1: Enable Generate Interrupt for COM2 Transmit Complete...

  • Page 272: Device 12 Function 0 (D12F0) - Sdio Host Controller

    VX800 / VX820 Series System Programming Manual Device 12 Function 0 (D12F0) - SDIO Host Controller PCI Configuration Space Header (00-3Fh) Offset Address: 01-00h (D12F0) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h Vendor ID Offset Address: 03-02h (D12F0) Device ID Default Value: 95D0h Attribute...
  • Page 273 VX800 / VX820 Series System Programming Manual Offset Address: 08h (D12F0) Revision ID Default Value: 10h Attribute Default Description Revision ID Offset Address: 0B-09h (D12F0) Class Code Default Value: 08 0501h Attribute Default Description 23:0 080501h Class Code Offset Address: 0C-0Dh (D12F0) – Reserved Offset Address: 0Eh (D12F0) Header Type Default Value: 00h...

  • Page 274: Pci Device Specific Registers (40-Ffh)

    VX800 / VX820 Series System Programming Manual Offset Address: 2F-2Eh (D12F0) Subsystem ID Default Value: 95D0h Attribute Default Description 15:0 95D0h Subsystem ID Offset Address: 30-33h (D12F0) – Reserved Offset Address: 34h (D12F0) Capabilities Pointer Default Value: 80h Attribute Default Description Capabilities Pointer Point to the power management capability...
  • Page 275 VX800 / VX820 Series System Programming Manual Offset Address: 81-80h (D12F0) PCI Power Management Capabilities ID Default Value: 0001h Attribute Default Description 15:8 Point to the Next Capability Structure PCI Power Management Capability Offset Address: 83-82h (D12F0) PCI Power Management Capabilities Default Value: FFC2h Attribute Default...
  • Page 276 VX800 / VX820 Series System Programming Manual Offset Address: 8B-88h (D12F0) SDIO Host Capabilities Default Value: 0560 0181h Attribute Default Description 31:27 Reserved Voltage Support 1.8v 0: Not supported 1: Supported Reserved Voltage Support 3.3v 0: Not supported 1: Supported Suspend / Resume Support 0: Not supported 1: Supported...
  • Page 277 VX800 / VX820 Series System Programming Manual Offset Address: 8Dh (D12F0) SDIO Host Capabilities 1 Default Value: 00h Attribute Default Description Reserved Slot 2 Receiver Delay Clock Select 0: 2-clock period 1: 3-clock period Slot 1 Receiver Delay Clock Select This register is used to control how to generate read wait signal and stop clock.
  • Page 278 VX800 / VX820 Series System Programming Manual Offset Address: 99h (D12F0) SDIO Host Capabilities 4 Default Value: FCh Attribute Default Description Enable Dynamic Clock for PCI Configuration Clock 0: Disable 1: Enable Enable Dynamic Clock for North-South Module Interface Path Clock of Slot 1 0: Disable 1: Enable Enable Dynamic Clock for North-South Module Interface Path Clock of Slot 2...

  • Page 279: Sdio Host Standard Registers (00-Ffh)

    VX800 / VX820 Series System Programming Manual SDIO Host Standard Registers (00-FFh) This section describes memory mapped I/O registers. Please refer to SD Host Controller Standard Specification 1.0 for details. The following attributes are implemented specifically in the SDIO host standard registers. ROC: Read-only status.

  • Page 280: Table 22. Determination Of Transfer Type

    VX800 / VX820 Series System Programming Manual Offset Address: 0D-0Ch (SDIO-MMIO) Data Transfer Mode Default Value: 0000h Attribute Default Description 15:6 Reserved Multi / Single Block Select 0: Single Block 1: Multiple Block Data Transfer Direction Select 0: Write (Host to Card) 1: Read (Card to Host) Reserved Enable Auto CMD12...
  • Page 281 VX800 / VX820 Series System Programming Manual Offset Address: 23-20h (SDIO-MMIO) Buffer Data Port Default Value: 0000 0000h Attribute Default Description 31:0 Buffer Data The Host Controller buffer can be accessed through this 32-bit data port register. Offset Address: 27-24h (SDIO-MMIO) Present State Default Value: 01F2 0000h Attribute...
  • Page 282 VX800 / VX820 Series System Programming Manual Offset Address: 29h (SDIO-MMIO) Power Control Default Value: 0Eh Attribute Default Description Reserved 111b SD Bus Voltage Select 000-100: Reserved 101: 1.8V 110: 3.0V (not supported) 111: 3.3V SD Bus Power 0: Power off 1: Power on Offset Address: 2Ah (SDIO-MMIO) Block Gap Control...
  • Page 283 VX800 / VX820 Series System Programming Manual Offset Address: 2Eh (SDIO-MMIO) Timeout Control Default Value: 00h Attribute Default Description Reserved 0000b Data Timeout Counter Value 0000: TMCLK x 2 0001: TMCLK x 2 ………. 1110: TMCLK x 2 1111: Reserved Offset Address: 2Fh (SDIO-MMIO) Software Reset Default Value: 00h...
  • Page 284 VX800 / VX820 Series System Programming Manual Offset Address: 33-32h (SDIO-MMIO) Error Interrupt Status Default Value: 0000h Attribute Default Description 15:12 RW1C Vendor Specific Error Status 11:9 Reserved RW1C Auto CMD12 Error 0: No error 1: Error RW1C Current Limit Error 0: No error.
  • Page 285 VX800 / VX820 Series System Programming Manual Offset Address: 37-36h (SDIO-MMIO) Enable Error Interrupt Status Default Value: 0000h Attribute Default Description 15:12 Enable Vendor Specific Error Status 0: Mask 1: Enable 11:9 Reserved Enable Auto CMD12 Error Status 0: Mask 1: Enable Enable Current Limit Error Status 0: Mask...
  • Page 286 VX800 / VX820 Series System Programming Manual Offset Address: 3B-3Ah (SDIO-MMIO) Enable Error Interrupt Signal Default Value: 0000h Attribute Default Description 15:12 Enable Vendor Specific Error Signal 0: Mask 1: Enable 11:9 Reserved Enable Auto CMD12 Error Signal 0: Mask 1: Enable Enable Current Limit Error Signal 0: Mask...
  • Page 287 VX800 / VX820 Series System Programming Manual Offset Address: 47-40h (SDIO-MMIO) Capabilities Register Default Value: 0000 0000 0560 30B0h Attribute Default Description 63:32 Reserved 31:27 Reserved Reserved for voltage support. Voltage Support 1.8V 0: Not supported 1: Supported Voltage Support 3.0V 0: Not supported 1: Supported Voltage Support 3.3V...

  • Page 288: Irda Host Controller I/O Space Registers

    VX800 / VX820 Series System Programming Manual IrDA Host Controller I/O Space Registers These registers are located in the I/O address space at offsets from the “FIR I/O Address Base” located in D17F0 RxB6. I/O Offset: 10h (IrDA-IO) Infrared Mode Configuration - Low Default Value: 00h Attribute Default...
  • Page 289 VX800 / VX820 Series System Programming Manual I/O Offset: 12h (IrDA-IO) Infrared SIR BOF Default Value: C0h Attribute Default Description SIR Format Begin-of-Frame I/O Offset: 13h (IrDA-IO) Infrared SIR EOF Default Value: C1h Attribute Default Description SIR Format End of Frame I/O Offset: 14h (IrDA-IO) Infrared Status - High Default Value: 26h...

  • Page 290: Table 23. Programming Values For I/O Registers At Offset 16-19H

    VX800 / VX820 Series System Programming Manual I/O Offset: 18h (IrDA-IO) Infrared Packet Configuration - Low Default Value: 00h Attribute Default Description SIR / Indication Pulse Width [2:0] MIR Start / FIR Preamble Bytes to Send MIR: Number of start flags plus one (0 = 1 Byte) FIR: Number of preamble bytes plus one (0 = 1 Byte) I/O Offset: 19h (IrDA-IO) Infrared Packet Configuration - High...
  • Page 291 VX800 / VX820 Series System Programming Manual I/O Offset: 1Eh (IrDA-IO) Infrared Property Configuration Default Value: 00h Attribute Default Description FIR Adjustment Filter Rate 00: High filter 01: Medium high filter 10: Medium low filter 11: Low filter FIR Adjacent Pulse Width Packet Circuit 0: Enable 1: Disable FIR Pulse Width Adjustment Circuit...
  • Page 292 VX800 / VX820 Series System Programming Manual I/O Offset: 21h (IrDA-IO) IR Host Status Default Value: 00h Attribute Default Description Reserved Timer Interrupt Pending 0: Timer interrupt not pending 1: Timer interrupt pending Transmit Interrupt Pending 0: Timer interrupt not pending 1: Timer interrupt pending Receive Interrupt Pending 0: Timer interrupt not pending...
  • Page 293 VX800 / VX820 Series System Programming Manual I/O Offset: 23h (IrDA-IO) Transmit Control 1 Default Value: 00h Attribute Default Description Reserved Transmit FIFO Ready Interrupt 0: Disable 1: Enable interrupt when FIFO reaches threshold. See bit [4:3] for detail. Transmit FIFO Underrun/EOM Interrupt 0: Disable 1: Enable interrupt on underrun or EOM Transmit FIFO Threshold Level...
  • Page 294 VX800 / VX820 Series System Programming Manual I/O Offset: 25h (IrDA-IO) Transmit Status Default Value: 02h Attribute Default Description Reserved Transmit FIFO Underrun 1 indicates that the transmit FIFO ran out of data before the transmitter could finish transmitting all the data (i.e., transmit FIFO empty and a transmit byte count value greater than zero).
  • Page 295 VX800 / VX820 Series System Programming Manual I/O Offset: 27h (IrDA-IO) Receive Status Default Value: 02h Attribute Default Description PHY Error 1 indicates that the physical layer has detected an encoding error. This bit is automatically cleared upon detection of the ending / stop flag of the next incoming packet.
  • Page 296 VX800 / VX820 Series System Programming Manual I/O Offset: 29h (IrDA-IO) Packet Address Default Value: 00h Attribute Default Description Receive Packet Address Specifies the address value that must be contained in the address field of incoming packets. See also the “Receive Address Mode”...
  • Page 297 VX800 / VX820 Series System Programming Manual I/O Offset: 2Eh (IrDA-IO) Transmit Byte Count - Low Default Value: 00h Attribute Default Description Transmit Byte Count [7:0] Provides a running count of the number of bytes remaining to be transmitted. Before enabling transmission, software loads this register with the low-order byte length of the data packet.
  • Page 298 VX800 / VX820 Series System Programming Manual I/O Offset: 34h (IrDA-IO) Infrared Transceiver Control - Low Default Value: 00h Attribute Default Description Reserved GFX GPIO Data for I/O Function When read: The data is directly from IRSCLK pad. When write: The data is directly to IRSCLK pad.

  • Page 299: Device 13 Function 0 (D13F0) - Secure Digital Memory Card Controller

    VX800 / VX820 Series System Programming Manual Device 13 Function 0 (D13F0) – Secure Digital Memory Card Controller PCI Configuration Space Header (00-3Fh) Offset Address: 01-00h (D13F0) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technology ID Code Offset Address: 03-02h (D13F0) Device ID Default Value: 9530h...
  • Page 300 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D13F0) PCI Status Default Value: 0210h Attribute Default Description Reserved Signaled System Error (SERR# asserted) RW1C Received Master-Abort (except special cycle) 0: No abort received 1: Transaction aborted by the Master RW1C Received Target-Abort 0: No abort received...
  • Page 301 VX800 / VX820 Series System Programming Manual Offset Address: 0Fh (D13F0) Built In Self Test (BIST) Default Value: 00h Attribute Default Description BIST (Build In Self Test) Fixed at 0. Offset Address: 13-10h (D13F0) Card Reader (CR) MMIO Register Base Address Default Value: 0000 0000h Attribute Default...
  • Page 302 VX800 / VX820 Series System Programming Manual Offset Address: 3Ch (D13F0) Interrupt Line Default Value: 00h Attribute Default Description Reserved 0000b Interrupt Line Selection 0000: Disable 0001: IRQ1 0010: Reserve 0011: IRQ3 0100: IRQ4 0101: IRQ5 0110: IRQ6 0111: IRQ7 1000: Disable 1001: IRQ9 1010: IRQ10...

  • Page 303: Pci Card Reader - Specific Configuration Registers (40-Ffh)

    VX800 / VX820 Series System Programming Manual PCI Card Reader - Specific Configuration Registers (40-FFh) Offset Address: 40h (D13F0) Card Reader Working Mode Selection Default Value: 00h Attribute Default Description Reserved Scatter-Gather Mode Select 0: PIO mode 1:Scatter-Gather DMA mode Offset Address: 41h (D13F0) Debug Mode Control Default Value: 00h...
  • Page 304 VX800 / VX820 Series System Programming Manual Offset Address: 83-82h (D13F0) Power Management Capability Default Value: FFC2h Attribute Default Description 15:11 PME# Support This 5-bit field indicates the power states in which the function may assert PME#. A value of 0b for any bit indicates that the function is not capable of asserting the PME# signal while in that power state.

  • Page 305: Sdc Mmio Registers (00-Ffh)

    VX800 / VX820 Series System Programming Manual PCI CardReader-Specific MMIO Registers Offset Range 200h~~2FFh 400h~~4FFh Data DMA 500h~~5FFh CICH DMA 600h~~6FFh PCI Control SDC MMIO Registers (00-FFh) Offset Address: 00h (SDC-MMIO) Control Register Default Value: 00h Attribute Default Description Command Type Refer to the Command Type Field Encoding table below for valid encoding and descriptions.

  • Page 306: Table 24. Command Type Field Encodings

    VX800 / VX820 Series System Programming Manual Table 24. Command Type Field Encodings Command Action applied to SD Memory Action applied to SDIO Type[3:0] 0000b Non-data-write, non-data-read, non-data-stop, non-io-abort Non-data-write, non-data-read, non-data-stop, non-io-abort commands. commands. 0001b Single block write. Use when doing a WRITE_BLOCK (CMD24) Single block IO write.
  • Page 307 VX800 / VX820 Series System Programming Manual Command Action applied to SD Memory Action applied to SDIO Type[3:0] 0100b Multiple block read requires STOP command to end Multiple block IO read requires writing to CCCR to end transfer. transfer. Use when doing a READ_MULTIPLE_BLOCK Use when doing an IO_RW_EXTENDED (CMD53) with fields R/ (CMD18) command.
  • Page 308 VX800 / VX820 Series System Programming Manual Offset Address: 01h (SDC-MMIO) Command Index Default Value: 00h Attribute Default Description Command Index Bits[13:8] will be the contents of bits[45:40] in SD command token. Offset Address: 02h (SDC-MMIO) Response Type Default Value: 00h Attribute Default Description...
  • Page 309 VX800 / VX820 Series System Programming Manual Offset Address: 0D-0Ch (SDC-MMIO) Block Length Default Value: 0000h Attribute Default Description Enable SD Host Interrupt 0: Disable 1: Enable 14:13 Reserved Active Polarity of Card Detection Pin 0: Indicates the card insertion is active low. Low means the existence of memory card. 1: Indicates the card insertion is active high Enable Transaction Abort When Multiple Blocks R/W Command CRC Error Occurs 0: Disable...
  • Page 310 VX800 / VX820 Series System Programming Manual Offset Address: 24h (SDC-MMIO) Interrupt Mask 1 Default Value: 00h Attribute Default Description Reserved Enable Interrupt for Block Data Transfer Done Generate an interrupt at the completion of each block of data transfer. 0: Disable 1: Enable Enable Interrupt for Multiple Blocks Transfer Done...
  • Page 311 VX800 / VX820 Series System Programming Manual Offset Address: 28h (SDC-MMIO) SD Status 1 Default Value: 00h Attribute Default Description RW1C Card Detect Interrupt by GPI Pin Card insertion or removal interrupt, using CRSD_CD# as card detection pin. 0: No interrupt 1: Card insertion or removal interrupt is detected Reserved RW1C...
  • Page 312 VX800 / VX820 Series System Programming Manual Offset Address: 2Ah (SDC-MMIO) SD Status 3 Default Value: 00h Attribute Default Description SD Host Automatic Clock Freezing Enable 0: Disable. Card always transfers data without stopping clock. 1: Enable. When DMA can not transfer data, controller can stop the clock of card in order to block the card data. It is highly recommended to set this bit always.

  • Page 313: Data Dma Control Registers (00-Ffh)

    VX800 / VX820 Series System Programming Manual Data DMA Control Registers (00-FFh) Offset Address: 03-00h (Data DMA-MMIO) Data DMA Base Address Default Value: 0000 0000h Attribute Default Description 31:0 Data DMA Base Address When Write: Base Address for Data DMA. When Read: Current memory address will be read or write if DMA is busy or Base Address for Data DMA if DMA is idle.
  • Page 314 VX800 / VX820 Series System Programming Manual Offset Address: 0F-0Ch (Data DMA-MMIO) Data DMA Status 1 Default Value: 0000 0000h Attribute Default Description 31:17 Reserved RW1C IRQ Status IRQ will assert when this bit is set and IRQ is enabled. 15:0 Reserved Offset Address: 13-10h (Data DMA-MMIO)

  • Page 315: Cich Dma Control Registers (00-Ffh)

    VX800 / VX820 Series System Programming Manual CICH DMA Control Registers (00-FFh) Offset Address: 03-00h (CICH DMA-MMIO) Scatter-Gather Base Address Default Value: 0000 0000h Attribute Default Description 31:2 Scatter-Gather Descriptor Base Address The starting address of the first descriptor in the Scatter-Gather descriptor list. Reserved Offset Address: 07-04h (CICH DMA-MMIO) Control Register...
  • Page 316 VX800 / VX820 Series System Programming Manual Offset Address: 0F-0Ch (CICH DMA-MMIO) Status Register Default Value: 0000 0000h Attribute Default Description 31:22 Reserved 21:20 Descriptor Engine Status 00: Idle. Engine is not executing any descriptor. 01: Busy. Engine is fetching or executing descriptor. 10: Wait.
  • Page 317 VX800 / VX820 Series System Programming Manual Offset Address: 13-10h (CICH DMA-MMIO) Engine Setting Default Value: 0000 0000h Attribute Default Description 31:18 Reserved 17:16 Wait for Controller Interrupt Time Out Counter 00: Never time out 01: Time out after 1 us 10: Time out after 1 ms 11: Time out after 1024 ms 15:11...

  • Page 318: Pci Control Registers (00-Ffh)

    VX800 / VX820 Series System Programming Manual PCI Control Registers (00-FFh) Offset Address: 00-01h (PCI Control-MMIO) – Reserved Offset Address: 02h (PCI Control-MMIO) Clock Gating Control Default Value: 01h Attribute Default Description Reserved SD Output Clock Select Mode 0x: Use card detection to select 10: Dedicated for SD 11: Reserved Enable Clock Gating...
  • Page 319 VX800 / VX820 Series System Programming Manual Offset Address: 08h (PCI Control-MMIO) Interrupt Control Default Value: 00h Attribute Default Description Reserved Enable CICH Interrupt 0: Disable 1: Enable Enable DMA Interrupt 0: Disable 1: Enable Reserved Enable SDC Interrupt 0: Disable 1: Enable Reserved Offset Address: 09h (PCI Control-MMIO)

  • Page 320: Device 15 Function 0 (D15F0): Serial Ata & Eide Controller

    VX800 / VX820 Series System Programming Manual Device 15 Function 0 (D15F0): Serial ATA & EIDE Controller * VX820 Series do not support Serial ATA. Device 15 Function 0 integrates one EIDE controller and two SATA ports. Please refer to the following table for the IDE/SATA mode configuration.
  • Page 321 VX800 / VX820 Series System Programming Manual Offset Address: 05-04h (D15F0) PCI Command Default Value: 0000h Attribute Default Description 15:11 Reserved Interrupt Disable Reserved Parity Error Response VGA Palette Snooping Reserved Memory Write and Invalidate Respond to Special Cycle Bus Master Memory Space Access I/O Space Access When the “I/O Space”...
  • Page 322 VX800 / VX820 Series System Programming Manual Offset Address: 08h (D15F0) Revision ID Default Value: nnh Attribute Default Description Revision ID Offset Address: 09h (D15F0) Programming Interface Default Value: 8Ah If Rx0A = 04h, this register will be read as configuration RAID while if Rx0A = 01h, this register will be read as Configuration IDE. Attribute Default Description...
  • Page 323 VX800 / VX820 Series System Programming Manual Offset Address: 0Dh (D15F0) Latency Timer Default Value: 20h Attribute Default Description Latency Timer Fixed at 0. Offset Address: 0Eh (D15F0) Header Type Default Value: 00h Attribute Default Description Multiple Function Device Fixed at 0. Offset Address: 0Fh (D15F0) –...
  • Page 324 VX800 / VX820 Series System Programming Manual Offset Address: 1B-18h (D15F0) PATA (Secondary Channel) Data / Command Base Address Default Value: 0000 0000h Specifies an 8-bytes I/O address space. Attribute Default Description Configuration IDE Class (if Rx0A = 01h) and Compatible Mode (if Rx09[2] = 0) 31:16 Reserved (Must set to 0)
  • Page 325 VX800 / VX820 Series System Programming Manual Offset Address: 2D-2Ch (D15F0) Subsystem Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h Subsystem Vendor ID The read back value can be changed by writing to RxBC-BD. Offset Address: 2F-2Eh (D15F0) Subsystem ID Default Value: 5324h Attribute...

  • Page 326: Sata Registers (40-47H)

    VX800 / VX820 Series System Programming Manual SATA Registers (40-47h) Offset Address: 40h (D15F0) SATA Channel Enable Default Value: 03h Attribute Default Description Reserved SATA Downstream IO and Configuration Cycles Control 0: SATA downstream IO cycles are blocked, i.e. SATA will not serve ATA commands. SATA downstream configuration cycles work as normal.
  • Page 327 VX800 / VX820 Series System Programming Manual Offset Address: 44h (D15F0) Miscellaneous Control 1 Default Value: 87h Attribute Default Description Disable SATA 66MHz Data Path Dynamic Clock Gating 0: Enable 1: Disable Reserved Wait Until PHY Ready if Device Has Been Detected When Executing SW Reset 0: Jump the ports that PHY is not ready 1: Wait until PHY ready Bus Master IDE Status Register Read Retry...

  • Page 328: Eide Registers (48-54H)

    VX800 / VX820 Series System Programming Manual EIDE Registers (48-54h) Offset Address: 49-48h (D15F0) EIDE (Secondary Channel) PIO & Multi-Word DMA Timing Control Default Value: A8A8h The following waveform defines the Active Pulse Width and Recovery Time for the EIDE PDIOR# and PDIOW# signals when accessing the data ports (170h): The actual pulse width is the encoded value in the field plus one in unit of PCI clocks.
  • Page 329 VX800 / VX820 Series System Programming Manual Offset Address: 50h (D15F0) EIDE (Secondary Channel) Slave Ultra DMA Mode Control Default Value: 07h Attribute Default Description Way to Enable UltraDMA Mode for Slave Device 0: Enabled by the Set Feature (EFh) command 1: UltraDMA On/Off is decided by the setting of Rx50[6] Ultra DMA Mode Enable 0: Disable...

  • Page 330: Sata Link Control Registers (55-56H)

    VX800 / VX820 Series System Programming Manual SATA Link Control Registers (55-56h) Offset Address: 55h (D15F0) SATA Control Register 1 Default Value: 9Ch Attribute Default Description Host Transmit COMRESET and Keep 6 Bursts for Power-on Sequence 0: Disable 1: Enable Asynchronous Recovery Stop When Asynchronous Recovery Five Times 0: Disable 1:Enable...

  • Page 331: Sata Phy Control Registers (57-5Eh)

    VX800 / VX820 Series System Programming Manual SATA PHY Control Registers (57-5Eh) Offset Address: 57h (D15F0) PHY Test Mode Control 1 Default Value: 30h Attribute Default Description Reserved Enable SATA AFE Output Signal Gating 0: Disable 1: Enable Enable SATA PLL Turn Off When C4P State 0: Disable 1: Enable Note: C4P state means “special power state for VIA CPU.
  • Page 332 VX800 / VX820 Series System Programming Manual Offset Address: 5Ch (D15F0) PHY Control Register 1 Default Value: 00h Attribute Default Description Bypass Oscillator FTMODE 0: Normal mode 1: FT mode SATA PHY Dynamic Clock Gating 0: Enable 1: Disable Double (6 to 12) OOB Burst Number 0: No (6) 1: Yes (12) SATA PHY 150MHz Dynamic Clock Gating...

  • Page 333: Sata Hot Plug And Rambist Status Registers (5F-63H)

    VX800 / VX820 Series System Programming Manual SATA Hot Plug and RAMBIST Status Registers (5F-63h) Offset Address: 5Fh (D15F0) SATA Hot Plug Status Default Value: 00h Attribute Default Description Reserved RW1C Primary Channel (SATA Port 1) Slave Plug Out Status RW1C Primary Channel (SATA Port 1) Slave Plug In Status RW1C...

  • Page 334: Sata Analog Phy Control (64-77H)

    VX800 / VX820 Series System Programming Manual SATA Analog PHY Control (64-77h) Offset Address: 64h (D15F0) Analog PHY Control Register 1 Default Value: 35h Attribute Default Description When CDR Disperses, Re-assign Phase-mode and CDR Reset Signals 0: Disable 1: Enable CDR Bandwidth Select Bit [1:0] 0: Disable 1: Enable...
  • Page 335 VX800 / VX820 Series System Programming Manual Offset Address: 69h (D15F0) Analog PHY Control Register 5 Default Value: 00h Attribute Default Description Port 0 Supports External Interconnect (For Box-to-Box / Long-Haul - Gen1x or Gen2x Support) 0:Disable 1: Enable Select CDR Regulator Reset Source 0: PCI Reset 1: Driver Reset Reserved...
  • Page 336 VX800 / VX820 Series System Programming Manual Offset Address: 6Ch (D15F0) Analog PHY Control Register 8 Default Value: 44h Attribute Default Description Duty-Balance Control: Rising Time for Serial Data Port 0 Bit [1:0] Duty-Balance Control: Falling Time for Serial Data Port 0 Bit [1:0] Duty-Balance Control: Rising Time for Serial Data Port 1 Bit [1:0] Duty-Balance Control: Falling Time for Serial Data Port 1 Bit [1:0] Note:...
  • Page 337 VX800 / VX820 Series System Programming Manual Offset Address: 74h (D15F0) Analog PHY Control Register 11 Default Value: FFh Attribute Default Description Latch Up Test Pin Status for Port 0 Tx PAD [1:0] 0: Disable 1: Enable Latch Up Test Pin Status for Port 0 Rx PAD [1:0] 0: Disable 1: Enable Latch Up Test Pin Status for Port 1 Tx PAD [1:0]...
  • Page 338 VX800 / VX820 Series System Programming Manual Offset Address: 77h (D15F0) Analog PHY Control Register 13 Default Value: 44h Attribute Default Description Port 0 Driver Current Source Bit [3:0] – Gen2 0000: TX output current 10mA 0001: TX output current 10.5mA 0010: TX output current 11.2mA 0011: TX output current 11.8mA 0100: TX output current 12.4mA...

  • Page 339: Miscellaneous Registers (78-7Fh)

    VX800 / VX820 Series System Programming Manual Miscellaneous Registers (78-7Fh) Offset Address: 78h (D15F0) SATA (Primary Channel) Transport Status 1 Default Value: 01h Attribute Default Description Reserved DMA Read Device Cycle Active 0: Inactive 1: Active DMA Write Device Cycle Active 0: Inactive 1: Active SG Operation Active...

  • Page 340: Sata Transport Control Registers (80-8Fh)

    VX800 / VX820 Series System Programming Manual SATA Transport Control Registers (80-8Fh) Offset Address: 80h (D15F0) SATA PHY Power Management Mode – Software Request Default Value: 00h Attribute Default Description Reserved Request for Slumber Mode on Internal PHY Port 1 0: Disable 1: Enable Request for Partial Slumber Mode on Internal PHY Port 1...
  • Page 341 VX800 / VX820 Series System Programming Manual Offset Address: 82h (D15F0) Transport Miscellaneous Control Default Value: 00h Attribute Default Description Reserved Transport Issue Early Request to Link 0: Disable 1: Enable Reserved Single Data FIS Transmission Size 0: Maximum size: 8K bytes 1: Allow over 8K bytes.

  • Page 342: Sata Scr Registers (A0-Afh)

    VX800 / VX820 Series System Programming Manual SATA SCR Registers (A0-AFh) Offset Address: A0h (D15F0) Primary Channel Master Device Status (SStatus) Default Value: 00h Attribute Default Description Reserved SATA Gen 2 (3Gb) Status Slumber Mode Power Management Status When read 1, it indicates that the device and the controller are currently in Slumber mode. 0: Not in slumber mode 1: Slumber mode Partial Mode Power Management Status...
  • Page 343 VX800 / VX820 Series System Programming Manual Offset Address: A5h (D15F0) SATA (Primary Channel) Slave Device Control (SControl) Default Value: 0Ch Attribute Default Description Reserved Transition to Slumber Power State 0: Enable 1: Disable Transition to Partial Power State 0: Enable 1: Disable SATA Interface and Put PHY In Offline Mode 0: Enable...

  • Page 344: Legacy / Back Door Registers (B0-Bfh)

    VX800 / VX820 Series System Programming Manual Legacy / Back Door Registers (B0-BFh) Offset Address: B1-B0h (D15F0) Power Management Capability ID Default Value: 0001h Attribute Default Description 15:8 Fixed at 0 Capability ID A PCI power management capability pointer. Offset Address: B3-B2h (D15F0) Power Management Interface Revision Default Value: 0002h Attribute...
  • Page 345 VX800 / VX820 Series System Programming Manual Offset Address: BB-BAh (D15F0) Device ID (IDE) Back Door Default Value: 5324h Attribute Default Description 15:0 5324h Device ID Back Door Merge Device ID back door for RAID mode and Device ID back door for IDE mode. These are backdoor registers of Rx03-02, and writing RxBB-BA can change the Device ID value.

  • Page 346: Eide Registers (C0-Ffh)

    VX800 / VX820 Series System Programming Manual EIDE Registers (C0-FFh) Offset Address: C0h (D15F0) EIDE Control Default Value: 08h Attribute Default Description Chip ID 100b Reserved (Do not program) EIDE (Secondary Channel) Enable 0: Disable 1: Enable Please refer to the IDE/SATA Support Option table for details. Offset Address: C1h (D15F0) EIDE Configuration Default Value: 02h...
  • Page 347 VX800 / VX820 Series System Programming Manual Offset Address: C4h (D15F0) EIDE Configuration 1 Default Value: 08h Attribute Default Description Reserved EIDE PIO Read Pre-Fetch Byte Counter 0: Disable. Pre-fetch will continue when FIFO has vacancy. 1: Enable. The pre-fetch byte count is determined by RxE9-E8[11:0] for EIDE PIO Read. Bus Master IDE Status Register Read Retry Determines whether a read to the bus master IDE status register is retried when DMA operation is not complete.
  • Page 348 VX800 / VX820 Series System Programming Manual Offset Address: D4h (D15F0) EIDE Configuration 3 Default Value: 0Ch Attribute Default Description IRQ15 Usage when IDE Channel is Disabled 0: Release IRQ15 for system usage when IDE Channel is disable (–i.e. RxC0[0] is cleared) 1: IRQ15 is reserved.
  • Page 349 VX800 / VX820 Series System Programming Manual Offset Address: F2h (D15F0) EIDE FIFO Threshold Control Default Value: 01h Attribute Default Description Reserved Two FIFO Thresholds 0: Disable (Use one threshold, defined in RxC3[1:0], for both direction of data transfer between Device and Memory) 1: Enable (Memory-to-Device and Device-to-Memory use RxF2[1:0] and RxC3[1:0] settings, respectively as threshold settings)

  • Page 350: Device 16 Function 0-2 (D16F0-F2) - Usb 1.1 Uhci Ports 0-5

    VX800 / VX820 Series System Programming Manual Device 16 Function 0-2 (D16F0-F2) – USB 1.1 UHCI Ports 0-5 This Universal Serial Bus host controller interface is fully compatible with UHCI specification v1.1. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the Device 16 Function 0-2 PCI configuration space of the chip.
  • Page 351 VX800 / VX820 Series System Programming Manual Offset Address: 0B-09h (D16F0-F2) Class Code Default Value: 0C 0300h Attribute Default Description 23:0 0C0300h Class Code To indicate the USB1.1 Host Controller. Offset Address: 0Ch (D16F0-F2) Cache Line Size Default Value: 00h Attribute Default Description...
  • Page 352 VX800 / VX820 Series System Programming Manual Offset Address: 2F-2Eh (D16F0-F2) Subsystem ID Default Value: 3038h Attribute Default Description 15:0 3038h Subsystem ID Offset Address: 30-33h (D16F0-F2) – Reserved Offset Address: 34h (D16F0-F2) Power Management Capabilities Default Value: 80h Attribute Default Description Power Management Capabilities...

  • Page 353: Usb 1.1-Specific Configuration Registers (40-Ffh)

    VX800 / VX820 Series System Programming Manual USB 1.1-Specific Configuration Registers (40-FFh) Offset Address: 40h (D16F0-F2) Control Register 1 Default Value: 40h Attribute Default Description Reserved Babble Option This bit controls whether the port is disabled when EOF (End-Of-Frame) babble occurs. Babble is unexpected bus activity that persists into the EOF interval.
  • Page 354 VX800 / VX820 Series System Programming Manual Offset Address: 42h (D16F0-F2) Control Register 3 Default Value: 03h Attribute Default Description Reserved Hold Data Transmission till FIFO Reaches Transmission Threshold 0: Enable 1: Disable Reserved (Do not program) Offset Address: 43h (D16F0-F2) Control Register 4 Default Value: 00h Attribute...
  • Page 355 VX800 / VX820 Series System Programming Manual Offset Address: 4Ah (D16F0-F2) Control Register 7 Default Value: A0h Attribute Default Description USB 1.1 Bus Timeout Parameter Reserved Use External 60 MHz Clock Set this bit to use external 60 MHz input clock. 0: Disable 1: Enable Offset Address: 4Bh (D16F0-F2)
  • Page 356 VX800 / VX820 Series System Programming Manual Offset Address: C1-C0h (D16F0-F2) Legacy Support (for UHCI v1.1 Compliant) Default Value: 2000h Attribute Default Description RW1C End of A20Gate Pass Through Status (A20PTS) 1 to indicate A20Gate pass through sequence has ended. Reserved Fixed to 0.

  • Page 357: Usb 1.1 I/O Registers (00-13H)

    VX800 / VX820 Series System Programming Manual USB 1.1 I/O Registers (00-13h) These registers are compliant with the UHCI v1.1 standard. Refer to the UHCI v1.1 specification for further details. I/O Offset Address: 01-00h (USB 1.1-IO) USB Command Default Value: 0000h Attribute Default Description...

  • Page 358: Device 16 Function 4 Registers - Usb 2.0 Ehci

    VX800 / VX820 Series System Programming Manual Device 16 Function 4 Registers - USB 2.0 EHCI This Enhanced Serial Bus host controller interface is fully compatible with EHCI specification v1.0. There are two sets of software accessible registers: PCI configuration registers and USB I/O registers. The PCI configuration registers are located in the Bus 0 Device 16 Function 4 PCI configuration space of the chip.
  • Page 359 VX800 / VX820 Series System Programming Manual Offset Address: 08h (D16F4) Revision ID Default Value: nnh Attribute Default Description Revision ID Offset Address: 0B-09h (D16F4) Class Code Default Value: 0C 0320h Attribute Default Description 23:0 0C0320h Class Code for USB2.0 EHCI Host Controller Offset Address: 0Ch (D16F4) Cache Line Size Default Value: 00h...
  • Page 360 VX800 / VX820 Series System Programming Manual Offset Address: 2D-2Ch (D16F4) Subsystem Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h Subsystem Vendor ID Offset Address: 2F-2Eh (D16F4) Subsystem ID Default Value: 3104h Attribute Default Description 15:0 3104h Subsystem ID Offset Address: 30-33h (D16F4) –...

  • Page 361: Usb 2.0-Specific Configuration Registers (40-Fch)

    VX800 / VX820 Series System Programming Manual USB 2.0-Specific Configuration Registers (40-FCh) Offset Address: 40h (D16F4) Control Register 1 Default Value: 00h Attribute Default Description Reserved Babble Option This bit controls whether the port is disabled when EOF (End-Of-Frame) babble occurs. Babble is unexpected bus activity that persists into the EOF interval.
  • Page 362 VX800 / VX820 Series System Programming Manual Offset Address: 48h (D16F4) Control Register 3 Default Value: BEh Attribute Default Description USB 2.0 EOP Pattern (FEh) Error Check 0: Disable 1: Enable Extra-Handshake Error Checking in Isochronous Transaction 0: Disable 1: Enable CCA Burst Access 0: Burst Enable 1: Burst Disable...
  • Page 363 VX800 / VX820 Series System Programming Manual Offset Address: 4Ch (D16F4) PHY Control 1 Default Value: 12h Attribute Default Description Resume ACK Control 0: 20ms resume, then send ACK to C4P state resume request 1: Quickly send ACK to C4P state resume request Reserved USB1.0 UTM Tx Speed Up 0: Disable...
  • Page 364 VX800 / VX820 Series System Programming Manual Offset Address: 50h (D16F4) USB 2.0 Doorbell Bit Function Default Value: 00h Attribute Default Description Fetch One More QH Before De-asserting Doorbell Bit 0: Disable 1: Enable Reserved Offset Address: 51h (D16F4) USB 2.0 MAC Timeout Parameter Default Value: 60h Attribute Default...
  • Page 365 VX800 / VX820 Series System Programming Manual Offset Address: 59h (D16F4) PHY Control 3 Default Value: 0Bh Attribute Default Description Disable PHY Auto Power-Down Feature When set this bit, if port is suspended or is not EHCI owned, the port will auto power-down. 0: Auto power-down 1: Disable Auto power-down Transit POwner Control...
  • Page 366 VX800 / VX820 Series System Programming Manual Offset Address: 63-62h (D16F4) Port Wake Capability Default Value: 0001h Attribute Default Description 15:7 Reserved Port Wake Capability Port Wake Capability Offset Address: 64-67h (D16F4) – Reserved Offset Address: 6B-68h (D16F4) USB Legacy Support Extended Capability Default Value: 0000 0001h Attribute Default...
  • Page 367 VX800 / VX820 Series System Programming Manual Offset Address: 83-82h (D16F4) Power Management Capability Default Value: FFC2h Attribute Default Description 31:0 FFC2h Power Management Capability If D16F0-F2 Rx49[1]= 1, this register is fixed at FFC2h. If D16F0-F2 Rx49[1]= 0, this register is fixed at 7E0Ah. Offset Address: 85-84h (D16F4) Power Management Capability Control / Status Default Value: 0000h...

  • Page 368: Ehci Usb 2.0 I/O Registers (00-B3H)

    VX800 / VX820 Series System Programming Manual EHCI USB 2.0 I/O Registers (00-B3h) These registers are compliant with the EHCI v1.0 standard. Refer to the EHCI v1.0 specification for further details. EHCI Capabilities (00-0Bh) I/O Offset Address: 00h (USB 2.0-IO) Capability Register Length Default Value: 10h Attribute...
  • Page 369 VX800 / VX820 Series System Programming Manual Host Controller Operations (10-9Fh) I/O Offset Address: 13-10h (USB 2.0-IO) USB Command Default Value: 0008 0000h Attribute Default Description 31:0 0008 0000h USB Command I/O Offset Address: 17-14h (USB 2.0-IO) USB Status Default Value: 0000 1000h Attribute Default Description...
  • Page 370 VX800 / VX820 Series System Programming Manual I/O Offset Address: 57-54h (USB 2.0-IO) Port 1 Status / Control Default Value: 0000 3000h Attribute Default Description 31:0 RW1C 0000 3000h Port 1 Status / Control I/O Offset Address: 5B-58h (USB 2.0-IO) Port 2 Status / Control Default Value: 0000 3000h Attribute...
  • Page 371 VX800 / VX820 Series System Programming Manual Debug Port Controller Operational Registers (A0-B3h) I/O Offset Address: A3-A0h (USB 2.0-IO) Debug Port Control / Status Default Value: 0000 0000h Attribute Default Description 31:0 RW/RO 0000 0000h Debug Port Control / Status /RW1C I/O Offset Address: A7-A4h (USB 2.0-IO) Debug Port USB PIDs...

  • Page 372: Device 17 Function 0 (D17F0) - Bus Control And Power Management

    VX800 / VX820 Series System Programming Manual Device 17 Function 0 (D17F0) - Bus Control and Power Management All registers are located in the device 17 function 0 configuration space of VX800 / VX820 Series. These registers are accessed through PCI configuration mechanism #1 via I/O address 0CF8h / 0CFCh. PCI Configuration Space Header (00-3Fh) Offset Address: 01-00h (D17F0) Vendor ID...
  • Page 373 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D17F0) PCI Status Default Value: 0210h Attribute Default Description Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase Signaled System Error (SERR# asserted) Received Master-Abort (except special cycle) 0: No abort received 1: Transaction aborted by the Master...

  • Page 374: Isa Bus Control (40-49H)

    VX800 / VX820 Series System Programming Manual Offset Address: 0Fh (D17F0) BIST Default Value: 00h Attribute Default Description BIST (Built In Self Test) Fixed at 00h. Offset Address: 10-2Bh (D17F0) – Reserved Offset Address: 2D-2Ch (D17F0) Subsystem Vendor ID Default Value: 0000h Attribute Default Description...
  • Page 375 VX800 / VX820 Series System Programming Manual Offset Address: 41h (D17F0) ROM Decode Control Default Value: 80h Setting these bits to 1 enables the indicated address range to be included in the LPC BIOS ROM address decode: Attribute Default Description 000E0000h-000EFFFFh FFF00000h-FFF7FFFFh FFB00000h-FFB7FFFFh...
  • Page 376 VX800 / VX820 Series System Programming Manual Offset Address: 43h (D17F0) Delay Transaction Control Default Value: 00h Attribute Default Description Reserved Delayed Transactions (PCI Spec Rev 2.1) This bit controls whether delayed transactions (delayed read / write and posted write) are enabled. 0: Disable 1: Enable Delayed Transaction –...
  • Page 377 VX800 / VX820 Series System Programming Manual Offset Address: 47h (D17F0) PATA PAD Control Default Value: 03h Attribute Default Description 0000b SPI IRQ Routing 0000: IRQ0 0001: IRQ1 … … 1111: IRQ15 IDE Pad Mux Select 00: The pads mux is determined by strapping value (registers default value). 01: The IDE pads are dedicated to IDE (no matter what strapping values are).

  • Page 378: Lpc Firmware Memory Control (4A-4Bh)

    VX800 / VX820 Series System Programming Manual Offset Address: 49h (D17F0) SM Peripheral Device Control Default Value: 20h Attribute Default Description SERR from Host Directed to PMU (SMI, SCI) 0: Disable 1: Enable Reserved Gated IRQ before SM Buffer Clean Controls whether interrupt requests are gated until data is written to memory.
  • Page 379 VX800 / VX820 Series System Programming Manual Offset Address: 4Dh (D17F0) Miscellaneous Control Default Value: 00h Attribute Default Description LPC Firmware Memory 16 Bytes Burst Read 0: Disable 1: Enable LPC Firmware Memory 4 Bytes Burst Read / Write Access 0: Disable 1: Enable Firmware Memory Burst Detection...

  • Page 380: Function Control (50-51H)

    VX800 / VX820 Series System Programming Manual Offset Address: 4Fh (D17F0) PCI Reset Control Default Value: 00h Attribute Default Description Reserved Software PCI Reset Write 1 to generate PCI reset 0: Disable 1: Enable Software reset can also be initiated through I/O port CF9 as follows: Write 1 to I/O port CF9 bit-2 for software reset: if CF9 bit-1 is 0, INIT will be asserted;...

  • Page 381: Serial Irq, Lpc And Pc / Pci Dma Control (52-53H)

    VX800 / VX820 Series System Programming Manual Serial IRQ, LPC and PC / PCI DMA Control (52-53h) Offset Address: 52h (D17F0) Serial IRQ, PCI / DMA Control and LPC Control Default Value: 00h Attribute Default Description Reserved LPC Short Wait Abort 0: Disable 1: Enable.

  • Page 382: Plug And Play Control - Pci (54-57H)

    VX800 / VX820 Series System Programming Manual Plug and Play Control – PCI (54-57h) Offset Address: 54h (D17F0) PCI Bus and CPU Interface Control Default Value: 00h Attribute Default Description Reserved The following bits all default to “Low Active Level ” triggered (0) Enable External Debug Card by SDIO Pad 0: Disable 1: Enable...

  • Page 383: Table 26. Pnp Irq Routing Table

    VX800 / VX820 Series System Programming Manual Table 26. PnP IRQ Routing Table Bit Value IRQ-N 0000 Reserved 0001 IRQ1 0010 Reserved 0011 IRQ3 0100 IRQ4 0101 IRQ5 0110 IRQ6 0111 IRQ7 1000 Reserved 1001 IRQ9 1010 IRQ10 1011 IRQ11 1100 IRQ12 1101...

  • Page 384: Gpio And Miscellaneous Control (58-5Bh)

    VX800 / VX820 Series System Programming Manual GPIO and Miscellaneous Control (58-5Bh) Offset Address: 58h (D17F0) South Module Miscellaneous Control 1 Default Value: 20h Attribute Default Description Reserved Internal APIC 0: Disable 1: Enable South Module Interrupt Cycles are Sync. by 33 MHz Clock 0: Disable (8MHz) 1: Enable South Module PCI Cycle Decode...
  • Page 385 VX800 / VX820 Series System Programming Manual Offset Address: 5Ah (D17F0) DMA Bandwidth Control Default Value: 00h Attribute Default Description DMA Channel 7 Bandwidth 0: Normal 1: Improved DMA Channel 6 Bandwidth 0: Normal 1: Improved DMA Channel 5 Bandwidth 0: Normal 1: Improved DMA Single Transfer Mode Bandwidth...

  • Page 386: Programmable Chip Select (Pcs) Control (5C-66H)

    VX800 / VX820 Series System Programming Manual Programmable Chip Select (PCS) Control (5C-66h) Offset Address: 5D-5Ch (D17F0) PCS 0 I/O Port Address Default Value: 0000h Attribute Default Description 15:0 PCS 0 I/O Port Address Offset Address: 5F-5Eh (D17F0) PCS 1 I/O Port Address Default Value: 0000h Attribute Default...

  • Page 387: Output Control (67H)

    VX800 / VX820 Series System Programming Manual Offset Address: 66h (D17F0) PCS Control Default Value: 00h Attribute Default Description Reserved PCS 3 0: Disable 1: Enable PCS 2 0: Disable 1: Enable PCS 1 0: Disable 1: Enable PCS 0 0: Disable 1: Enable Output Control (67h)

  • Page 388: High Precision Event Timers (Hpet) (68-6Bh)

    VX800 / VX820 Series System Programming Manual High Precision Event Timers (HPET) (68-6Bh) Offset Address: 68h (D17F0) HPET Control Default Value: 00h Attribute Default Description High Precision Event Timers 0: Disable 1: Enable Reserved PCS 3 256-Byte IO Range Decoding Enable 0: Disable 1: Enable PCS 2 256-Byte IO Range Decoding Enable...

  • Page 389: Isa Decoding Control (6C-6Fh)

    VX800 / VX820 Series System Programming Manual ISA Decoding Control (6C-6Fh) Offset Address: 6Ch (D17F0) ISA Positive Decoding Control 1 Default Value: 00h Attribute Default Description On-Board I/O (Ports 00-FFh) Positive Decoding 0: Disable 1: Enable Microsoft-Sound System I/O Port Positive Decoding 0: Disable 1: Enable (bits 5-4 determine the decode range) Microsoft-Sound System I/O Decode Range...
  • Page 390 VX800 / VX820 Series System Programming Manual Offset Address: 6Fh (D17F0) ISA Positive Decoding Control 4 Default Value: 00h Attribute Default Description SPI Positive Decoding Control 0: Disable 1: Enable LPC TPM Positive Decoding 0: Disable 1: Enable PCS2# and PCS3# Positive Decoding 0: Disable 1: Enable I/O Port 0CF9h Positive Decoding...

  • Page 391: Pci I/O Cycle Control (74-7Fh)

    VX800 / VX820 Series System Programming Manual PCI I/O Cycle Control (74-7Fh) Offset Address: 74h (D17F0) PCI I/O Cycle Control Default Value: 00h Attribute Default Description Forward Card Reader DMA Cycles to the External PCI Bus 0: Disable 1: Enable Forward SDIO DMA Cycles to the External PCI Bus 0: Disable 1: Enable...
  • Page 392 VX800 / VX820 Series System Programming Manual Offset Address: 77h (D17F0) Firmware Memory IDSEL 2 Default Value: 00h Attribute Default Description 0000 Firmware Memory IDSEL for the Two 1MB Memory Ranges {FF700000h-FF7FFFFFh, FF300000h- FF3FFFFFh} 0000: IDSEL0 … 1111: IDSEL15 0000 Firmware Memory IDSEL for the Two 1MB Memory Ranges {FF600000h-FF6FFFFFh, FF200000h- FF2FFFFFh} 0000: IDSEL0...
  • Page 393 VX800 / VX820 Series System Programming Manual Offset Address: 7Eh (D17F0) Firmware Memory IDSEL 5 Default Value: 00h Attribute Default Description Firmware Memory IDSEL for the Two 512K Memory Ranges {FFE80000h-FFEFFFFFh, FFA80000h- FFAFFFFFh} 0000: IDSEL0 … 1111: IDSEL15 Firmware Memory IDSEL for the Two 512K Memory Ranges {FFE00000h-FFE7FFFFh, FFA00000h- FFA7FFFFh} 0000: IDSEL0 …...

  • Page 394: Power Management-Specific Configuration Registers (80-Cfh)

    VX800 / VX820 Series System Programming Manual Power Management-Specific Configuration Registers (80-CFh) Offset Address: 80h (D17F0) PM General Configuration 1 Default Value: 00h Attribute Default Description Reserved Enable GPIO7 (THRMTRIP#) as SLPBTN# 0: Disable 1: Enable Power Button De-bounce 0: Disable 1: Enable Reserved Microsoft Sound Monitor in Audio Access...
  • Page 395 VX800 / VX820 Series System Programming Manual Offset Address: 82h (D17F0) ACPI Interrupt Select Default Value: 40h Attribute Default Description ATX / AT Power Indicator 0: ATX 1: AT PSON (SUSC#) Current State 0: PSON Gating Active 1: PSON Gating Complete During system on/off, this status bit reports whether PSON gating state has been completed, 0 meaning that gating is active now and 1 meaning that gating is complete.
  • Page 396 VX800 / VX820 Series System Programming Manual Offset Address: 85-84h (D17F0) IRQn as Primary Interrupt Default Value: 0000h If an IRQ is enabled as a Primary IRQ, its assertion can be used as a wakeup event in system power management. This register is used in conjunction with: •...
  • Page 397 VX800 / VX820 Series System Programming Manual Offset Address: 87-86h (D17F0) IRQn as Secondary Interrupt Default Value: 0000h This register is used in conjunction with: • PMIO Rx28[1]–Secondary Event Timer Timeout Status • PMIO Rx2A[1]–SMI on Secondary Event Timer Timeout Secondary IRQ is different from Primary IRQ in systems that resume due to a Secondary IRQ event can return to the suspend state after the secondary event timer times out.
  • Page 398 VX800 / VX820 Series System Programming Manual Offset Address: 8Ah (D17F0) Auto-Switching Processor Power State Default Value: 00h Attribute Default Description Reserved C2 to C3 / C4 Auto Mode 0: Processor power state will not be auto-switched from C2 to the previous C3 or C4 state. 1: In C2 state, if no bus master activity after a period of time, it will return to the previous C3 or C4 state.
  • Page 399 VX800 / VX820 Series System Programming Manual Offset Address: 8Ch (D17F0) Host Power Management Control Default Value: 07h Attribute Default Description 0000b Thermal Duty Cycle This field determines STPCLK# duty cycle when the THRM# signal is asserted. The duty cycle of STPCLK#, if not activated by the assertion of THRM#, is controlled by PMIO Rx10[3:0].
  • Page 400 VX800 / VX820 Series System Programming Manual Offset Address: 8Dh (D17F0) Throttle / Clock Stop Control Default Value: 00h Attribute Default Description Throttle Timer Reset Write 1 to reset the throttle timer. Throttle Timer Counter Width This field determines the counter width of the throttle timer, which in conjunction with the throttle timer tick determines the cycle time of STPCLK#.
  • Page 401 VX800 / VX820 Series System Programming Manual Offset Address: 93-90h (D17F0) Power Management Timer Control Default Value: 0000 0000h Attribute Default Description 31:30 Power Conserve Mode Timer Period 00: 1/16 second 01: 1/8 second 10: 1 second 11: 1 minute RW1C Power Conserve Mode Status This bit reads 1 when in Conserve Mode...
  • Page 402 VX800 / VX820 Series System Programming Manual Offset Address: 94h (D17F0) Miscellaneous Configuration 1 (Power Well) Default Value: 88h Attribute Default Description SMBus Clock Select 0: SMBus from divider of 14.318 Mhz 1: SMBus from RTC clock Note: If set, SMBus always uses RTC clock. If not set, SMBus uses RTC clock in suspend mode and uses 128K when RxD2[2] is set.
  • Page 403 VX800 / VX820 Series System Programming Manual Offset Address: 96h (D17F0) Miscellaneous Configuration 3 (Battery Well) Default Value: 0Fh Attribute Default Description Reserved Always reads 0. Reserved Enable SMB GPOUT6 and GPOUT7 as PWRGD and PWRBTN Enable ASF function. Used by Alert-on-LAN to reset the system. CPU Frequency Strapping Value Output through NMI, INTR, IGNNE#, and A20M# during RESET#.
  • Page 404 VX800 / VX820 Series System Programming Manual Offset Address: 98h (D17F0) GP2 / GP3 Timer Control Default Value: 10h Attribute Default Description GP3 Timer Start When set to 1, the GP3 timer loads the value specified by Rx9A and starts counting down. The GP3 timer is reloaded at the occurrence of certain events enabled in the GP Timer Reload Enable Register (PMIO Rx38).
  • Page 405 VX800 / VX820 Series System Programming Manual Offset Address: 9Ch (D17F0) ASF Byte Write Command Default Value: 00h Attribute Default Description Command Decode Table 00h: Reserved 01h: Generate ASF wakeup event and SCI or SMI event PMIO Rx3A[0]: SCI enable, PMIO Rx3B[0]: SMI enable. 02h: Unconditional Power Down 03h: System Reset 04h: Power Cycle Reset...

  • Page 406: Uart / Fir Misc Control Registers (B0-Bfh)

    VX800 / VX820 Series System Programming Manual UART / FIR Misc Control Registers (B0-BFh) Offset Address: B0h (D17F0) UART and FIR Control Default Value: 08h Attribute Default Description UART2 MIDI Mode Enable 0: Disable 1: Enable UART1 MIDI Mode Enable 0: Disable 1: Enable UART 2...
  • Page 407 VX800 / VX820 Series System Programming Manual Offset Address: B6h (D17F0) FIR I/O Base Address Default Value: 00h Attribute Default Description FIR IO Base Address A[15:8] Offset Address: B7h (D17F0) COM Control Default Value: 00h Attribute Default Description Reserved Enable UART DMA I/O Cycle Positive Decoding 0: Disable 1: Enable Enable UART DMA Function...
  • Page 408 VX800 / VX820 Series System Programming Manual Offset Address: BBh (D17F0) COM2 DMA Channel Control Default Value: 00h Attribute Default Description Reserved 000b COM2 Receive DMA Channel Select 000: No channel selected 100: DMA channel 0 101: DMA channel 1 110: DMA channel 2 111: DMA channel 3 Others: reserved...

  • Page 409: System Management Bus-Specific Configuration Registers (D0-E7H)

    VX800 / VX820 Series System Programming Manual Offset Address: C3-C0h (D17F0) Power Management Capability Default Value: 0002 0001h Attribute Default Description 31:16 0002h Power Management Capability 0002h indicates that: This function does not support D2 or D1 power state. This function does not require PCI clock to generate PME#. This function complies with PCI Power Management Interface Specification Revision 1.1.
  • Page 410 VX800 / VX820 Series System Programming Manual Offset Address: D4h (D17F0) SMBus Slave Address for Port 1 Default Value: 00h Attribute Default Description SMBus Slave Address for Port 1 Read / Write for Shadow Port 1 Offset Address: D5h (D17F0) SMBus Slave Address for Port 2 Default Value: 00h Attribute...
  • Page 411 VX800 / VX820 Series System Programming Manual Offset Address: E3h (D17F0) Pullup Option Default Value: 03h Attribute Default Description PCIe Hot Plug Wakeup in S1 State 0: Not supported 1: Supported VR Change Timer Select 0: 7.5 us 1: 45us Enable SDIO Device 2 Break Event 0: Disable 1: Enable...

  • Page 412: Table 29. C3 Latency Configuration Table

    VX800 / VX820 Series System Programming Manual Table 29. C3 Latency Configuration Table RxEC[2] RxE4[7] STOP GRANT SLP# 1->0 Break Event CPUSTP# 0->1 SLP# 0->1 to SLP# 1->0 to CPUSTP# 1->0 to CPUSTP# 0->1 to SLP# 0->1 to STPCLK# 0->1 7.5~15 us 8~11.25 us 7.5~15 us...

  • Page 413: Table 30. C4 Latency Configuration Table

    VX800 / VX820 Series System Programming Manual Table 30. C4 Latency Configuration Table RxEC[2] RxE4[7] STOP GRANT SLP# 1->0 CPUSTP# 1->0 Break Event VRDSLP 1->0 CPUSTP# 0->1 SLP# 0->1 SLP# 0->1 SLP# 1->0 CPUSTP# 1->0 VRDSLP 0->1 VRDSLP 1->0 CPUSTP# 0->1 STPCLK# 0->1 7.5~15 us 8~11.25 us...
  • Page 414 VX800 / VX820 Series System Programming Manual Offset Address: E5h (D17F0) Multi Function Select 2 Default Value: 01h Attribute Default Description C4 VR Recovery Latency Selection Bit VRDSLP de-assertion to DPSLP de-assertion latency. In detail, please refer to C3/C4 latency configuration tables. RxE5[7] / RxE3[6] VR Change Timer 90~100 us...
  • Page 415 VX800 / VX820 Series System Programming Manual Offset Address: E7h (D17F0) Cx State Break Event Enable 2 Default Value: 00h Attribute Default Description Enable APIC Cycle Reflect to ALL Bus Master Activity Effective Signal 0: Disable 1: Enable HD Audio Record FIFO Status Reflect Control Enable HD audio record FIFO not empty signal reflect to HD/PCI DMA bus master activity effective signal if HDAC break event enable is set.

  • Page 416: Watchdog Timer Registers (E8-Ffh)

    VX800 / VX820 Series System Programming Manual Watchdog Timer Registers (E8-FFh) Offset Address: EB-E8h (D17F0) Watchdog Timer Memory Base Default Value: 0000 0000h Attribute Default Description 31:8 Watchdog Timer Memory Base Hardwire to 0. 0: Memory base address Offset Address: ECh (D17F0) Watchdog Timer Control &...

  • Page 417: Acpi Io Space Registers (Pmio 00-0Bh)

    VX800 / VX820 Series System Programming Manual ACPI IO Space Registers (PMIO 00-0Bh) Offset Address: 01-00h (PMIO) Power Management Status Default Value: 0000h The bits in this register are set by hardware and can be reset by software by writing a one to the desired bit position. Attribute Default Description...
  • Page 418 VX800 / VX820 Series System Programming Manual Offset Address: 03-02h (PMIO) Power Management Enable Default Value: 0100h The bit, which is defined in this register, corresponds to the bit in the same location of the Power Management Status Register at offset 1-0. Attribute Default Description...
  • Page 419 VX800 / VX820 Series System Programming Manual Offset Address: 05-04h (PMIO) Power Management Control Default Value: 0000h Attribute Default Description Soft Resume This bit is used to allow a system using an AT power supply to operate as if an ATX power supply were being used. Refer to the BIOS Porting Guide for implementation details.

  • Page 420: Processor Power Management Registers (Pmio 10-16H)

    VX800 / VX820 Series System Programming Manual Processor Power Management Registers (PMIO 10-16h) Offset Address: 13-10h (PMIO) Processor Control Default Value: 0000 0000h Attribute Default Description 31:5 Reserved Throttling Enable Setting this bit starts clock throttling (modulating the STPCLK# signal) regardless of the CPU state. Its duty cycle is determined by bits 3-0 of this register.

  • Page 421: General Purpose Power Management Registers (Pmio 20-52H)

    VX800 / VX820 Series System Programming Manual General Purpose Power Management Registers (PMIO 20-52h) Offset Address: 21-20h (PMIO) General Purpose Status Default Value: 0000h Attribute Default Description RW1C North Module SERR# Status RW1C USB Wake-Up in Suspend For suspend states: STR / STD / Soft off. RW1C HDAC Wake-Up Status Can be set only in suspend mode.
  • Page 422 VX800 / VX820 Series System Programming Manual Offset Address: 23-22h (PMIO) General Purpose SCI / RESUME Enable Default Value: 0000h Attribute Default Description Enable SCI on North Module SERR Event 0: Disable 1: Enable Enable SCI on USB Wake-up Event Enable SCI on HDAC Wake-up Event Enable SCI on BATLOW# Event Enable SCI on LID# Event...
  • Page 423 VX800 / VX820 Series System Programming Manual Offset Address: 26h (PMIO) Processor Control Default Value: 00h Attribute Default Description Reserved PCISTP# Assertion while CLKRUN# is De-asserted 0: Assert PCISTP# 1: Not assert PCISTP# (no stop on PCICLK) PCI CLKRUN# Control 0: CLKRUN# is always asserted 1: CLKRUN# will be de-activated after the PCI bus is idle for 26 clocks Host Clock Stop (CPUSTP#) Control...
  • Page 424 VX800 / VX820 Series System Programming Manual Offset Address: 29-28h (PMIO) Global Status Default Value: 0000h Attribute Default Description RW1C GPIO Range 1 Access Status RW1C GPIO Range 0 Access Status RW1C GP3 Timer Time Out Status RW1C GP2 Timer Time Out Status RW1C SERIRQ SMI Status RW1C...
  • Page 425 VX800 / VX820 Series System Programming Manual Offset Address: 2B-2Ah (PMIO) Global Enable Default Value: 0200h Attribute Default Description SMI Enable on GPIO Range 1 Access 0: Disable 1: Enable SMI Enable on GPIO Range 0 Access SMI Enable on GP3 Timer Timeout SMI Enable on GP2 Timer Timeout SMI Enable on SERIRQ SMI SMI Enable on Rx5[5] Write...
  • Page 426 VX800 / VX820 Series System Programming Manual Offset Address: 2D-2Ch (PMIO) Global Control Default Value: 0010h Attribute Default Description 15:11 Reserved IDE Bus Power-Off 0: Disable 1: Enable Reserved RW1C SMI Active Status 0: SMI inactive 1: SMI active. If the SMI Lock bit is set, this bit must be written 1 to clear it before the next SMI can be generated. LID# Triggering Polarity 0: Rising edge 1: Falling edge...
  • Page 427 VX800 / VX820 Series System Programming Manual Offset Address: 33-30h (PMIO) Primary Activity Detect Status Default Value: 0000 0000h The Primary Activity Detect Status bits have one-to-one correspondence to the Primary Activity Detect Enable bits in Rx37-34. If the corresponding bit is set in the Enable register, setting of a bit in the Status register will cause the Primary Activity Status (PMIO Rx28[0]) bit to be set.
  • Page 428 VX800 / VX820 Series System Programming Manual Offset Address: 37-34h (PMIO) Primary Activity Detect Enable Default Value: 0000 0000h The Primary Activity Detect Enable bits have one-to-one correspondence to the Primary Activity Detect Status bits in Rx33-30. Setting of any of Status bits also sets the Primary Activity Status (PMIO Rx28[0]) bit which causes the GP0 timer to be reloaded (if the Primary Activity GP0 Enable bit is set) or generates an SMI (if Primary Activity Enable is set).
  • Page 429 VX800 / VX820 Series System Programming Manual Offset Address: 38h (PMIO) GP Timer Reload Enable Default Value: 00h All bits in this register default to 0 on power up. Attribute Default Description GP1 Timer Reload on KBC Access 0: Normal GP1 Timer Operation 1: Setting of PMIO Rx30[9] causes the GP1 timer to reload.
  • Page 430 VX800 / VX820 Series System Programming Manual Offset Address: 40h (PMIO) Extend SMI/IO Trap Status Default Value: 00h Attribute Default Description Reserved RW1C BIOS Write Access Status RW1C GP3 Timer Second Timeout With No Cycles 0: No cycles occurred in between GP3 timer 2 time out and reset assertion.
  • Page 431 VX800 / VX820 Series System Programming Manual Offset Address: 4B-48h (PMIO) General Purpose Input Status Default Value: ― Attribute Default Description Reserved 31:24 23:0 General Purpose Input ― Bit 0: GPI0 Bit 1: GPI1 Bit 2: GPI2 Bit 3: GPI3 Bit 4: GPI4 Bit 5: GPI5 Bit 6: GPI6...
  • Page 432 VX800 / VX820 Series System Programming Manual Offset Address: 50h (PMIO) GPI Change Status Default Value: 00h Attribute Default Description RW1C Pin Change Status Bit 0: PEPMESGPI2 Bit 1: PEHPSGPI3 Bit 2: GPIO0 Bit 3: GPIO1 Bit 4: GPIO10 Bit 5: GPIO11 Bit 6: GPIO12 Bit 7: GPIO13 Notes for PEPMESGPI2 and PEHPSGPI3:...

  • Page 433: Io Trap Registers (Pmio 54-69H)

    VX800 / VX820 Series System Programming Manual IO Trap Registers (PMIO 54-69h) Offset Address: 57-54h (PMIO) I/O Trap PCI Data Default Value: ― Attribute Default Description 31:0 PCI Data During I/O Trap SMI ― Offset Address: 59-58h (PMIO) I/O Trap PCI I/O Address Default Value: ―...
  • Page 434 VX800 / VX820 Series System Programming Manual Offset Address: 60h (PMIO) C4P State Event Enable Default Value: 00h All bits in this register default to 0 on power up. Attribute Default Description Enable to Support PLL Off State during C4 State If this bit is set to 1, the bus master monitor timer is enabled.
  • Page 435 VX800 / VX820 Series System Programming Manual Offset Address: 64h (PMIO) C4P State SATA and USB Related Enable Default Value: 00h All bits in this register default to 0 on power up. Attribute Default Description Turn Off USB PHY 120MHz PLL 0: Disable 1: Enable USB Wake Up Event for C4P State...
  • Page 436 VX800 / VX820 Series System Programming Manual Offset Address: 66h (PMIO) C4P State NM and HDAC Related Enable Default Value: 00h All bits in this register default to 0 on power up. Attribute Default Description Enable HDAC Master Reset Bus Master Idle Timer 0: Ignore HDAC master reset bus master idle time.
  • Page 437 VX800 / VX820 Series System Programming Manual Offset Address: 68h (PMIO) C4P State Other Devices Related Enable Default Value: 00h All bits in this register default to 0 on power up. Attribute Default Description Enable PCI Master Reset Bus Master Idle Timer 0: Disable 1: Enable RW1C...

  • Page 438: Watchdog Timer Memory Base (Pm-Mmio 00-07H)

    VX800 / VX820 Series System Programming Manual Watchdog Timer Memory Base (PM-MMIO 00-07h) The memory base address for these registers is defined in RxEB-E8h of the D17F0 PCI configuration registers. Offset Address: 03-00h (PM-MMIO) Watchdog Control / Status Default Value: 0000 0000h Attribute Default Description...

  • Page 439: System Management Bus I/O Space Registers (Smio 00-0Fh)

    VX800 / VX820 Series System Programming Manual System Management Bus I/O Space Registers (SMIO 00-0Fh) The base address for these registers is defined in RxD1-D0 of the D17F0 PCI configuration registers. The System Management Bus I/O space is enabled for access by the system if D17F0 RxD2[0] = 1. Offset Address: 00h (SMIO) SMBus Host Status Default Value: 00h...
  • Page 440 VX800 / VX820 Series System Programming Manual Offset Address: 01h (SMIO) SMBus Slave Status Default Value: 00h Attribute Default Description RW1C SMB GPIO Slave PEC Error 0: SMBus GPIO slave PEC calculation is correct. 1: SMBus GPIO slave PEC calculation is error. This bit is only set by hardware and can be cleared by writing a 1 to this bit position.
  • Page 441 VX800 / VX820 Series System Programming Manual Offset Address: 02h (SMIO) SMBus Host Control Default Value: 00h Attribute Default Description PEC Enable 0: Disable 1: Enable SMBus Host to support PEC calculation. Start 0: Write 0 has no effect 1: Start Execution of Command Write 1 to this bit causes the SMBus controller host interface to initiate execution of the command in the SMBus Command Protocol field (bits 5-2).
  • Page 442 VX800 / VX820 Series System Programming Manual Offset Address: 05h (SMIO) SMBus Host Data 0 Default Value: 00h The contents of this register are transmitted in the Data 0 field of SMBus host transaction writes. On reads, Data 0 byte is stored here. Attribute Default Description...
  • Page 443 VX800 / VX820 Series System Programming Manual Offset Address: 08h (SMIO) SMBus Slave Control Default Value: 00h Attribute Default Description SMBus GPIO Slave PEC Enable 0: Disable 1: Enable SMBus GPIO Slave to support PEC calculation. SMBus Host Slave PEC Enable 0: Disable 1: Enable SMBus Host Slave to support PEC calculation.
  • Page 444 VX800 / VX820 Series System Programming Manual Offset Address: 0D-0Ch (SMIO) SMBus Slave Data Default Value: 0000h This register is used to store data values for external SMBus master accesses to the shadow ports or the SMBus host controller’s slave port. Attribute Default Description...

  • Page 445: Spi Controller

    VX800 / VX820 Series System Programming Manual SPI Controller SPI controller is connected to the LPC controller. All registers are memory-mapped and the base address are located in D17F0 RxBEh~RxBCh of the LPC controller. SPI Memory-Mapped Base Address (SPIBAR) = D17F0 RxBEh~RxBCh [23:0] << 8 Offset Address: 01-00h (SPI-MMIO) SPI Status (SPIS) Default Value: 0000h...
  • Page 446 VX800 / VX820 Series System Programming Manual Offset Address: 03-02h (SPI-MMIO) SPI Control (SPIC) Default Value: 4005h Attribute Default Description SPI SMI# Enable 0: Disable 1: Enable The SPI asserts an SMI# request whenever Rx0[2] Cycle Done Status bit is 1. DATA Cycle 0: No data is delivered for this cycle.
  • Page 447 VX800 / VX820 Series System Programming Manual Offset Address: 07-04h (SPI-MMIO) SPI Address (SPIA) Default Value: 0000 0000h Attribute Default Description 31:24 Reserved 23:0 SPI Cycle Address <SCA> This field is shifted out as the SPI Address (MSb first). Bit[23:0] correspond to Address bit[23:0]. Offset Address: 0F-08h (SPI-MMIO) SPI Data 0 Register (SPID0) Default Value: 0h...
  • Page 448 VX800 / VX820 Series System Programming Manual Offset Address: 53-50h (SPI-MMIO) BIOS Base Address (BBAR) Default Value: 0000 0000h Attribute Default Description 31:24 Reserved 23:8 Bottom of System Flash This field determines the bottom of the System BIOS. The chip will not run programmed commands nor memory reads whose address field is less than this value.
  • Page 449 VX800 / VX820 Series System Programming Manual Offset Address: 5F-58h (SPI-MMIO) Opcode Menu Configuration (OPMENU) Default Value: 0 Attribute Default Description 63:56 Opcode 7 (See the description for bit[7:0].) 55:48 Opcode 6 (See the description for bit[7:0].) 47:40 Opcode 5 (See the description for bit[7:0].) 39:32 Opcode 4...
  • Page 450 VX800 / VX820 Series System Programming Manual Offset Address: 6Ch (SPI-MMIO) Clock Divider Default Value: 02h Attribute Default Description SPI Master Clock Divider Value 02h to indicate 8 MHz. The exact frequency: 33/2^n MHZ n = value (Rx6C) Offset Address: 6Dh (SPI-MMIO) Miscellaneous Control Default Value: 00h Attribute...

  • Page 451: Device 17 Function 7 (D17F7): South-North Module Interface Control

    VX800 / VX820 Series System Programming Manual Device 17 Function 7 (D17F7): South-North Module Interface Control This configuration is provided to facilitate the configuration of the North Module Interface logic of the South Module (“SM”) without requiring new enumeration code. This function is represented as Device 17, Function 7. PCI Configuration Space Header (00-3Fh) Offset Address: 01-00h (D17F7) Vendor ID...
  • Page 452 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D17F7) PCI Status Default Value: 0200h Attribute Default Description RW1C Detected Parity Error Set by PERRS, reset by writing 1. RW1C Detected SERR# Note: Set if ECC error RW1C Received Master-Abort (except special cycle) 0: No abort received 1: Transaction aborted by the Master RW1C...

  • Page 453: South -North Module Interface Control (40-5F)

    VX800 / VX820 Series System Programming Manual Offset Address: 0Eh (D17F7) Header Type Default Value: 00h Attribute Default Description Header Type It adheres to the PCI-PCI Bridge Configuration. Offset Address: 0Fh (D17F7) Built In Self Test (BIST) Default Value: 00h Attribute Default Description...
  • Page 454 VX800 / VX820 Series System Programming Manual Offset Address: 4Fh (D17F7) South-North Module Interface Control Default Value: 00h Attribute Default Description Reserved Enable P2P Bridge Header for External PCI Bus 0: Disable 1: Enable Reserved Hide C2P (CPU to PCI) Cycle for Internal Devices on PCI BUS When Bit[6] set to 1, only cycles which act with external PCI devices will appear on PCI Bus.
  • Page 455 VX800 / VX820 Series System Programming Manual Offset Address: 51h (D17F7) P2P Bridge Related Control Default Value: 00h Attribute Default Description Enable Subtract Decode for P2P Cycle 0: Disable 1: Enable Reserved Enable PCI Master Function 0: Enable PCI master function by D19F0 Rx04[2] 1: Enable PCI master function even when D19F0 Rx04[2] is disabled.

  • Page 456: Dram Configuration (60H)

    VX800 / VX820 Series System Programming Manual Offset Address: 54h (D17F7) CCA REQ Timing Option Default Value: 00h Attribute Default Description Reserved Synchronize Card Reader REQ for Better Timing 0: Use original REQ 1: Synchronize REQ before using Synchronize SDIO REQ for Better Timing 0: Use original REQ 1: Synchronize REQ before using Synchronize IDE REQ for Better Timing...

  • Page 457: Shadow Ram Control (61-64H)

    VX800 / VX820 Series System Programming Manual Shadow RAM Control (61-64h) Offset Address: 61h (D17F7) Page-C ROM Shadow Control Default Value: 00h Attribute Default Description CC000-CFFFFh Memory Space Access Control 00: Read / Write Disable 01: Write Enable 10: Read Enable 11: Read / Write Enable C8000-CBFFFh Memory Space Access Control (See Bit[7:6] for bit value descriptions.)

  • Page 458: Conventional Pci Bus Control (70-7Fh)

    VX800 / VX820 Series System Programming Manual Conventional PCI Bus Control (70-7Fh) Offset Address: 70h (D17F7) CPU to PCI Flow Control – 1 Default Value: 00h Attribute Default Description CPU to PCI Post-Write 0: Disable 1: Enable C2P posted cycle could be delayed by PCI master cycles (i.e. PCI master access is allowed even if C2P buffer is not flushed).
  • Page 459 VX800 / VX820 Series System Programming Manual Offset Address: 72h (D17F7) PCI P2C Read Caching and Prefetch Control Default Value: 00h Attribute Default Description No Arbitration on PCI Bus during PCI-DMA Period 0: Disable 1: Enable Reserved Conservative Read Caching 0: Disable 1: Enable When set to 1, the previous prefetched data will be flushed when PCI master changes or starting address is not...
  • Page 460 VX800 / VX820 Series System Programming Manual Offset Address: 75h (D17F7) PCI Arbitration 1 Default Value: 00h Attribute Default Description Arbitration Mode 0: REQ-based (arbitrate at the end of REQ#) 1: Frame-based (arbitrate as FRAME# asserts) PCI Bus Time Slice Bit[2:0] for CPU as A Master (in unit of PCI clocks) Disable PCI Master Time-out / Enable New Grant Mechanism 0: Enable PCI Master time-out / disable new grant mechanism 1: Disable PCI Master time-out / enable new grant mechanism...
  • Page 461 VX800 / VX820 Series System Programming Manual Offset Address: 7Ah (D17F7) PCI V2X Device Capability Default Value: 00h Attribute Default Description PREQ's Device Is Capable of V2X Internal devices pass to PCI bus in V2X mode. 0: Not support V2X mode 1: Support V2X mode REQ6's Device Is Capable of V2X 0: Not support V2X mode...

  • Page 462: Hdac Control (D0-Dfh)

    VX800 / VX820 Series System Programming Manual HDAC Control (D0-DFh) Offset Address: D0h (D17F7) – Reserved Offset Address: D1h (D17F7) HDAC and P2P Related Default Value: 00h Attribute Default Description Reserved Enable the Capability / Status Write of the P2P Bridge Configuration Capability 0: Disable 1: Enable Disable HDAC...
  • Page 463 VX800 / VX820 Series System Programming Manual Offset Address: E2h (D17F7) Dynamic Clock Control 3 Default Value: 1Fh Attribute Default Description Reserved Downstream Interface Clock Control 0: New dynamic clock scheme in this chip 1: Free run PCI1 Clock Control 0: New dynamic clock scheme in this chip 1: Free run Downstream HDAC Clock Control...

  • Page 464: Dram Above 4G Support (E4-Ffh)

    VX800 / VX820 Series System Programming Manual DRAM Above 4G Support (E4-FFh) Offset Address: E4h (D17F7) Low Top Address - Low Default Value: 00h Attribute Default Description Low Top Address – [23:20] DRAM Granularity (Powell) Total DRAM Bit[3:0] Less than Granularity 128M 256M...

  • Page 465: Device 19 Function 0 (D19F0): Pci To Pci Bridge

    VX800 / VX820 Series System Programming Manual Device 19 Function 0 (D19F0): PCI to PCI Bridge * VX820 Series does not support PCI. PCI Configuration Space Header (00-3Fh) Offset Address: 01-00h (D19F0) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h VIA Technology ID...
  • Page 466 VX800 / VX820 Series System Programming Manual Offset Address: 07-06h (D19F0) PCI Status Default Value: 0010h Attribute Default Description RW1C Detected Parity Error 0: No parity error detected 1: Error detected in either address or data phase RW1C Detected SERR# RW1C Received Master-Abort (except special cycle) 0: No abort received...
  • Page 467 VX800 / VX820 Series System Programming Manual Offset Address: 0Fh (D19F0) Built In Self Test (BIST) Default Value: 00h Attribute Default Description BIST Support Reserved Offset Address: 10-17h (D19F0) – Reserved Offset Address: 18h (D19F0) Primary Bus Number Default Value: 00h Attribute Default Description...
  • Page 468 VX800 / VX820 Series System Programming Manual Offset Address: 1Eh (D19F0) Secondary Status Register 1 Default Value: 00h Attribute Default Description Fast Back to Back Cycle Reserved 66MHz Capability Reserved Offset Address: 1Fh (D19F0) Secondary Status Register 2 Default Value: 02h Attribute Default Description...
  • Page 469 VX800 / VX820 Series System Programming Manual Offset Add▊461ss: 2F-28h (D19F0) Prefetchable Upper Limit and Base Default Value: 0000 0000 0000 0000h Attribute Default Description 63:36 Prefetchable Upper Limit 32 Bits [31:4] (Not Supported） 35:32 Prefetchable Upper Limit 32 Bits [3:0] 31:4 Prefetchable Upper Base 32 Bits [31:4] (Not Supported) Prefetchable Upper Base 32 Bits [3:0]...
  • Page 470 VX800 / VX820 Series System Programming Manual Offset Address: 40h (D19F0) External PCI Device Enable Control Default Value: 00h Attribute Default Description Reserved Hide AD25 on External PCI Bus when Assert 0: Disable 1: Enable Hide AD24 on External PCI Bus when Assert 0: Disable 1: Enable Hide AD23 on External PCI Bus when Assert...

  • Page 471: Device 20 Function 0 (D20F0) - High Definition Audio Controller (Hdac)

    VX800 / VX820 Series System Programming Manual Device 20 Function 0 (D20F0) - High Definition Audio Controller (HDAC) PCI Configuration Space Header (00-3Fh) Offset Address: 01-00h (D20F0) Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h Vendor ID Offset Address: 03-02h (D20F0) Device ID Default Value: 3288h Attribute...
  • Page 472 VX800 / VX820 Series System Programming Manual Offset Address: 08h (D20F0) Revision ID Default Value: nnh Attribute Default Description Revision ID Offset Address: 0B-09h (D20F0) Class Code Default Value: 04 0300h Attribute Default Description 23:0 040300h Class Code Offset Address: 0Ch (D20F0) Cache Line Size Default Value: 00h Attribute...
  • Page 473 VX800 / VX820 Series System Programming Manual Offset Address: 2D-2Ch (D20F0) Subsystem Vendor ID Default Value: 1106h Attribute Default Description 15:0 1106h Subsystem Vendor ID Offset Address: 2F-2Eh (D20F0) Subsystem ID Default Value: 3288h Attribute Default Description 15:0 3288h Subsystem ID Offset Address: 33-30h (D20F0) Expansion ROM Default Value: 0000 0000h...

  • Page 474: Hdac Pci Extended Configuration Space (40-260H)

    VX800 / VX820 Series System Programming Manual HDAC PCI Extended Configuration Space (40-260h) Offset Address: 40h (D20F0) – Reserved Offset Address: 41h (D20F0) HDAC Control Default Value: 30h Attribute Default Description Reserved HDAC Dynamic Stop 0: Free running 1:Enable dynamic stop clock Offset Address: 42-43h (D20F0) –...
  • Page 475 VX800 / VX820 Series System Programming Manual Offset Address: 53-52h (D20F0) PCI Power Management Capabilities Default Value: C842h Attribute Default Description 15:11 PME# Can Be Generated from D3 and D0 State Indicates the power states in which the function may assert PME#. Bit-15: PME# can be asserted from D3cold Bit-14: PME# can be asserted from D3hot Bit-13: PME# can be asserted from D2...
  • Page 476 VX800 / VX820 Series System Programming Manual Offset Address: 61-60h (D20F0) MSI Capability ID Default Value: 7005h Attribute Default Description 15:8 Point to the Next Capability Structure (PCIe) MSI Capability Offset Address: 63-62h (D20F0) MSI Message Control Default Value: 0080h Attribute Default Description...
  • Page 477 VX800 / VX820 Series System Programming Manual Offset Address: 71-70h (D20F0) PCI Express Capability ID Default Value: 0010h Attribute Default Description 15:8 Capability Link This is the last capability structure of the list. PCI Express Capability Offset Address: 73-72h (D20F0) PCI Express Capability Default Value: 0091h Attribute...
  • Page 478 VX800 / VX820 Series System Programming Manual Offset Address: 103-100h (D20F0) Virtual Channel Enhanced Capability Default Value: 1301 0002h Attribute Default Description 31:20 130h Next Capability Pointer Hardwired to 130h. 19:16 Capability Structure Revision This field is a PCI-SIG defined version number that indicates the version of the capability structure present. Hardwired to 1h to indicate PCIe version 1.1.
  • Page 479 VX800 / VX820 Series System Programming Manual Offset Address: 113-110h (D20F0) VC0 Resource Capability Default Value: 0000 0000h Attribute Default Description 31:0 Hardwired to 0 This field is not valid for endpoint devices. Offset Address: 117-114h (D20F0) VC0 Resource Control Default Value: 8000 00FFh Attribute Default...
  • Page 480 VX800 / VX820 Series System Programming Manual Offset Address: 137-134h (D20F0) Element Self Description Default Value: 0401 0100h Attribute Default Description 31:24 Port Number Hardwired to 04h indicating HDAC controller is assigned as port #5. 23:16 Component ID Hardwired to 01h. 15:8 Number of Link Entries Hardwired to 01h.

  • Page 481: High Definition Audio Controller Memory Mapped I/O Registers (Hdac-Mmio)

    VX800 / VX820 Series System Programming Manual High Definition Audio Controller Memory Mapped I/O Registers (HDAC-MMIO) This section describes the memory mapped HDAC registers. Please refer to High Definition Audio Specification 1.0 for details. Global Capabilities and Control (00-1Bh) Offset Address: 01-00h (HDAC-MMIO) Global Capabilities –...
  • Page 482 VX800 / VX820 Series System Programming Manual Offset Address: 0B-08h (HDAC-MMIO) Global Control – GCTL Default Value: 0000 000nh Attribute Default Description Mnemonic 31:9 Reserved Accept Unsolicited Response Enable UNSOL 0: Unsolicited response from codec are not accepted. 1: Unsolicited response from codec are accepted by the controller. RsvdP Reserved Flush Control...

  • Page 483: Interrupt Control (20-27H)

    VX800 / VX820 Series System Programming Manual Interrupt Control (20-27h) Offset Address: 23-20h (HDAC-MMIO) Interrupt Control – INTCTL Default Value: 0000 0000h Attribute Default Description Mnemonic Global Interrupt Enable 0: Disable 1: Enable device interrupt generation. Controller Interrupt Enable 0: Disable 1: Enable controller’s general interrupt When set to 1, the controller generates an interrupt when the corresponding status bit is set due to a response interrupt, a response buffer overrun, and wake events.

  • Page 484: Hdac Corb (Command Output Ring Buffer) Control (40-4Eh)

    VX800 / VX820 Series System Programming Manual HDAC CORB (Command Output Ring Buffer) Control (40-4Eh) Offset Address: 43-40h (HDAC-MMIO) CORB Lower Base Address – CORBLBASE Default Value: 0000 0000h Attribute Default Description Mnemonic 31:7 CORB Lower Base Address CORBLBASE Lower address of the Command Output Ring Buffer. Reserved Hardwired to 0 for alignment to 128-byte boundary.

  • Page 485: Hdac Rirb (Response Input Ring Buffer) Control (50-5Eh)

    VX800 / VX820 Series System Programming Manual Offset Address: 4Ch (HDAC-MMIO) CORB Control – CORBCTL Default Value: 00h Attribute Default Description Mnemonic Reserved Enable CORB DMA Engine CORBRUN 0: DMA stop 1: DMA run (when read pointer lags write pointer). Software must read the value back. CORB Memory Error Interrupt Enable *CMEIE 0: Disable...
  • Page 486 VX800 / VX820 Series System Programming Manual Offset Address: 59-58h (HDAC-MMIO) RIRB Write Pointer – RIRBWP Default Value: 0000h Attribute Default Description Mnemonic RIRB Write Pointer Reset RIRBWPRST Writes 1 to reset the RIRB Write Pointer to 0. The DMA engine must be stopped prior to resetting the write pointer or DMA transfer may be corrupted.

  • Page 487: Hdac Immediate Command Control (60-69H)

    VX800 / VX820 Series System Programming Manual Offset Address: 5Eh (HDAC-MMIO) RIRB Size – RIRBSIZE Default Value: 42h Attribute Default Description Mnemonic 0100b RIRB Size Capability RIRBSZCAP 0100b indicates 256 entries (2 KB). Reserved RIRB Size RIRBSIZE 00: 2 entries (16 bytes) 01: 16 entries (128 bytes) 10: 256 entries (2 KB) 11: Reserved...

  • Page 488: Dma Position Base Address (70-77H)

    VX800 / VX820 Series System Programming Manual DMA Position Base Address (70-77h) Offset Address: 73-70h (HDAC-MMIO) DMA Position Lower Base Address – DPLBASE Default Value: 0000 0000h Attribute Default Description Mnemonic 31:7 DMA Position Lower Base Address DPLBASE DMA Position Lower Base Unimplemented Bits Hardwired to 0.

  • Page 489: Hdac Stream Descriptors (80-17Fh)

    VX800 / VX820 Series System Programming Manual HDAC Stream Descriptors (80-17Fh) HDAC Stream Descriptor Control (HDAC-MMIO) Default Value: 00 0000h Offset Address 82-80h: Input Stream 0 Offset Address A2-A0h: Input Stream 1 Offset Address C2-C0h: Input Stream 2 Offset Address E2-E0h: Input Stream 3 Offset Address 102-100h: Output Stream 0 Offset Address 122-120h: Output Stream 1 Offset Address 142-140h: Output Stream 2...
  • Page 490 VX800 / VX820 Series System Programming Manual HDAC Stream Descriptor Status (HDAC-MMIO) Default Value: 00h Offset Address 83h: Input Stream 0 Offset Address A3h: Input Stream 1 Offset Address C3h: Input Stream 2 Offset Address E3h: Input Stream 3 Offset Address 103h: Output Stream 0 Offset Address 123h: Output Stream 1 Offset Address 143h: Output Stream 2 Offset Address 163h: Output Stream 3...
  • Page 491 VX800 / VX820 Series System Programming Manual HDAC Stream Descriptor Cyclic Buffer Length (HDAC-MMIO) Default Value: 0000 0000h Offset Address 8B-88h: Input Stream 0 Offset Address AB-A8h: Input Stream 1 Offset Address CB-C8h: Input Stream 2 Offset Address EB-E8h: Input Stream 3 Offset Address 10B-108h: Output Stream 0 Offset Address 12B-128h: Output Stream 1 Offset Address 14B-148h: Output Stream 2...
  • Page 492 VX800 / VX820 Series System Programming Manual HDAC Stream Descriptor FIFO Size (HDAC-MMIO) Offset Address 91-90h: Input Stream 0 Input Stream Default Value: 0060h Offset Address B1-B0h: Input Stream 1 Offset Address D1-D0h: Input Stream 2 Offset Address F1-F0h: Input Stream 3 Offset Address 111-110h: Output Stream 0 Output Stream Default value: 00C0h Offset Address 131-130h: Output Stream 1...
  • Page 493 VX800 / VX820 Series System Programming Manual HDAC Stream Descriptor Format (HDAC-MMIO) Default Value: 0000h Offset Address 93-92h: Input Stream 0 Offset Address B3-B2h: Input Stream 1 Offset Address D3-D2h: Input Stream 2 Offset Address F3-F2h: Input Stream 3 Offset Address 113-112h: Output Stream 0 Offset Address 133-132h: Output Stream 1 Offset Address 153-152h: Output Stream 2 Offset Address 173-172h: Output Stream 3...

  • Page 494: Alias Registers (2030-2167H)

    VX800 / VX820 Series System Programming Manual Stream Descriptor BDL Pointer Upper Base Address (HDAC-MMIO) Default Value: 0000 0000h Offset Address 9F-9Ch: Input Stream 0 Offset Address BF-BCh: Input Stream 1 Offset Address DF-DCh: Input Stream 2 Offset Address FF-FCh: Input Stream 3 Offset Address 11F-11Ch: Output Stream 0 Offset Address 13F-13Ch: Output Stream 1 Offset Address 15F-15Ch: Output Stream 2...

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