Detecting Frame-Sync Pulses, Even In The Reset State; Ignoring Unexpected Frame-Sync Pulses; Frame Frequency; Maximum Frame Frequency - Texas Instruments TMS320VC5501 Reference Manual

2.3.4

Detecting Frame-Sync Pulses, Even in the Reset State

2.3.5

Ignoring Unexpected Frame-Sync Pulses

2.3.6

Frame Frequency

Equation 2−1. Frame Frequency of a McBSP
Frame Frequency +
2.3.7

Maximum Frame Frequency

SPRU592E
The McBSP can send receive and transmit interrupts to the CPU to indicate
specific events in the McBSP. To facilitate detection of frame synchronization,
these interrupts can be sent in response to frame-sync pulses. Set the
appropriate interrupt mode bits to 10b (for reception, RINTM = 10b; for
transmission, XINTM = 10b).
Unlike other serial port interrupt modes, this mode can operate while the
associated portion of the serial port is in reset (such as activating RINT when
the receiver is in reset). In this case, FSRM/FSXM and FSRP/FSXP still select
the appropriate source and polarity of frame synchronization. Thus, even
when the serial port is in the reset state, these signals are synchronized to the
McBSP internal input clock and then sent to the CPU in the form of RINT and
XINT at the point at which they feed the receiver and transmitter of the serial
port. Consequently, a new frame-synchronization pulse can be detected, and
after this occurs the CPU can take the serial port out of reset safely.
The McBSP can be configured to ignore transmit and/or receive
frame-synchronization pulses. To have the receiver or transmitter recognize
frame-sync pulses, clear the appropriate frame-sync ignore bit (RFIG = 0 for
the receiver, XFIG = 0 for the transmitter). To have the receiver or transmitter
ignore frame-sync pulses until the desired frame length or number of words
is reached, set the appropriate frame-sync ignore bit (RFIG = 1 for the
receiver, XFIG = 1 for the transmitter).
The frame frequency
frame-synchronization pulses and is defined as shown by Equation 2−1.
Number of Clock Cycles Between Frame−Sync Pulses
The frame frequency can be increased by decreasing the time between
frame-synchronization pulses (limited only by the number of bits per frame).
As the frame transmit frequency increases, the inactivity period between the
data packets for adjacent transfers decreases to zero.
The minimum number of clock cycles between frame synchronization pulses
is equal to the number of bits transferred per frame. The maximum frame
frequency is defined as shown by Equation 2−2.
is determined by
Clock Frequency
McBSP Operation
Clocking and Framing Data
the period between
2-9