Unipolar Input-Signal Configuration; Adsxx53Evm Onboard Reference And Adsxx53 Device Internal Reference; Bipolar Input Signal Configuration With 2 × V 4 Unipolar Input Signal Configuration; Range - Texas Instruments ADS8353EVM-PDK User Manual

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Figure 3 shows an example where the ADSxx53EVM is configured to support a bipolar input signal with 2
× V range at the J1 (JP1.2) and J2 (JP2.2) analog interface connectors.
ref
Bipolar Input Signal
+2.3 V
0 V
-2.3 V
JP9/JP10 (CLOSED)
Figure 3. Bipolar Input Signal Configuration with 2 × V
2.4

Unipolar Input-Signal Configuration

When jumpers JP9 and JP10 are open, the inverting amplifier (OPA836) is biased at the appropiate
common-mode voltage level to support unipolar signals on the analog interface connectors. In this
configuration, apply a unipolar input signal with FSR / 2 common-mode voltage.
example where the ADSxx53EVM is configured to support a unipolar input signal with 2 × V
J1 (JP1.2) and J2 (JP2.2) analog interface connectors.
Unipolar Input Signal
+4.8 V
2.5 V
0.2 V
JP9/JP10 (OPEN)
2.5

ADSxx53EVM Onboard Reference and ADSxx53 Device Internal Reference

The ADSxx53 dual, simultaneous ADC operates with reference voltages VREF_A and VREF_B present
on pins REFIO_A and REFIO_B, respectively. The ADSxx53 device incorporates two internal individually-
programmable 2.5-V reference sources. Alternatively, the onboard 2.5-V reference, REF5025 (U5), can
also be selected. The reference voltage source is determined by setting bit B6 of the ADC configuration
register. Note that this bit is common to ADC_A and ADC_B. Configure the reference settings on the
ADSxx53EVM-PDK by navigating to the ADSxx53EVM Settings page on the GUI; see
more information. By default, the evaluation module is set up with the onboard external reference source,
with jumpers JP5 and JP6 installed, as shown in
internal reference, make sure to remove jumpers JP5 and JP6 before enabling the internal reference.
SBAU210A – June 2014 – Revised August 2014
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1 k 
1 k 
5 V
J1/J2
-
OPA836
+
+1.25 V
1 k 
1 k 
5 V
J1/J2
-
OPA836
+2.5 V +
Figure 4. Unipolar Input Signal Configuration
Copyright © 2014, Texas Instruments Incorporated
4.8 V
2.5 V
10 
0.2 V
8200 pF
10 
GND or
FSR/2
4.8 V
2.5 V
10 
0.2 V
8200 pF
10 
GND or
FSR/2
Figure 5. If the ADSxx53 must be configured with the
ADS8353EVM-PDK and ADS7853EVM-PDK
EVM Analog Interface
AINP
AINN

range

ref
Figure 4 shows an
range at the
ref
AINP
AINN
Section 6.3 for
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