Adsxx53Evm Analog Interface Input Connections - Texas Instruments ADS8353EVM-PDK User Manual

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AIN_A
SMA J1
Header JP1.2
VREF
AIN_B
SMA J2
Header JP2.2
VREF
Figure 1. ADSxx53EVM Analog Interface Input Connections
Table 1 summarizes the JP1 and JP2 analog interface connections.
Pin Number
JP1.2
JP2.2
Table 2 lists the SMA analog inputs.
Pin Number
J1
J2
SBAU210A – June 2014 – Revised August 2014
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OPA836
Inverting Configuration
AVDD
V
CM
+
-
Optional voltage divider and
OPA836 Buffer
OPA836
Inverting Configuration
AVDD
V
CM
+
-
Optional voltage divider and
OPA836 Buffer
Table 1. JP1 - JP2: Analog Interface Connections
Signal
CHA inverted input. The signal is routed through an OPA836
AIN_A
in the inverting configuration.
CHB inverted input. The signal is routed through an OPA836
AIN_B
in the inverting configuration.
Table 2. SMA Analog Interface Connections
Signal
Channel A inverted input. The signal is routed through an
AIN_A
OPA836 in the inverting configuration
Channel B inverted input. The signal is routed through an
AIN_B
OPA836 in the inverting configuration.
Copyright © 2014, Texas Instruments Incorporated
EVM Analog Interface
AINP-A (Pin 1)
AINM-A (Pin 2)
JP7
AINP-B (Pin 8)
AINM-B (Pin 7)
JP8
Description
Description
ADS8353EVM-PDK and ADS7853EVM-PDK
ADSxx53
5