Evm Analog Interface; Bipolar-Input Signal Configuration; Unipolar-Input Signal Configuration; Analog Inputs - Texas Instruments ADS8339EVM-PDK User Manual

EVM Analog Interface

2 EVM Analog Interface
The ADS8339EVM is designed to easily interface to multiple analog sources. SMA connectors allow the
EVM to have input signals connected through coaxial cables. In addition, the Samtec™ connector
provides a convenient 10-pin, dual-row, header and socket combination at J1. Consult Samtec at
www.samtec.com
are buffered by an
input.
Use appropriate caution when handling these pins.
Connector
Samtec 10 × 2
SMA
2.1

Bipolar-Input Signal Configuration

With JP4 closed, the OPA836 positive input is biased with 1.125 V, created by diving the 4.5-V onboard
reference by four. This bias becomes a 2.25-V offset at the output of the OPA836 that allows input signals
with a 0-V common mode voltage. To keep the OPA836 distortion as low as possible, limit the input signal
swing from –2.15 V to +2.15 V, as shown in
+2.15 V
0 V
±2.15 V
JP4 (CLOSED)
2.2

Unipolar-Input Signal Configuration

With JP4 open, the OPA836 positive input is biased with +2.25 V, created by diving the 4.5-V onboard
reference by two. This bias becomes a 4.5-V offset at the output of the OPA836 that allows input signals
with a 2.25-V common mode voltage. To keep the OPA836 distortion as low as possible, limit the input
signal swing from +0.1 V to +4.4 V, as shown in
4.4 V
2.25 V
0.1 V
JP4 (OPEN)
4
ADS8339EVM-PDK
or call 1-800-SAMTEC-9 for a variety of mating connector options. The analog inputs
OPA836 high-speed operational amplifier in order to properly drive the ADS8339 ADC
Table 1. Analog Inputs
Pin
Number Signal
J1.10 A0(–)
J4 A0(–)
Transfer Function:
AINP = 2.25V ± A0(±)
1 k 1 k
A0 (±)
5 V
±
OPA836
+
+1.125 V
Figure 1. Bipolar-Input Signal Configuration
Transfer Function:
AINP = 4.5 V ± A0(±)
1 k 1 k
A0 (±)
5 V
±
OPA836
+
+2.25 V
Figure 2. Unipolar-Input Signal Configuration
Copyright © 2014–2015, Texas Instruments Incorporated
Table 1 summarizes the pinout for analog interface J1.
Description
CH0 inverted EVM input
CH0 inverted EVM input
Figure 1.
4.4 V
2.25 V
4.7
0.1 V
10 nF
4.7
Figure 2.
2.25 V
4.7
4.7
SBAU233A – October 2014 – Revised November 2015
AINP
AINN
4.4 V
0.1V
AINP
AINN
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