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ADS8381EVM
User's Guide
May 2004
Data Acquistion
SLAU133

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Summary of Contents for Texas Instruments ADS8381EVM

  • Page 1 ADS8381EVM User’s Guide May 2004 Data Acquistion SLAU133...
  • Page 2 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products & application solutions:...
  • Page 3 EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found in the end product incorporating the goods.
  • Page 4 EVM schematic located in the EVM User’s Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated...
  • Page 5 Chapter 3 – Digital Interface Chapter 4 – Power Supply Requirements Chapter 5 – Using the EVM Chapter 6 − ADS8381EVM BOM, Layout, and Schematic Related Documentation From Texas Instruments To obtain a copy of any of the following TI documents, call the Texas Instruments Literature Response Center at (800) 477−8924 or the Product...
  • Page 6 Trademarks TMS320C5000 and TMS320C6000 DSP platforms are trademarks of Texas Instruments Incorporated.
  • Page 7 ..........ADS8381EVM BOM, Layout, and Schematic .
  • Page 8: Table Of Contents

    6−1 ADS8381EVM Bill of Materials ..........
  • Page 9 Chapter 1 EVM Overview This chapter contains the features of the ADS8381EVM. Topic Page Features ............
  • Page 10 Features 1.1 Features Full-featured evaluation board for the high-speed ADS8381 18-bit, single channel, parallel interface, SAR-type analog-to-digital converters. Onboard signal conditioning Onboard reference Input and output digital buffer Onboard decoding for stacking multiple EVMs...
  • Page 11: 2−1 Analog Input Connector

    Chapter 2 Analog Interface The ADS8381 analog-to-digital converter has both a positive and negative analog input pin. Ground for the negative input is provided on the EVM (via SJP3) close the device, or a user-furnished ground wire may be attached. The negative input pin has a range of –200 mV up to 200 mV, and is shorted on the EVM via SJP3.
  • Page 12: Input Buffer Circuit

    The factory recommends the analog input to any SAR-type converter be buffered and low-pass filtered. It is important to note that the input buffer circuit of the ADS8381EVM, shown in Figure 2−1, uses the THS4031 in an inverting gain-of-one configuration. The amplifier is not stable in a conventional gain-of-one configuration.
  • Page 13: Solder Short Jumper Setting

    Reference 2.2 Reference The ADS8381EVM provides an onboard 4.096-V reference circuit. This reference voltage can be applied directly to the VREF pin of the converter; it does not need to be buffered. The EVM also has provi- sion for a user-supplied external reference voltage. This voltage can be filtered, as needed, by routing the signal through amplifier U1.
  • Page 15: Pinout For Parallel Control Connector P2

    Chapter 3 Digital Interface The ADS8381EVM is designed for easy interfacing to multiple platforms. Samtec part numbers SSW−110−22−F−D−VS−K and TSM−110−01−T−DV−P provide a convenient dual-row-header/socket combination at P2 and P3. Consult Samtec at www.samtec.com or 1−800−SAMTEC−9 for a variety of mating connector options.
  • Page 16: Data Bus Connector P3

    Table 3−2. Jumper Settings Jumper Settings Reference Designator Description 1−2 2−3 † Set A[2..0] = 0x1 to generate RD pulse Installed Not installed Set A[2..0] = 0x2 to generate RD pulse Not installed Installed † CONVST Set A[2..0] = 0x3 to generate pulse Installed Not installed...
  • Page 17: Power Supply Test Points

    Chapter 4 Power Supply Requirements The EVM accepts four power supplies. A dual ±Vs DC supply for the dual supply op amps. Recommend a ±6-VDC supply. A single +5.0-VDC supply for analog section of the board (A/D + Refer- ence). A single +5.0-V or +3.3-VDC supply for digital section of the board (A/D + address decoder + buffers).
  • Page 19 Chapter 5 Using the EVM The ADS8381EVM serves three functions 1) As a reference design 2) As a prototype board and 3) As software test platform Topic Page As a Reference Board .........
  • Page 20 As a Reference Board 5.1 As a Reference Board As a reference design, the ADS8381EVM contains the essential circuitry to showcase the analog-to-digital converter. This essential circuitry includes the input amplifier, reference circuit, and buffers. The EVM analog input circuit is optimized for a 100-kHz sine wave;...
  • Page 21 Chapter 6 ADS8381EVM BOM, Layout, and Schematic This chapter contains the ADS8381EVM bill of materials, the layouts, and the schematic. Topic Page ADS8381EVM Bill of Materials ........
  • Page 22: 6.1 Ads8381Evm Bill Of Materials

    ADS8381EVM Bill of Materials 6.1 ADS8381EVM Bill of Materials Table 6−1 contains a complete bill of materials for the ADS8381EVM. The schematic diagram also is provided for reference. Contact the Product Information Center or send an e−mail to dataconvapps@list.ti.com questions regarding this EVM.
  • Page 23 REF3040 50 ppm/°C, 50 µA in SOT23−3 Instruments CMOS voltage reference ADS8381 Socket Texas ADS8381IPFB ADS8381 18 bit 48QFP Instruments 580 KSPS U5, U6, U7, SN74AHC24 20−TSSOP(P Texas SN74AHC245PWR Octal bus transceiver, 5PWR Instruments 3-state ADS8381EVM BOM, Layout, and Schematic...
  • Page 24 ADS8381EVM Bill of Materials Reference Designator Value Footprint Mfr’s Part Number Description SOIC−8 8−SOP(D) Not installed Not installed Footprint for 8-pin Footprint SOIC reference operates from +5 V. REF3020 3−SOT−23 Not installed Not installed REF3020 50 ppm/°C, 50 µA in SOT23−3...
  • Page 25: Top Layer-Layer

    ADS8381EVM Layout 6.2 ADS8381EVM Layout Figure 6−1. Top Layer—Layer 1 Figure 6−2. Ground Plane—Layer 2 ADS8381EVM BOM, Layout, and Schematic...
  • Page 26: Power Plane-Layer

    ADS8381EVM Layout Figure 6−3. Power Plane—Layer 3 Figure 6−4. Bottom Layer—Layer 4...
  • Page 27 ADS8381EVM Schematic 6.3 ADS8381EVM Schematic The schematic follows this page. ADS8381EVM BOM, Layout, and Schematic...
  • Page 28 Revision History ECN Number Approved Analog-to-Digital Converter 11 12 13 14 15 16 17 18 19 20 EXT_REF Analog Input Power & Digital Buffer TP20 +5VA +5VA TP14 B_DB[17...0] TP18 B_DB[17...0] TP15 B_DB0 B_DB1 +5VA TP19 B_DB2 DGND AGND B_DB3 B_DB4 +3.3VD +5VD...
  • Page 29 Revision History ECN Number Approved EXT_REF +5VCC SJP2 +VCC B_CS +5VCC +5VCC B_CS B_RD B_RD B_CONVST 0.47uF +5VCC B_CONVST B_BYTE B_BYTE 0.1uF B_BUS18/16 0.1uF B_BUS18/16 0.1uF SJP1 0.01uF .01uF REF3040 49.9 +VBD 47uF OPA627 0.1uF 0.01uF 10uF -VCC 0.1uF 0.01uF +5VCC SJP5 +5VCC...
  • Page 30 Revision History ECN Number Approved +5VCC +5VA +5VA BLM21AJ601SN1L + C14 10uF 0.1uF 0.01uF 10uF 1000nF +VBD +VBD B_RD 0.1uF +VBD +BVDD +BVDD BLM21AJ601SN1L B_DB0 + C24 B_DB1 10uF 0.1uF 0.01uF 10uF 1000nF SN74AHC245PWR +VBD +VBD B_RD +VCC 0.1uF BLM21AJ601SN1L B_DB2 B_DB3 + C29...

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