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Memory decoding
The Pentium CPU has a memory address area of 4 Gbyte. The CPU has a
function
64-bit wide data bus, 29 address lines (A3...A31) and 8 bus enable lines
(BD0...BE7) which code the non-existent byte address lines A0, A1 and A2.
The CPU address bus is mapped on the PCI address bus via the TSC (system
controller). Excluded from this are the memory addresses from 0000 0000h
to 0009 FFFFh (640 KB) and from 0010 0000h to 07FF FFFFh (127 Mbyte).
The ISA bridge via the PIIX chip (PCI ISA IDE accelerator) maps the ISA
address bus exactly once on the PCI address bus. The ISA address bus for
8-bit modules covers the address area from A0 to A19, corresponding to the
CPU addresses 0000 0000h to 000F FFFFh (1 Mbyte). For 16-bit ISA
modules, the address bus is extended by the address lines A20...A23 and
therefore addresses from 0000 0000h to 00FF FFFFh (16 MB). The
differentiation between the 1 Mbyte and 16 Mbyte ISA address areas is
achieved using special memory read/write signals which are only activated if
the address lines A20, A21, A22 and A23 have a level of logical "0". If the
CPU addresses areas which are occupied by the main memory, no ISA bus
control signals are generated. This means that an ISA bus module is not
addressed in these memory areas. On the contrary, an ISA bus master cannot
reach addresses above 16 MB. In order to achieve a larger address area for
dual-port RAM extensions than the memory address area between 640 KB
and 1 Mbyte, special decoder hardware is provided on the Pentium
programming device basic module:
PG 760 Programming Device
C79000-G7076-C761-01
The CPU address area from FFF8 0000h to FFFD FFFFh (512k - 128k
BOIS = 384 KB) is mapped into the ISA address area 00F8 0000h to
00FD FFFFh and is always addressed in the CPU address area. Decoding
of the address lines A24 to A31 missing on the ISA bus is achieved using
special hardware on the basic module.
Hardware Information
7-3
7
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