Terasic Altera Cyclone V GX Starter Kit User Manual page 25

disable the JTAG signals on HSMC connector that will form a closed JTAG loop chain on Cyclone
V GX Starter Kit board (See Figure 3-2). Thus, only the on-board FPGA device (Cyclone V GX)
will be detected by the Quartus II programmer. If users want to include another FPGA device or
interface containing FPGA device in the chain via HSMC connector, remove JP2 Jumper (open pin1
and pin2 on JP2) to enable the JTAG signal ports on the HSMC connector.
Figure 3-1 The JTAG chain on Cyclone V GX Starter Kit board
Figure 3-2 The JTAG chain configuration header
The sections below describe the steps to perform both JTAG and AS programming. For both
methods the Cyclone V GX Starter Kit board is connected to a host computer via a USB cable.
Using this connection, the board will be identified by the host computer as an Altera USB Blaster
device.
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