Terasic DE1-SOC User Manual
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Terasic DE1-SOC User Manual

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Summary of Contents for Terasic DE1-SOC

  • Page 2: Table Of Contents

    ...... 39 4.1 Compile Your Design ............39 4.2 Program the FPGA Device ............ 41 4.3 Verify The Hardware ............. 44 Appendix Chapter 5 ......... 47 5.1 Headquarter & Branches ............47 www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 3: Introduction

    This tutorial provides comprehensive information that will help you understand how to create a FPGA design and run it on your DE1-SoC development board. The following sections provide a quick overview of the design flow, explain what you need to get started, and describe what you will learn.

  • Page 4: Before You Begin

    Next step you should installed the USB-BlasterII driver, Plug in the 12-volt adapter to provide power to the board. Use the USB cable to connect the leftmost USB connector on the DE1-SoC board to a USB port on a computer that runs the Quartus II software. Turn on the power switch on the DE1-SoC board.
  • Page 5 Figure 1-3 Driver Software Installation Since the desired driver is not available on the Windows Update Web site, open the Computer Management and select the Device Manager. This leads to the window in Figure 1-4. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 6 Figure 1-4 Device Manager Right click Other devices>Unknown device and select Update Driver Software…This leads to the window in Figure 1-5. Figure 1-5 Update Driver Software www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 7 Figure 1-6 Specify the location of the driver Now, click Browse to get to the pop-up box in Figure 1-7 Find the desired driver, which is at location C:\altera\13.1\quartus\drivers\usb-blaster-ii. Click OK and then upon returning to Figure 1-6.click Next. www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 8: What You Will Learn

    The driver will now be installed as indicated in Figure 1-8 Click close and you can start using the DE1-SoC board. Figure 1-8 The driver is installed In this tutorial you will perform the following tasks: www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 9: Assign The Device

    Of course, you can use your DE1-SoC board to run other designs as well. For the LED design, you will write Verilog HDL code for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as the clock source, and add a 2-input multiplexer megafunction.
  • Page 10 File names, project names, and directories in the Quartus II software cannot contain spaces. d. What is the name of this project? Type my_first_fpga. e. What is the name of the top-level design entity for this project? Type my_first_fpga. See Figure 2-2. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 11 Figure 2-2 Project information f. Click Next. g. You will assign a specific FPGA device to the design and make pin assignments. See Figure 2-3. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 12 Figure 2-3 Specify the Device Example h. Click Finish. When prompted, choose Yes to create the my_first_fpga project directory. You just created your first Quartus II FPGA project. See Figure 2-4. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 13 Figure 2-4 my_first_fpga project www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 14: Design Entry

    When creating your own designs, you can choose any of these methods or a combination of them. Choose File > New > Block Diagram/Schematic File (see Figure 3-1 to create a new file, Block1.bdf, which you will save as the top-level design. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 15 Choose File > Save As and enter the following information.  File name: my_first_fpga  Save as type: Block Diagram/Schematic File (*.bdf) Click Save. The new design file appears in the Block Editor (see Figure 3-2). www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 16 Click OK to create a new file Verilog1.v, which you will save as simple_counter.v. Select File > Save As and enter the following information (see Figure 3-3).  File name: simple_counter.v  Save as type: Verilog HDL File (*.v, *.vlg, *.verilog) www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 17 //It has a single clock input and a 32-bit output port module simple_counter ( CLOCK_50, counter_out input CLOCK_50 ; output [31:0] counter_out; [31:0] counter_out; always @ (posedge CLOCK_50) // on positive clock edge www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 18 Symbol File (.sym).You use this Symbol File to add the HDL code to your BDF schematic. The Quartus II software creates a Symbol File and displays a message (see Figure 3-5). www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 19 BDF. You can move the block after placing it by simply clicking and dragging it to where you want it and releasing the mouse button to place it. See Figure 3-7. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 20 This tutorial design uses a PLL clock source to drive a simple counter. A PLL uses the on-board oscillator (DE1-SoC Board is 50 MHz) to create a constant clock frequency as the input to the counter. To create the clock source, you will add a pre-built LPM megafunction named Altera PLL.
  • Page 21 Figure 3-9): Choose PLL> Altera PLL v13.1. Under Which device family will you be using? Choose the Cyclone V for DE1-SoC development board. Under Which type of output file do you want to create? Choose Verilog HDL. Under What name do you want for the output file? Type pll.v at the end of the already created directory name.
  • Page 22 Figure 3-9 MegaWizard Plug-In Manager [page 2a] Selections In the MegaWizard Plug-In Manager window, make the following selections (see Figure 3-10). The device speed grade choose 6 for DE1-SoC. Set the frequency of the refclk input 50 MHz. www.terasic.com DE1-SoC My First FPGA...
  • Page 23 Figure 3-10 MegaWizard Plug-In Manager Selections Turn off the Enable locked output port option on MegaWizard . As you turn it off, pin disappear from the PLL block’s graphical preview. See Figure 3-11 for an example. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 24 Figure 3-11 MegaWizard Plug-In Manager Selections Then, make the following selection (see Figure 3-12). Desired Frequency www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 25 Figure 3-12 MegaWizard Plug-In Manager Selections 8. Click Finish . It leads to Figure 3-13.Click Exit. Figure 3-13 PLL Generation The Symbol window opens, showing the newly created PLL megafunction. See Figure 3-14. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 26 11. Click OK and place the pll symbol onto the BDF to the left of the simple_counter symbol. You can move the symbols around by holding down the left mouse button, helping you ensure that they line up properly. See Figure 3-15. Figure 3-15 Place the PLL Symbol www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 27 Figure 3-17 Click OK If you need more room to place symbols, you can use the vertical and horizontal scroll bars at the edges of the BDF window to view more drawing space. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 28 Using the Orthogonal Bus tool, draw a bus line connected on one side to the simple_counter output port, and leave the other end unconnected at about 4 to 8 grid spaces to the right of the simple_counter. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 29 BDF schematics, where X is the most significant bit (MSB) and Y is the least significant bit (LSB). Click OK. Figure 3-21 shows the BDF. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 30 Figure 3-20 Change the output BUS name Figure 3-21 BDF www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 31: Add A Multiplexer

    This design uses a multiplexer to route the simple_counter output to the LED pins on the DE1-SoC development board. You will use the MegaWizard Plug-In Manager to add the multiplexer, lpm_mux. The design multiplexes two variations of the counter bus to four LEDs on the DE1-SoC development board.
  • Page 32 Under How ‘wide’ should the data input and result output be? Select 4 (see Figure 3-23). Figure 3-23 lpm_mux settings Click Next. 10. Click Finish twice. The Symbol window appears (see Figure 3-24 for an example). www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 33 13. Add input buses and output pins to the counter_bus_mux symbol as follows: Using the Orthogonal Bus tool, draw bus lines from the data1x[3..0] and data0x[3..0] Input ports to about 8 to 12 grid spaces to the left of counter_bus_mux. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 34 If you have not done so already, save your project file before continuing. 14. Choose Edit > Insert Symbol. 15. Under Libraries, double-click quartus/libraries/ > primitives > pin > output (see Figure 3-27). www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 35 19. Attach an input pin to the multiplexer select line using an input pin: Choose Edit > Insert Symbol. Under Libraries, double-click quartus/libraries/ > primitives > pin > input. Click OK. 20. Place this input pin below counter_bus_mux. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 36 25. Under Libraries, double-click quartus/libraries/ > primitives >logic > not (see Figure 3-30). 26. Click OK. 27. Place this not pin so that it connects to KEY[1] and the pll rst (see Figure 3-31). Figure 3-29 Adding the KEY [1:0] Input Pin www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 37 Text tool on the toolbar (indicated with the A symbol). For example, you can add the label “OFF = SLOW, ON = FAST” to the KEY [0] input pin and add a project description, such as “My First FPGA Project.” www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 38: Assign The Pins

    In the Location column next to each of the seven node names, add the coordinates (pin numbers) as shown in Table 3-1 for the actual values to use with your DE1-SoC board. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 39 Group. Each bank has a distinct color, which corresponds to the top-view wire bond drawing in the upper right window. See Figure 3-33. Figure 3-33 Completed Pin Planning Example Now, you are finished creating your Quartus II design! www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 40: Create A Default Timequest Sdc File

    Choose File > New SDC file. The SDC editor opens. Type the following code into the editor: create_clock -name "CLOCK_50" -period 20.000ns [get_ports {CLOCK_50}] derive_pll_clocks derive_clock_uncertainty Save this file as my_first_fpga.sdc (see Figure 3-34). Figure 3-34 Default SDC www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 41 Naming the SDC with the same name as the top-level file except for the .sdc extension causes the Quartus II software to using this timing analysis file automatically by default. If you used another name, you would need to add the SDC to the assignments file list. www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 42: Compile And Verify Your Design

    In the Processing menu, choose Start Compilation or click the Play button on the toolbar. If you are asked to save changes to your BDF, click Yes. While compiling your design, the Quartus II software provides useful information about the compilation (see Figure 4-1). www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 43 I/O pins used for the LEDs were not set. The software provides the compilation results in the Compilation Report tab as shown in Figure 4-2. www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 44: Program The Fpga Device

    Connect the power supply cable to your board and to a power outlet. For the DE1-SoC board, connect the USB-BlasterII (included in your development kit) to J13 and the USB cable to the USB-BlasterII. Connect the other end of the USB cable to the host computer.
  • Page 45 Figure 4-3 Programmer Window Click Hardware Setup. If it is not already turned on, turn on the DE1-SoC [USB-1] option under currently selected hardware. See Figure 4-4. Figure 4-4 Hardware Setting Click Close. Click Auto Detect to detect all the devices on the JTAG chain.
  • Page 46 Click Yes to match device list. Figure 4-6 Warning for device list not match Both HPS and FPGA will be list on the programmer. Select FPGA device and click Change File a .sof file. www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 47: Verify The Hardware

    Press and hold KEY [0] on the development board and observe that the LEDs advance more quickly. Pressing this KEY causes the design to multiplex using the faster advancing part of the counter (bits [24..21]). www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 48 If other LEDs emit faintness light, Choose Assignments > Device. Click Device and Pin Options. See Figure 4-9. Figure 4-9 Device and Options Choose unused pins. Reserve all unused pins: Choose the As input tri-stated option. See Figure 4-10. www.terasic.com DE1-SoC My First FPGA December 16, 2014...
  • Page 49 In the Processing menu, choose Start Compilation. After the compile, Choose Tools > Programmer. Select the my_first_fpga.sof file from the project directory. Click Start. At this time you could find the other LEDs are unlighted. www.terasic.com DE1-SoC My First FPGA December 16, 2014...

  • Page 50: Appendix

    Chapter 5 Appendix & &  Tel ：+886-3-575-0880  Fax ：+886-3-572-6690  Add：9F, No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, Taiwan 300-70  Email：sales@terasic.com / support@terasic.com www.terasic.com DE1-SoC My First FPGA December 16, 2014...

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