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JSCLR
Operation:
If S[n]=0,
then SP+1 SP; PC SSH; SR SSL; xxxx
else PC+1
PC
I
f S[n]=0,
then SP+1 SP; PC SSH; SR SSL; xxxx PC
else PC+1 PC
If S[n]=0,
then SP+1 SP; PC SSH; SR SSL; xxxx PC
else PC+1 PC
If S[n]=0,
then SP+1 SP; PC SSH; SR SSL; xxxx PC
else PC+1 PC
If S[n]=0,
then SP+1 SP; PC SSH; SR SSL; xxxx PC
else PC+1 PC
If S[n]=0,
then SP+1 SP; PC SSH; SR SSL; xxxx PC
else PC+1 PC
If S[n]=0,
then SP+1 SP; PC SSH; SR SSL; xxxx PC
else PC+1 PC
Description: Jump to the subroutine at the 16-bit absolute address in program memory
specified in the instruction's 24-bit extension word if the n
clear. The bit to be tested is selected by an immediate bit number from 0–23. If the n
of the source operand S is clear, the address of the instruction immediately following the
JSCLR instruction (PC) and the system status register (SR) are pushed onto the system
stack. Program execution then continues at the specified absolute address in the instruc-
tion's 24-bit extension word. If the sepcified memory bit is not clear, the program counter
(PC) is incremented and the extension word is ignored. However, the address register
specified in the effective address field is always updated independently of the state of the
th
n
bit. All address register indirect addressing modes may be used to reference the
A - 90
Freescale Semiconductor, Inc.
Jump to Subroutine if Bit Clear
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Assembler Syntax
JSCLR
#n,X:ea,xxxx
PC
JSCLR
#n,X:aa,xxxx
JSCLR
#n,X:pp,xxxx
JSCLR
#n,Y:ea,xxxx
JSCLR
#n,Y:aa,xxxx
JSCLR
#n,Y:pp,xxxx
JSCLR
#n,S,xxxx
th
bit of the source operand S is
JSCLR
th
bit
MOTOROLA
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