Advertisement
Freescale Semiconductor, Inc.
BSET
Operation:
D[n]
C;
1
D[n]
D[n]
C;
1
D[n]
D[n]
C;
1
D[n]
D[n]
C;
1
D[n]
D[n]
C;
1
D[n]
D[n]
C;
1
D[n]
D[n]
C;
1
D[n]
Description: Test the n
destination location. The state of the n
code register. After the test, the n
tested is selected by an immediate bit number from 0–23. This instruction performs a
read-modify-write operation on the destination location using two destination accesses
before releasing the bus. This instruction provides a test-and-set capability which is use-
ful for synchronizing multiple processors using a shared memory. This instruction can use
all memory alterable addressing modes.
Example:
Before Execution
X:$FFE5
SR
A - 42
Bit Test and Clear
th
bit of the destination operand D, set it, and store the result in the
th
bit is stored in the carry bit C of the condition
th
bit of the destination location is set. The bit to be
:
BSET #$0,X:<<$FFE5;test and clear bit 14 in I/O Port B Data Reg.
:
X:$FFE5
$000000
$0300
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Assembler Syntax:
BSET
#n,X:ea
BSET
#n,X:aa
BSET
#n,X:pp
BSET
#n,Y:ea
BSET
#n,Y:aa
BSET
#n,Y:pp
BSET
#n,D
After Execution
$000001
SR
$0300
BSET
MOTOROLA
Advertisement
