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BCHG
Operation:
D[n]
C;
D[n]
D[n]
D[n]
C;
D[n]
D[n]
D[n]
C;
D[n]
D[n]
D[n]
C;
D[n]
D[n]
D[n]
C;
D[n]
D[n]
D[n]
C;
D[n]
D[n]
D[n]
C;
D[n]
D[n]
Description: Test the n
result in the destination location. The state of the n
condition code register. After the test, the n
mented. The bit to be tested is selected by an immediate bit number from 0–23. This
instruction performs a read-modify-write operation on the destination location using two
destination accesses before releasing the bus. This instruction provides a test-and-
change capability which is useful for synchronizing multiple processors using a shared
memory. This instruction can use all memory alterable addressing modes.
Example:
:
BCHG
#$7,X:<<$FFE2
:
Before Execution
X:$FFE2
SR
A - 32
Freescale Semiconductor, Inc.
Bit Test and Change
th
bit of the destination operand D, complement it, and store the
;test and change bit 7 in I/O Port B DDR
X;$FFE2
$000000
$0300
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
Assembler Syntax:
BCHG
#n,X:ea
BCHG
#n,X:aa
BCHG
#n,X:pp
BCHG
#n,Y:ea
BCHG
#n,Y:aa
BCHG
#n,Y:pp
BCHG
#n,D
th
bit is stored in the carry bit C of the
th
bit of the destination location is comple-
After Execution
$000080
SR
$0300
BCHG
MOTOROLA
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