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Table A-1 Instruction Description Notation (Continued)
<<
I/O Short Addressing Mode Force Operator
<
Short Addressing Mode Force Operator
>
Long Addressing Mode Force Operator
#
Immediate Addressing Mode Operator
#>
Immediate Long Addressing Mode Force Operator
#<
Immediate Short Addressing Mode Force Operator
LF
Loop Flag Bit Indicating When a DO Loop is in Progress
T
Trace Mode Bit Indicating if the Tracing Function has been Enabled
S1, S0
Scaling Mode Bits Indicating the Current Scaling Mode
I1, I0
Interrupt Mask Bits Indicating the Current Interrupt Priority Level
Standard Definitions (Table A - 3 Describes Exceptions)
L
Limit Bit Indicating Arithmetic Overflow and/or Data Shifting/Limiting
E
Extension Bit Indicating if the Integer Portion of A or B is in Use
U
Unnormalized Bit Indicating if the A or B Result is Unnormalized
N
Negative Bit Indicating if Bit 55 of the A or B Result is Set
Z
Zero Bit Indicating if the A or B Result Equals Zero
V
Overflow Bit Indicating if Arithmetic Overflow has Occurred in A or B
C
Carry Bit Indicating if a Carry or Borrow Occurred in A or B Result
ory addressing modes and alterable addressing modes. Thus, memory alterable
addressing modes use address register indirect and absolute addressing modes.
The address register indirect addressing modes require that the offset register number
be the same as the address register number. However, future family members may allow
the offset register number to be different from the address register number. The assem-
bler syntax ''Nn'' supports the future feature. The assembler syntax ''N'' may be used
A - 6
Freescale Semiconductor, Inc.
Addressing Mode Operators
Mode Register (MR) Symbols
Condition Code Register (CCR) Symbols
DSP56000/DSP56001 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
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